JPH06197877A - Bioelectric signal extracting device - Google Patents

Abstract

PURPOSE:To simplify the arrangement of circuitry by using an amplifier having d.c. and a.c. gains which are specified, as an ECG amplifier of receiving a bioelectric signal from each of joint electrodes. CONSTITUTION:A bioelectric signal from a joint electrode ELi (i=1 to 6) is introduced into an amplifier circuit, and high frequency range components are removed from the signal by a low pass filter composed of a resistor R1 and a capacitor C1. Then it is delivered to a positive input terminal of an amplifier Ai. As to its d.c. component the circuit is equivalent to that from which a resistor R3, a capacitor C2 and a resistor R4 are removed, due to the provision of the capacitor C2, and accordingly, it serves as a buffer having a gain of 1. Meanwhile, as to an a.c. signal, the gain of the amplifier is exhibited by (R2+R11)/R11 where R11 is an impedance given by the resistor R3, the capacitor C2 and the resistor R4, and R2 is a feed-back resistor, that is, it becomes about 50 times. Accordingly, a polarizing potential which functions as a d.c. offset, does not affect the resolution of a downstream A/D converter, appreciably, thereby it is possible to eliminate the necessity of multi-bits type.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a biological signal collecting device for collecting a biological signal from a living body such as an electrocardiograph.

[0002]

2. Description of the Related Art Conventionally, an electrocardiograph has been used to examine the function of the heart of a patient. Without using an electrocardiograph, biological signals at various parts of the living body are collected.

FIG. 11 is a view showing an example of attaching a patient electrode. (A) shows a specific mounting state, and (b) shows an equivalent circuit thereof. In (a), 1 is a living body, 2
Is the biological surface. 3 is a patient electrode, which is an electrolyte 3a
And an electrode 3b made of a metal piece, silver-silver chloride, or the like. The terminal 4 is taken out from the electrode 3b.

In FIG. 1B, V1 is a polarization potential (direct current) generated based on the configuration of the electrode 3, V2 is a drift having a period sufficiently longer than the heartbeat period, V2.
Reference numeral 3 is an original biological signal. The maximum polarization potential V1 is ± 0.
It has an amplitude of about 5V. On the other hand, the fluctuation V2 is 5
The biological signal V3 is about 0 mVpp and about 1 to 2 mV. Therefore, when measuring a biomedical signal, it is important to suppress the polarization potential V1, which is the highest level, to the extent possible and to accurately extract the biomedical signal V3.

FIG. 12 is a diagram showing an example of a detected waveform of a biological signal. The polarization potential V1 changes up to about ± 0.5V. Within that range, the fluctuation V2 is about 50 mV or less, the biological signal V3 is about 5 mV or less, and the noise is about 2.5 μV or less.

FIG. 13 is a diagram showing a circuit example of a conventional biological signal collecting apparatus. In the figure, 10 is an input terminal.
RA is the right hand, LA is the left hand, and RL is the right foot. Biological signals from RA and LA enter the buffer amplifiers U1 and U2 via the input terminal 10. The buffer amplifiers U1 and U2 are impedance conversion amplifiers having a gain of 1, and their outputs are respectively input to the differential amplifier 11. This differential amplifier is composed of an amplifier U3 and a resistor, and its gain is about 10.

The differential amplifier 11 enters a DC cut section 12 including a capacitor C and a resistor R. Then, the DC potential of the polarization potential is cut by the DC cutting unit 12. Therefore, only the fluctuation V2 and the biological signal V3 are transmitted to the circuit in the subsequent stage. Since the DC component, which is the largest offset component, is removed, the load (demand for the dynamic range) of the circuit in the subsequent stage is lightened. The output of the DC cut unit 12 enters the gain amplifier 13 and is output from 30 times to 10
It is amplified about 0 times. The gain amplifier 13 is composed of an amplifier U4 and a resistor.

In the case of the conventional analog recorder type biological signal sampling apparatus, the output of the gain amplifier 13 is used as the input of the recorder. Since it is currently processed digitally, the output of the gain amplifier 13 is input to the A / D converter 14 and converted into digital data. As the conversion bit number, for example, about 8 bits are used. Since the polarization potential V1 has been removed, the resolution of the A / D converter 14 need only be about 8 bits.

Reference numeral 15 is an amplifier which receives outputs from the buffer amplifiers U1 and U2, and its output is connected to the right leg RL as an analog ground. If three channels of biological signal output are desired, three circuits shown in the figure are required.

[0010]

In the above-mentioned conventional circuit, the buffer amplifiers U1 and U2 receive the biomedical signals from the two electrodes.
After that, the output is put into the differential amplifier 11, differentially amplified, the direct current component is cut from the output, and further amplified by the gain amplifier 13, and then converted into digital data by the A / D converter 14. The configuration is to do. Therefore,
The conventional circuit has a complicated circuit configuration. There is also a method of feeding back from the digital side to the input side of the amplifier in order to remove the DC component, but this method does not change in that the circuit is complicated.

The present invention has been made in view of the above problems, and an object thereof is to provide a biological signal sampling device having a simple circuit configuration.

[0012]

According to the present invention for solving the above-mentioned problems, in a biological signal collecting apparatus for receiving and recording signals of a plurality of channels from a plurality of function electrodes, a biological signal from each function electrode is received. The ECG amplifier is characterized by using an amplifier having a DC gain of about 1 and an AC gain of several tens.

[0013]

The direct current gain and the alternating current gain of the ECG amplifier which receives the biomedical signal from each electrode are set to about 1 and about several tens, respectively. As a result, since the DC gain is small, the polarization potential V1 is not amplified and only the biological signal V3, which is the original signal, is amplified. Therefore, the number of bits of the A / D converter that converts an analog signal into a digital signal is not so large. It doesn't have to be many. According to the present invention, a DC cut circuit is unnecessary, and a differential amplifier and an amplifier are not connected in series.
It is possible to provide a biological signal collecting device having a simple circuit configuration. Further, since a direct current signal is also passed, when the patient electrode is detached, the input of the ECG amplifier is in a floating state, and its output is swung out to the positive side or the negative side. Therefore, it is convenient that the detachment of the patient electrode can be detected.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an essential part of the first embodiment of the present invention. In the figure, EL1 to EL6 are related electrodes, EL7 is an indifferent electrode, and EL8 is a guard (ground G) electrode. The biological signal from each Seki electrode is
It enters into an amplifier circuit 20 which is composed of operational amplifiers A1 to A6 and resistors and capacitors, respectively. 21 is each amplification circuit 20
A / that receives the biological signal from the
It is a D converter. An A / D converter (not shown) is provided for each amplifier circuit 20 in the A / D converter 21.
Each biological signal is A / D-converted independently and in parallel.

CAL is a test pulse for checking the gain of each amplifier circuit, and a signal of 0 to 5 V is applied. The applied CAL pulse is attenuated at the input stage to 0.
A pulse of ˜50 mV is commonly applied to each amplifier circuit 20. The amplifier circuit 20 can be tested by checking the response of the output to this pulse input at the output side.

A reset signal is input to the A / D converter 21 from the outside. The output of each A / D converter is adapted to be output from DATA OUT. The clock is also output. This clock is synchronous with DATAOUT.
Reference numeral 22 is an oscillator that generates a clock for operating the A / D converter 21, and its frequency is about 1 MHz. A crystal, for example, is used as the oscillator. The operation of the circuit thus configured will be described below.

Each function electrode ELi (i = 1 to 6, the same applies hereinafter)
The biological signal from the input device enters the amplification circuit 20 and is amplified.
Here, the operation of the amplifier circuit 20 will be described in detail. FIG. 2A is a diagram showing a configuration example of the amplifier circuit 20. The biological signal from the common electrode ELi has a high-pass component removed by a low-pass filter (low-pass filter) including a resistor R1 and a capacitor C1, and enters the positive input terminal of the amplifier Ai.

First, the operation of amplifying the DC component will be described. At this time, the direct current component is the same as that without the resistor R3, the capacitor C2 and the resistor R4 due to the capacitor C2, and the equivalent circuit thereof is as shown in (b). This figure is just a unity gain buffer.
Therefore, the circuit shown in (a) operates as a gain 1 buffer in terms of direct current.

On the other hand, for an AC signal, the equivalent circuit is as shown in (c), where R11 is the impedance of the resistor R3, the capacitor C2, and the resistor R4 at a specific frequency. The feedback resistor is R2,
If the identification symbol is used as it is as the resistance value, the gain of the amplifier at this time is expressed by the following equation.

(R2 + R11) / R11 In the case of the resistance value and the capacitor value shown in (a), this gain is about 50 times.

Here, it is assumed that the object electrode ELi is off the body surface of the patient. As a result, the input of the amplifier circuit is floated, and the output of the operational amplifier Ai is swung out in the positive direction or the negative direction. The fact that the electrode ELi has come off can be detected based on the fact that it has shaken out.

Further, in this amplifier circuit 20, a direct current (D
In C), the gain functions as 1 and the gain functions as 50 in AC. Therefore, the polarization potential V1 having the widest input range is not amplified, but only the original biological signal is amplified 50 times. Therefore, the polarization potential V1 that functions as a DC offset does not significantly affect the resolution of the A / D converter of the A / D converter 21 in the subsequent stage. Therefore, it is not necessary to use such a multi-bit resolution as the A / D converter. For example, about 12 bits may be sufficient.

In this way, the biological signal amplified by the amplifier circuit 20 enters the subsequent A / D converter 21 and is A / D converted by an independent A / D converter for each channel and converted into digital data. To be done. This digital data is DAT
It is output from the A OUT terminal to the outside, and the latter CPU
Enter (not shown).

The CPU at the subsequent stage receives the biomedical signal from each channel, removes the polarization potential, and carries out an inductive operation for extracting the biomedical signal as the original potential difference signal. The guidance calculation includes a limb guidance calculation that simply calculates the difference between the data of the two channels, and a guidance calculation that applies a weighting factor to the calculation formula. The formula shown below is an example of what is called a Frank derivation operation.

Vx = 0.3454M + 0.6546F-1.000H Vy = 0.6110A + 0.1704C-0.7814I Vz = 0.2315C + 0.2647I + 0.3731E-0.7368M-0.1325A In the above formula, H, F, A, I, E, M, and C indicate detected biomedical signals at predetermined positions on the body surface. These seven points are connected via some resistors to form X, Y and Z induction terminals. Here, when the coefficients in each of the induction calculation formulas are added, it becomes 0, but this eliminates the common mode.

In the above-mentioned embodiment, the case where a normal A / D converter is used as the A / D converter 21 is taken as an example. Here, if a ΔΣ A / D converter is used as the A / D converter,
The advantage is that the anti-aliasing filter is not required in the input stage. The ΔΣ A / D converter is
It is composed of a ΔΣ modulator and a decimation filter. However, for digitizing biomedical signals, ΔΣA /
When a D converter is used, a problem occurs because the polarization potential is the largest component. In other words, DC in the decimation filter
When the (direct current) component is flown, an excessive demand is imposed on the dynamic range (about 18 bits are required), and the size becomes large and expensive.

FIG. 3 is a block diagram showing the essential parts of the second embodiment of the present invention. In the figure, 30 is a ΔΣ modulator that receives a biological signal, 31 is a primary combiner that receives the output of the ΔΣ modulator 30 and a feedback signal and performs weighted addition, and 32 is a decimation that receives the output of the primary combiner 31. It is a filter. A cumulative adder 33 cumulatively adds the output of the decimation filter 32, and its output is fed back to the primary combiner 31. The operation of the circuit thus configured will be described below.

The biological signal that has entered the ΔΣ modulator 30 is converted into a pulse density modulated signal by a known operation of the modulator. The output enters the primary combiner 31 and weighted addition is performed. The output of the primary combiner 31 enters the decimation filter 32, and bit serial data is output as a digital signal in synchronization with the clock. Here, the output of the decimation filter 32 enters the cumulative adder 33 and is cumulatively added. The addition result is fed back to the primary combiner 31.

The primary combiner 31 performs an operation of subtracting the output of the cumulative adder 33 from the output of the ΔΣ modulator 30. As a result, from the decimation filter 32, a digital signal containing only the biological signal from which the DC offset component including the polarization potential has been removed is obtained. As a result, the decimation filter 32 is not overloaded.

Here, the coefficient string of the primary combiner 31 must be rewritable quickly at any point during the execution of processing. The sum of the absolute values of the coefficient sequence is 1, and the arithmetic mean value is 0. By setting the arithmetic mean value to 0, the common mode component is removed. If the coefficient of the cumulative adder 33 at the time of feedback can be freely rewritten, a so-called instrument function can be realized.

FIG. 4 is a block diagram showing an example of the overall configuration of the second embodiment of the present invention. The same parts as those in FIG. 3 are designated by the same reference numerals. In the figure, the part surrounded by the broken line is integrated into a circuit as required. In the figure, EL
1 to EL6 are related electrodes, and EL7 is an indifferent electrode. The function electrode ELi enters the ΔΣ modulator 30 via an RC filter (a circuit composed of a resistor 10 KΩ and a capacitor 330 pF) for removing the RF frequency component.

The ΔΣ modulator 30 is provided for each channel. That is, six are provided in this embodiment. The indifferent electrode EL7 is Vref / 2 (Vref is A /
It is connected to the potential of the reference voltage of the D converter). Each ΔΣ
The output of the modulator 30 is input to each of the three primary combiners 31.

A decimation filter 32 receives the output of each primary combiner 31. The required number of the decimation filters 32 is provided so as to be equal to the number of parallel channels (3 in the figure) required on the output side, and is different from the number of electrodes. As the output bit number of these decimation filters 32, for example, about 12 to 16 bits are used. φ 0 is an operation clock, and is included in the ΔΣ modulator 30 and the decimation filter 32.

Reference numeral 34 designates three decimation filters 32.
Of the parallel output of the /
It is a series converter. A 1-bit serial signal is output from the parallel / serial converter 34 and is connected to, for example, a DSP (digital signal processor) to perform various desired analysis processes. The para / serial converter 34 includes:
A transfer clock φ1 for parallel / serial conversion and a shift clock are input, and serial data for expansion is input from another device. Of these signals,
The transfer clock is the decimation filter 3
2 is input as an A / D conversion start signal.

A cumulative adder 33 receives the output signals from the decimation filters 32 and cumulatively adds the signals. The outputs of the cumulative adders 33 are fed back to the respective primary combiners 31. As the power supply voltage Vcc for operating the circuit shown in the figure, about 2.7 V to 3.3 V is used to reduce power consumption. The power supply system is divided into an analog system and a digital system to remove noise and bits.

The operation of each part of the circuit thus configured is as described with reference to FIG. In this embodiment, the primary combiner 31 and the decimation filter 32 can be regarded as a coefficient variable decimation filter.

FIG. 5 is a block diagram showing the essential parts of the third embodiment of the present invention. In this embodiment, as can be seen by comparing with the embodiment shown in FIG. 3, the input for cumulative addition of the cumulative adder 33 is obtained not from the output side of the decimation filter 32 but from the output of the primary combiner 31. It was done. Even with this configuration, the same operation as that of the embodiment of FIG. 3 can be expected.

As described above, when the biological signal is converted into the digital signal by using the A / D converter, the largest component of the signal coming from the gate electrode is the direct current polarization potential V1.
(See FIG. 11). Another effective method of performing A / D conversion by eliminating the influence of the polarization potential can be realized by focusing on the fact that the biological signal changes with time. That is, the signal from the related electrode is differentiated to extract a variation, the differentiated output is converted into a digital signal by an A / D converter, and finally integrated to obtain a correct digital signal.

FIG. 6 is a block diagram showing the configuration of the fourth embodiment of the present invention. In the figure, 40 is a differentiating circuit for differentiating a biological signal from the electrode ELi, and 41 is the differentiating circuit 40.
Is a ΔΣ modulator, and 42 is the ΔΣ modulator 4
1 is a primary combiner for receiving the output of 1, and 43 is the primary combiner 42
Is a decimation filter that receives the output of. 43a
Is an integrator provided in the decimation filter 43. The ΔΣ modulator 41, the primary combiner 42 and the decimation filter 43 form a ΔΣ A / D converter.
The operation of the circuit thus configured will be described below.

The biological signals from the respective electrodes ELi enter the differentiating circuits 40 and are differentiated. Therefore, only the change amount of the biological signal is extracted. This differentiation circuit 4
The output of 0 enters the ΔΣ modulator 41 and is modulated. The outputs of these ΔΣ modulators 41 enter the subsequent primary combiner 42 and the coefficient addition operation is performed. Then, the primary combiner 4
The output of 2 enters the decimation filter 43, and is taken out as a digital signal through the integrator 43a. According to the present invention, the integrator 43a is connected to the decimation filter 4
The circuit configuration is simplified by incorporating it into the inside of 3.

FIG. 7 is a circuit diagram showing a concrete configuration example of the fourth embodiment. The same parts as those in FIG. 6 are designated by the same reference numerals. In the figure, a differentiating circuit 40 is configured by a capacitor C10 and a resistor R11. The resistor R10 and the capacitor C11 are low-pass filters that remove high frequency components. Operational amplifier U10, D type flip-flop U1
A feedback resistor R12 and a capacitor C12 form a ΔΣ modulator 41. U12 is an up / down counter 43 as a decimation filter having an integration function.
Is. The clock inverted by the inverter G is input to the flip-flop U11, and the clock is input to the up / down counter U12 as it is.

In the circuit configured as described above, only the up / down counter 43 is used as the decimation filter 43 without being cleared in each conversion period. DC
When processing a signal containing a component, it is necessary to clear the counter every certain period. Therefore, it is not possible to always read the result, and it is necessary to repeat the process of reading and clearing the result at a fixed cycle. Therefore, in order to eliminate such a process, the DC component is cut, and the analog differentiation is performed before the input is put into the ΔΣ modulator 41 so that the property of the counter as the integrator is canceled. Then, in principle, the counter 43 balances up and down and becomes stable.

The differentiation at the input of the ΔΣ modulator 41 and the integration by the up / down counter 43 are balanced, and the counter reading follows the input signal as an AC signal. Therefore, whenever the output of the counter 43 is read, the output gives the correct input value.

In the ΔΣ A / D converter, the characteristics of the decimation filter following the ΔΣ modulator decisively determine the accuracy of the entire device. Conventionally, an interval weighted moving averager or a transversal filter is used as the decimation filter. In the simplest case, a simple up / down counter as described above may be used.

According to the fourth aspect of the present invention, it is possible to effectively limit the dynamic range of the biomedical signal handled by the A / D converter and to cope with a wide dynamic range as a whole. Therefore, it becomes possible to directly convert the electrode potential using an A / D converter of about 8 to 12 bits.

When a ΔΣ A / D converter is used as the A / D converter, the input of the ECG amplifier is input to the output of the target electrode signal so that the continuous wave (CW) such as broadcast radio waves does not affect the circuit. A low-pass filter (for example, R1 and C in FIG. 2)
1) is often inserted. This low-pass filter prevents continuous waves from entering the circuit.
However, from the perspective of simplifying the circuit configuration,
Even with one low-pass filter, if it covers many channels, the number of parts will increase.

In order to eliminate such a problem, it is necessary to eliminate the low pass filter. However, if this low-pass filter is eliminated, beats may occur with the sampling clock. In order to eliminate this beat, the clock applied to the ΔΣ modulator and the decimation filter may be a spread spectrum signal. For that purpose, for example, it is effective to slightly modulate the frequency of the clock so as to be harmless. As a result, the components that cause clocks and beats are spread out and obscured.

FIG. 8 is a block diagram showing the essential parts of the fifth embodiment of the present invention. The same parts as those in FIG. 6 are designated by the same reference numerals. In the figure, 40 is a differentiating circuit for differentiating an input biological signal, 41 is a ΔΣ modulator for receiving the output of the differentiating circuit 40, and 43 is an up-down counter for receiving the output of the ΔΣ modulator 41. The up / down counter 43 has the functions of the decimation filter and the integrator as described above.

Reference numeral 45 is a comparator for comparing the output of the up / down counter 43 with a reference value, and 50 is a C for receiving the output of the up / down counter 43 as a digital data output.
It is PU. The CPU 50 receives the comparison result from the comparator 45 as an interrupt signal and receives the up / down counter 43.
A clear signal is output to. The clock is input to the ΔΣ modulator 41 and the up / down counter 43. The operation of the circuit thus configured will be described below.

The up / down counter 43 outputs digital data corresponding to the change of the biological signal. The output of the up / down counter 43 enters the comparator 45 and is constantly compared with the reference value. This reference value serves to retain the previous value when the output change is smaller than that value. This will be described with reference to FIG. The waveform shown in the figure shows the biological signal waveform, and the vertical line in the figure shows the sampling period. Although the A / D converter outputs digital data at each sampling cycle, even if the portion where the change is gentle is taken in as data, it does not have much information.

Therefore, for the part where the change is gradual, the previous data is used as the value at that point.
When the change becomes large and exceeds the reference value, the comparator 45 generates an interrupt signal to the CPU 50. CPU50
Receives the interrupt signal, the up / down counter 4
Complete 3. As a result, new data is obtained at that sampling point. In this way, by skipping the data collection of points of gradual changes,
Data compression can be achieved. Taking the case of FIG. 9 as an example, the points indicated by ● in the figure are data sampling points, and the points indicated by × are thinned data points. Data can be compressed by the number of thinned data. This data compression method can be applied to any of the embodiment circuit shown in FIG. 1, the embodiment circuit shown in FIG. 3, and the embodiment circuit shown in FIG.

FIG. 10 is a block diagram showing the essential parts of the sixth embodiment of the present invention. In the figure, 50 is a ΔΣ modulator that receives inputs (biological signals) from a plurality of channels, 51
Is a para / serial converter that receives the parallel output from each ΔΣ modulator 50 and converts it into a serial signal, and 52 is a decimation filter that receives the output of the para / serial converter 51. Here, φ1 is an operation clock (first clock) of the ΔΣ modulator 50, and this clock is input to the parallel / serial converter 51 as a data acquisition clock. Further, φ2 is an operation clock (second clock) of the decimation filter 52, and the clock φ1 is φ2 =
There is a relationship of nφ1. This second clock is
It is sent to the serial converter 51 as a sending clock.
The operation of the circuit thus configured will be described below.

The sixth embodiment is based on the following principle. The principle is that the operation clock φ1 of the ΔΣ modulator 50 and the operation clock φ2 of the decimation filter 52 in the subsequent stage may be completely independent. The reason is that the output of the ΔΣ modulator 50 is the probability density modulation of “1” and “0”,
This is because the appearance frequencies of "1" and "0" do not depend on the clock of the decimation filter in the subsequent stage, from a broad perspective.

Therefore, if there are n ΔΣ modulators 50 as shown in FIG. 10 and they operate with a common clock φ1, and the input of the subsequent decimation filter 52 is 1 bit / word, the ΔΣ modulator 50 Of the common clock φ1 of the decimation filter 52
n (conversely, the second clock .phi.2 is n times the first clock .phi.1), and the output of n channels is serially converted by the para / serial converter 51 for each cycle, and 1 bit / It is input to the word decimation filter 52.
As a result, the decimation filter 52 obtains a simple average value by treating all channels equally. Generally, since the decimation filter 52 is a digital circuit, it is easy to increase the processing speed, but on the ΔΣ modulator 50 side including the analog portion, the processing speed cannot be increased unnecessarily. Therefore, even if such serialization is performed, it is easier to adapt by increasing the processing speed of the decimation filter 52.

[0055]

As described above in detail, according to the present invention, it is possible to provide a biological signal sampling device having a simple circuit configuration, which has a large practical effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of an amplifier circuit.

FIG. 3 is a configuration block diagram showing a main part of a second embodiment of the present invention.

FIG. 4 is a block diagram showing an example of the overall configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a configuration block diagram showing a main part of a third embodiment of the present invention.

FIG. 6 is a configuration block diagram showing a main part of a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a specific configuration example of a fourth exemplary embodiment of the present invention.

FIG. 8 is a configuration block diagram showing a main part of a fifth embodiment of the present invention.

FIG. 9 is an explanatory diagram of data compression.

FIG. 10 is a configuration block diagram showing a main part of a sixth embodiment of the present invention.

FIG. 11 is a diagram showing an example of attachment of electrodes.

FIG. 12 is a diagram showing an example of a detected waveform of a biological signal.

FIG. 13 is a diagram showing a circuit example of a conventional biological signal sampling device.

[Explanation of symbols]

 20 Amplification circuit 21 A / D converter 22 Oscillator EL1-EL6 Related electrode EL7 Indifferent electrode EL8 Ground electrode

Claims (11)

[Claims] 1. A biological signal collecting apparatus for receiving and recording signals of a plurality of channels from a plurality of electrodes, wherein an ECG amplifier for receiving a biological signal from each of the electrodes has a DC gain of about 1 and an AC gain. A biomedical signal collecting device using an amplifier having a large gain of about several tens. 2. The biological signal collecting apparatus according to claim 1, wherein the ECG amplifier detects the fact that the ECG amplifier has been swung to the positive side or the negative side, and finds the deviation of the related electrode. 3. The polarization potential is removed and only the biological signal is extracted by A / D converting the outputs of the respective ECG amplifiers independently and inductively calculating the respective A / D converted outputs by a microprocessor. The biological signal collecting apparatus according to claim 1, characterized in that. 4. An accumulator that uses a ΔΣ modulator and a ΔΣ A / D converter composed of a decimation filter as an A / D converter that converts a biological signal from a related electrode into digital data, and that cumulatively adds the output of the decimation filter. An adder is provided, and the output of this cumulative adder is fed back to the primary combiner inserted between the ΔΣ modulator and the decimation filter to remove the DC component including the DC polarization potential. A biological signal collecting device characterized by the above. 5. The biological signal sampling apparatus according to claim 4, wherein the output of the primary combiner is put into a cumulative adder, and the output of the cumulative adder is fed back to the primary combiner. . 6. The number of primary combiners and decimation filters is set to match the number of output signals, and the coefficient when feeding back the output of the cumulative adder to the primary combiner can be freely changed. The biological signal collecting device according to claim 4, wherein 7. A differential signal comprising a ΔΣ modulator and a ΔΣ A / D converter composed of a decimation filter is used as an A / D converter for converting the biological signal from the Seki electrode into digital data, and the biological signal from the Seki electrode is differentiated by a differentiating circuit. After doing the above
A / D conversion is performed using a / D converter, and the result is digitally integrated to obtain output data. The integration function is included in the decimation filter of the ΔΣ A / D converter. Characteristic biological signal sampling device. 8. The biological signal sampling apparatus according to claim 4, wherein the clock applied to the ΔΣ modulator and the decimation filter is a spread spectrum signal in order to remove the influence on the continuous interference wave. 9. The A / D converter monitors the amount of change in the input signal, and if the amount of change does not reach a reference value, the data is not captured as data, thereby achieving data compression. Item 10. The biological signal sampling device according to item 1 or 4 or 7. 10. A biological signal of the relevant electrode is differentiated by a differentiating circuit, which is then put into a ΔΣ A / D modulator, an up / down counter is used as a decimation filter, and the output of the ΔΣ modulator is put into this up / down. The biological signal collecting device according to claim 4, wherein the biological signal collecting device is configured to be performed. 11. A ΔΣ constituting the ΔΣ A / D converter.
The biological signal sampling apparatus according to claim 4 or 7, wherein each of the modulator and the decimation filter is operated by an asynchronous clock having a different frequency.