JPH06197548A - Inverter device - Google Patents

Abstract

PURPOSE:To suppress the fluctuation of the electric power supplied to a load by providing a duty setting means which can set the digital value corresponding to the duty of a switching element at every period of the switching element. CONSTITUTION:The voltage corresponding to a lamp voltage VC detected by means of a lamp voltage detection circuit 1 is inputted to an A/D converter 4 and further inputted to a ROM 5 after the voltage is converted into a digital signal. Then the digital signal is converted into digital data corresponding to the duty corresponding to the value of the lamp voltage VC and inputted to a digital PWM circuit 6. In addition, signals having duties corresponding to the lamp voltage VC are inputted to the switching elements Q1-Q4 of an inverter circuit and low-frequency square-wave power is supplied to an electric discharge lamp Z. As a result, the occurrence of such a drift, etc., that occurs in an analog PWM circuit can be prevented and the fundamental frequency of the digital PWM circuit does not unnecessarily become higher even when the duty resolution is improved. Therefore, this inverter device can stably supply electric power.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device for supplying a low frequency rectangular wave power to a load, and more particularly to an inverter device which requires fine power control for the load. .

[0002]

2. Description of the Related Art FIG. 11 is a circuit diagram of a conventional inverter device.
Is. The circuit configuration will be described below. DC power
A switching element Q is provided at both ends of the source E.₁, Q₂Series of
Path and switching element Q₃, Q_FourSeries circuit is connected in parallel
Has been continued. Each switching element Q₁, Q₂, Q₃，
Q_FourBoth ends of the diode D₁, D₂，
D₃, D_FourAre connected in anti-parallel. Switching element
Q₁, Q₂Connection point and switching element Q₃, Q_FourContact
Between the continuation points, inductor L₁Through the capacitor C ₁
And a parallel circuit of the discharge lamp Z are connected. Both of discharge lamp Z
At the end, the lamp voltage detection for detecting the lamp voltage Vc is performed.
The output circuit 1 is connected. Output of lamp voltage detection circuit 1
The input voltage is stored in the PWM control circuit 2 via the amplifier Am.
Input to the negative input terminal of the comparator Cp of the high frequency oscillator 3
I am forced. The positive input terminal of the comparator Cp
The high frequency sawtooth wave voltage is input from the oscillation circuit OSC1.
There is. The open collector output of the comparator Cp is
Pulled up by anti-r, AND circuit A₁, A
₂Connected to the first input of the. AND circuit A₁, A
₂The second input of the D flip-flop FF₁Output
Q and the inverted output Q'are respectively connected. and
Circuit A₁, A₂Is the oscillator circuit OSC2 connected to the third input of
A low frequency rectangular wave voltage is input. This rectangular wave electric
Pressure is D flip-flop FF₁To the clock input terminal of
It has been entered. D flip-flop FF₁Data input
The force terminal D is connected to the inverting output Q '. And times
Road A₁Output of the switch via the drive circuits DR1 and DR4.
Touching element Q₁, Q_FourHas been entered in. AND circuit
A₂Output of the switch via the drive circuits DR2 and DR3.
Holding element Q₂, Q₃Has been entered in.

The operation of the circuit shown in FIG. 11 will be described below. The amplifier Am detected by the lamp voltage detection circuit 1
The voltage Vi that has passed through the
Input to p. In the comparator Cp, the oscillator circuit OS
By comparing the high frequency sawtooth wave voltage generated by C1 with the reference voltage, a high frequency signal PWM-controlled (pulse width modulation control) is generated according to the lamp voltage, as shown in FIG. The output of the comparator Cp becomes High level only while the sawtooth wave voltage is higher than the reference voltage, and this action makes it possible to obtain an output having a duty width according to the lamp voltage.

Next, the rectangular wave voltage generated by the low frequency oscillator circuit OSC2 is shown in FIG. A voltage obtained by dividing the rectangular wave voltage by the D flip-flop FF ₁ is shown in FIGS. 13B and 13C. FIG. 13B shows D
This is the voltage of the output Q of the flip-flop FF ₁ , and is shown in FIG.
(C) is the voltage of the inverted output Q ′ of the D flip-flop FF ₁ . These voltages together with the low frequency signal as shown in FIG. 13 (a) output from the oscillator circuit OSC2 and the high frequency signal as shown in FIG. 13 (d) output from the comparator Cp are AND circuits A ₁ and A _2. Is input to and is ANDed. The output of the AND circuit A ₁ is shown in FIG.
The output of the AND circuit A ₂ is as shown in FIG.
3 (f). The switching elements Q ₁ and Q ₄ are driven by the output of the AND circuit A ₁ , and the switching elements Q ₂ and Q ₃ are driven by the output of the AND circuit A ₂ , so that the inductor L ₁ has a configuration shown in FIG.
A current I ₀ flows as shown in. Then, a high frequency component is removed by the high frequency bypass capacitor C ₁ , so that a rectangular wave lamp voltage Vc as shown in FIG. 13 (h) is applied to the discharge lamp Z. That is, FIG. 13 (h)
In the first period Ta, only the switching elements Q ₁ and Q ₄ are driven on / off at high frequency, and the voltage of the DC power supply E is intermittently switched by the switching elements Q ₁ and Q ₄ so that the inductor L ₁ and the capacitor C ₁ are connected. _A positive DC voltage is applied to the discharge lamp Z by removing high-frequency components with the low-pass filter of ₁ . Further, in the second period Tb of FIG. 13 (h), only the switching elements Q ₂ and Q ₃ are driven on / off at high frequency, and the voltage of the DC power source E is intermittently switched by the switching elements Q ₂ and Q _3. Then, a high-frequency component is removed by a low-pass filter composed of an inductor L ₁ and a capacitor C _1, so that a negative DC voltage is applied to the discharge lamp Z. Therefore, the discharge lamp Z receives the rectangular wave voltage 1 output from the low-frequency oscillator circuit OSC2.
A rectangular wave voltage alternating with a cycle of a half cycle is applied.

[0005]

In the above-mentioned conventional example, a feedback system as shown in FIG. 14 is configured as the control system of the inverter device. In this control system, when the voltage Vc across the discharge lamp load Z changes, the output voltage Vi of the amplifier Am changes, and the duty of the high frequency signal output from the PWM control circuit 2 changes. Here, as shown in FIG. 15, considering a control system having a characteristic that the on-duty of the switching element does not change much even if the lamp voltage Vc changes, the characteristic of the PWM control changes during operation. Even if the on-duty changes and the load power fluctuates, it is not possible to detect the change in the lamp voltage Vc and adjust the output again due to the characteristics of the discharge lamp, and the output power remains fluctuated. Become. Such a thing often happens in the PWM control circuit using the comparator, and for example, there is a change in the ambient temperature. This is because the offset voltage of the comparator changes due to the change of the ambient temperature, which causes a difference in the comparison of the positive and negative inputs, and the input / output characteristics of the PWM control circuit are disturbed. For this reason, the electric power supplied to the load Z deviates from the specific electric power.

The present invention has been made in view of the above points, and an object of the present invention is to change the supply power to a load in an inverter device in which the on-duty of a switching element is PWM-controlled. To suppress.

[0007]

According to the present invention, in order to solve the above problems, as shown in FIG. 1, a low frequency rectangular wave power controlled by a high frequency switching operation is applied to a load Z. In the inverter device in which the capacitor C ₁ is supplied and the output terminal is connected, the digital value corresponding to the duty of the switching elements Q _{1 to} Q ₄ operating at high frequency can be set for each cycle of the switching elements Q _{1 to} Q _4. The duty setting means is provided.

[0008]

According to the present invention, since the duty of the switching element can be set for each cycle in the inverter device that outputs the low-frequency rectangular wave power by the high-frequency switching operation, it is represented by digital data. By changing the duty value every cycle,
The duty can be controlled with a finer resolution than the minimum resolution. This makes it possible to finely adjust the power supplied to the load.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an embodiment of the present invention. In this embodiment, the voltage corresponding to the lamp voltage Vc detected by the lamp voltage detection circuit 1 is input to the A / D converter 4 and converted into a digital signal. Then, the digital signal is input to the ROM 5, converted into digital data corresponding to the duty corresponding to the value of the lamp voltage Vc, and input to the digital PWM circuit 6. Then, the switching element Q ₁ to Q ₄ of the inverter circuit, the duty signal corresponding to the lamp voltage is supplied. Other configurations are similar to those of the conventional example of FIG.
The discharge lamp Z is supplied with low-frequency rectangular wave power. The low frequency is, for example, several hundred Hz. The circuit configuration is not limited to the full bridge type, but may be a half bridge type or any other type as long as it outputs a rectangular wave.

FIG. 2 shows the configuration of the digital PWM circuit 6 used in this embodiment. The digital output of the A / D converter 4 is added by an adder J as input data corresponding to the duty.
Has been entered in. As the input data, the data of the integer part N of the duty (%) is represented by two digits of a binary coded decimal number (4 bits × 2 = 8 bits). D ₁₀ is upper digit data and D ₁ is lower digit data. When switching the duty corresponding to 0.5%, the signal of D _0.5 is switched to 1 or 0. For example, when a load current corresponding to a duty of 35.0% is passed, D ₁₀ = 00
11, D ₁ = 0101 and D _0.5 = 0. Also, 3
When a load current corresponding to a duty of 5.5% is passed, D ₁₀ = 0011, D ₁ = 0101, and D _0.5 = 1. The operation waveform in this case is shown in FIG. These digital data D ₁₀ , D ₁ and D _0.5 are given to the first input of the adder J. At first, assuming that the second input of the adder J is 0, the input data D ₁₀ and D ₁ are directly input to the registers R ₁ and R ₂ .

On the other hand, in the oscillator OSC3, the output is
Signal frequency f₁100 times the frequency f₂= 100
Xf₁Is generating the clock signal. And 0-
Two decimal counters to count up to 99
K₁, K₂Connected in a cascade to the clock terminal
The clock signal is input. This allows you to
Counter K₂Output F of the count value from 99 to 0
As it changes, it outputs 1 or 0. Also the counter
K₁, K₂Count output and register R₁, R₂Output of
Are digital comparators P₁, P₂Entered in
When these two data match, the higher rank
Comparator P₂Output E is output. And the counter K₂
To the set input S of the RS flip-flop
Comparator P₂Connect the output of the
Input K₂When the output of changes from 99 to 0, RS
The output G of the lip flop FF changes from 0 to 1,
Star R₁, R₂Value C and counter K₁, K₂Count value D
RS flip-flop FF₂Output
G changes from 1 to 0. By this operation, RS flip
Pro-flop FF₂Output G of the frequency f₁, Duet
Input digital data D _Ten, D₁, D_0.5Equivalent to
The signal is output. On the other hand, the counter output F is
Pro-flop FF₃To the Q output and the fractional part
Data D_0.5AND with the input signal of the AND circuit A₃With
The second one is connected to the second input of the adder J. this
Counter K₁, K₂Counts from 0 to 99,
When the count output F changes from 99 to 0, T
Up-flop FF₃Q output is 0 or 1
U If the fractional data D_0.5If is 1, the adder
The second input of J is the counter K₁, K₂Is from 0 to 99
Each time counting is performed, 0 or 1 will be input alternately.
It Therefore, if the integer part of the input data B is N,
The force data is only the integer part N, and the decimal part is the data D_0.5Is 0
Occasionally, the output G of the digital PWM circuit 6 has a frequency f
₁Outputs a signal of duty N (%). Also, enter
The integer part of force data is N and the decimal part is data D_0.5Is 1
In this case, as shown in FIG. 4, the duty is N (%).
A signal in which N + 1 (%) is alternately repeated has a frequency f₁Output with
To be done. Therefore, the output from the digital PWM circuit 6
The duty of the signal
Is supplied with a square wave power that averages it, so
The power control resolution by duty becomes finer in value.
You can get the same effect.

Therefore, even if an expensive and complicated highly stable analog PWM circuit is not used, an inexpensive digital PWM circuit can be used to form a circuit in which drift or the like does not occur. Digital P
In general, the WM circuit must use the frequency obtained by multiplying the frequency of the output signal by the resolution as the frequency of the basic clock. For example, when the output signal is 50 kHz and the resolution is 1%, the frequency of the basic clock is 50 × 100 kHz.
z, that is, 5 MHz. When the method of the present invention is used, a fundamental frequency lower than the frequency obtained by multiplying the frequency of the output signal by the resolution can be used, and it becomes unnecessary to use an unnecessarily high-speed digital circuit. When the output signal is 50 kHz in this embodiment, the duty resolution is 0.5%, so the fundamental frequency is essentially 10 MHz. However, by operating as described above, the fundamental frequency is 5 MHz. The duty resolution can be 0.5%.

FIG. 5 is a circuit diagram of a control unit according to another embodiment of the present invention. The configuration of the main circuit section is the same as that in FIG. In this embodiment, the rectangular wave power supplied from the inverter circuit to the discharge lamp Z is supplied to a microcomputer (hereinafter referred to as "microcomputer").
Called)). This microcomputer 7 is CP
It has a U, a RAM, a ROM, an A / D converter, an I / O port, and a timer circuit. The terminal TM1 outputs a basic clock that determines the duty of the high frequency switching signal, and is equivalent to the oscillator OSC3 of FIG. The terminal TM2 generates a rectangular wave low frequency signal.
The oscillator OSC2 has the same function. Figure 5
The operation of the digital PWM circuit 6 is the same as the operation of the circuit of FIG. 2 as is clear from the operation waveform of FIG.
A high frequency signal having a duty corresponding to the digital data output from the output terminals D _{0 to} D _{7 of the} O port is output to the terminal G. An example of this signal is shown in FIG. Also, the operation of the inverter section is exactly the same as that of the circuit of FIG.

8 and 9 are flowcharts of a part of the program of the microcomputer 7, and FIG. 8 shows the lamp voltage Vc.
The measurement part of is shown. In this embodiment, the detected value of the lamp voltage Vc is A / D converted in the main program, and the electric power corresponding to the lamp voltage Vc is supplied to the discharge lamp load Z.
, The duty data required to be added is stored in the work area on the RAM as shown in FIG. Then, by the interrupt program shown in FIG. 9, the external digital PWM circuit 6
Set the duty data to. This interrupt program is called after one cycle of PWM conversion,
Each time, the duty data on the work area indicated by the pointer is sequentially output to the digital PWM circuit 6.

In this embodiment, since the basic clock f ₂ output from the terminal TM1 is frequency-divided by two cascaded decimal counters K ₁ and K ₂ , an output signal is basically obtained. Has a duty resolution of 1%
It is a tick. However, since the CPU switches the duty setting over four cycles, it is possible to control with a resolution of ¼ (in 0.25% increments). As an example, 35.0%, 35.25%, 35.50%,
Table 1 shows a data pattern when applying power corresponding to a duty of 35.75%.

[0016]

[Table 1]

However, when the data shown in Table 1 is repeatedly output, the duty changes regularly, so that a frequency component other than the high frequency switching frequency is generated and cannot be removed by the filter of the inverter. May have a bad influence depending on the load, but by constantly changing the order of the duty pattern shown in Table 1 by the random number program of the CPU, it is possible to suppress the generation of a specific frequency component. In this way, by controlling the duty data by the microcomputer, the duty resolution can be made substantially fine. Moreover, the generation of a specific frequency component can be suppressed by the random number program, and for example, a discharge lamp accompanied by an acoustic resonance phenomenon can be stably lit.

[0018]

According to the present invention, by using a digital PWM circuit in an inverter device which generates a low frequency rectangular wave power by a high frequency operation of a switching element, a drift or the like which occurs in an analog PWM circuit occurs. The basic frequency of the digital PWM circuit does not unnecessarily increase even if the duty resolution is increased, and the control circuit can be configured at low cost. Furthermore, by using a microcomputer as in the embodiment of FIG. 5, it is possible to perform more detailed and complicated power control.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a control circuit unit according to an embodiment of the present invention.

FIG. 3 is an operation waveform diagram of one embodiment of the present invention.

FIG. 4 is a waveform diagram of a switching signal according to an embodiment of the present invention.

FIG. 5 is a block circuit diagram showing a control circuit unit according to another embodiment of the present invention.

FIG. 6 is an operation waveform diagram of another embodiment of the present invention.

FIG. 7 is a waveform diagram of a switching signal according to another embodiment of the present invention.

FIG. 8 is a flowchart showing a duty calculation routine of another embodiment of the present invention.

FIG. 9 is a flowchart showing an interrupt routine according to another embodiment of the present invention.

FIG. 10 is an explanatory diagram showing a work area according to another embodiment of the present invention.

FIG. 11 is a circuit diagram of a conventional example.

FIG. 12 is an operation waveform diagram of a conventional analog PWM circuit.

FIG. 13 is an operation waveform diagram of a rectangular wave inverter circuit of a conventional example.

FIG. 14 is a block diagram showing a control system of a conventional example.

FIG. 15 is a characteristic diagram showing a relationship between a lamp voltage and a duty in a conventional example.

[Explanation of symbols]

1 Lamp voltage detection circuit 4 A / D converter 5 ROM 6 Digital PWM circuit C ₁ capacitor E DC power supply L ₁ inductor Q ₁ switching element Q ₂ switching element Q ₃ switching element Q ₄ switching element Z discharge lamp

Claims (1)

[Claims] 1. A digital value corresponding to the duty of a switching element operating at high frequency in an inverter device in which a low-frequency rectangular wave power controlled by high-frequency switching operation is supplied to a load and a capacitor is connected to an output terminal. An inverter device is provided with a duty setting means capable of setting each cycle of the switching element.