JPH0619709B2 - Micro program control system - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for controlling an information processing device that performs pipeline processing with a microprogram.

(b) Background of technology In an information processing device that performs pipeline processing by micro program control, one macro instruction is expanded into a flow of a plurality of micro instructions, and each flow is processed by one micro instruction. Generally, each bit group of the microinstruction is assigned to control each stage of the pipeline).

On the other hand, in the micro program control method, it is necessary to read the micro instruction from the control memory, and due to the time constraint of the access time, the micro program is used to control the first stage (referred to as D stage) of the pipeline. It was the current situation.

Therefore, if the amount of hardware increases and if there is a function change in the D stage, it is necessary to change the hardware. There is a point where flexibility cannot be fully utilized, and a method capable of performing microprogram control at all stages has been demanded.

(c) Conventional technology and problems The conventional microprogram control method for controlling an information processing apparatus that performs pipeline processing requires a long time to read the control memory, so that the first stage (D stage) of the pipeline is controlled. Has been unable to meet the timing, and has taken measures such as performing this stage by a hardware decoding circuit or inserting a dummy cycle for reading the control memory.

However, hardware control has the drawback that it is difficult to perform flexible and fine control, and the method of inserting a dummy cycle has the drawback that the dummy cycle appears on the surface of the processing time at the break of the instruction and the processing speed slows down. was there.

(d) Object of the Invention In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a method for controlling the first stage of a pipeline by a microprogram.

(e) Structure of the invention In an information processing apparatus that decomposes one macroinstruction into a plurality of microinstruction flows by microprogram control and processes in a pipeline system, the microinstruction controls the first stage of the pipeline. And a part for controlling the second and subsequent stages, and a part for controlling the first stage of the second and subsequent flows of a plurality of micro-instructions in each flow described above is the first part of the previous flow. At the same time as the part that controls the second and subsequent stages,
This is achieved by reading in the previous flow, and the microprogram can be controlled even in the first stage of the pipeline, thus constructing an information processing device that is more flexible than conventional pipeline processing. There is an advantage that can be done.

(f) Embodiments of the Invention To summarize the gist of the present invention, the present invention separates the field controlling the first stage of the pipeline from the field controlling the other stages, and the second flow of the immediately preceding flow.
By controlling the timing of reading the field for controlling the second and subsequent stages and reading the field simultaneously, the control of the first stage of the pipeline can be controlled by the microprogram.

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram for explaining the concept of the present invention, FIG. 2 is a diagram showing a logical configuration of a control memory when the present invention is implemented, and FIG. 3 is an embodiment of the present invention. It is a figure which shows with a block diagram.

In FIG. 1, each stage of the pipeline is named D, A, T, ... For convenience. Then, it is assumed that one macro instruction is expanded into a flow of a plurality of micro instructions and processed.

Even when the present invention is implemented, the D stage of the first flow of the instruction is controlled by hardware because there is no time to read the control memory.

In this D stage, a portion (hereinafter referred to as FCS) corresponding to the first flow of the control memory for the A stage and thereafter, and D
The micro-instruction read from the FCS is performed simultaneously with the reading of the stage control memory (hereinafter referred to as NDCS).
The micro-instruction used for the control after the A stage of the first flow and read from the NDCS is used for the control of the D stage of the second flow.

In the D stage of the second flow, the reading of microinstructions used for control after the A stage of the second flow is performed from a portion (hereinafter referred to as MCS) corresponding to the second flow and later of the control memory for the A stage and thereafter, At the same time, the micro instruction used for controlling the D stage of the third flow is read from the NDCS.

FIG. 2 shows the relationship between the logical structure of the control memory accessed as described above and the fields read at the same timing.

In this figure, D, A, T, ... Show fields for controlling each stage.

Further, the part surrounded by the dotted line (NDCS) indicates that there is no NDSC in the corresponding part because the D stage of the first flow is controlled by hardware.

As is clear from FIG. 2, the same flow of D, A, T,
...... The microinstruction controlling the stage is logically accessible at the same address even if it is separated from the NDCS and MCS. Part)).

However, in terms of timing, the address used for reading is different between NDCS and MCS at the same timing, and the address used for MCS is used after being delayed by one flow for the address used for NDCS. Controlled as.

NDCS and FCS or MCS read at the same timing
Examples of micro-instructions are shown with diagonal lines, solid lines, and vertical lines.

The above function is realized by one embodiment of the present invention shown in the block diagram of FIG. 3, in which 1 is a selector, 2 is a D-stage control memory (NDCS), and 3 is an A-stage or later control memory. , 31 is the part (FCS) corresponding to the first flow,
Reference numeral 32 is a portion (MCS) corresponding to the second and subsequent flows, 4 is a latch, and 51 and 52 are decoders (DEC).

The access method of the control memory when the present invention is implemented will be described below with reference to FIGS. 1 and 2.

Now, when an instruction to be executed is set in the instruction register (not shown), at the timing of the D stage of the first flow of the instruction, the operation unit (instruction code) causes the FC
At the same time when S 31 is accessed and the microinstruction used for control after the A stage of the first flow is read,
CS 2 is accessed through the selector 1 to read the microinstruction used to control the D stage of the second flow, and the decoder (DEC) 52, 51 outputs the control signal used for the control in each stage. Output.

The address used for the above access is latch 4
The MCS 32 is accessed at the timing of the D stage of the second flow of the instruction, and the ACS of the second flow is accessed.
At the same time that the microinstruction used for the control after the stage is read, the A of the first flow that has been read in advance is read.
The next micro address generated by the address generation circuit (not shown) based on the address part of the micro instruction used for control after the stage accesses the NDCS 2 through the selector 1, and the next third flow The microinstruction used for controlling the D stage is read, the address is stored in the latch 4, and the MCS 32 is read in the D stage of the next flow.
Controlled to access.

Similarly, in the D stage of each flow,
The address stored in the latch 4 is used to access the control memory (MCS) 32 for the A stage and thereafter of the flow to
At the same time as reading the microinstruction used for control after the stage, the output of the address generation circuit outputs D
The stage control memory (NDCS) 2 is accessed to read the microinstruction used to control the stage and store the address in the latch 4 repeatedly.

With the above operation, the control method by the microprogram can be introduced to the first D stage of the pipeline, which is conventionally controlled by hardware.

(g) Effects of the Invention As described above in detail, the microprogram control method of the present invention allows the field (NDCS) for controlling the first stage (D stage) of the pipeline to be transferred to other stages (A stage and later). ) Controlling fields (FCS, MC
S) and controlling the first stage of each flow, the timing of reading the field controlling the second and subsequent stages (A stage and later) of the immediately preceding flow, and the reading at the same time, The control of the first stage of the pipeline can also be controlled by the microprogram, and for the information processing device that performs the pipeline processing, except for the D stage of the first flow, all can be controlled by the microinstruction, so that the function change There is an effect that an information processing device that can deal flexibly can be constructed.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the concept of the present invention, FIG. 2 is a diagram showing a logical configuration of a control memory when the present invention is implemented,
FIG. 3 is a block diagram showing an embodiment of the present invention. In the drawings, D, A, T, ... Name of each stage of the pipeline or field name for controlling each stage of the control memory, 1 is a selector, 2 is a D stage control memory (NDCS), and 3 is Control memory for the A stage and thereafter, 31 is a portion corresponding to the first flow, 32 is the second
A part corresponding to the flow and thereafter, 4 is a latch, and 51 and 52 are decoders, respectively.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsumi Onishi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) References JP-A-50-68747 (JP, A) JP-A-56-19152 (JP, A)

Claims (1)

[Claims] 1. In an information processing device that decomposes one macroinstruction into a flow of a plurality of microinstructions by microprogram control and performs processing in a pipeline system, the microinstruction controls the first stage of the pipeline. And a part for controlling the second and subsequent stages, and a part for controlling the first stage of the second and subsequent flows of a plurality of microinstructions of each flow described above is the second of the previous flow. A microprogram control method, wherein the reading is performed in the preceding flow at the same time as a portion for controlling the second and subsequent stages.