JPH0619701A - Flag control circuit - Google Patents

Abstract

PURPOSE:To efficiently use ROM into which firmware being a program that sequentially operates a flag control circuit is written and which has prescribed capacity and to speed up processing speed. CONSTITUTION:The flag control circuit which compares an operated result Cres that is the output of an ALU computing element 10 and is accumulated in an accumulator C with an arbitrary threshold Th in a comparator 20 and which controls the polarity H/L of the flag of the compared result is provided with a threshold register 1 storing the arbitrary threshold Th becoming the reference input of the comparator 20. The comparator 20 being hardware compares the operated result Cres accumulated in the accumulator C with the threshold Th stored in the threshold register 1 and the signal H of the compared result is inputted to a latch 30. An input clock CLK to the latch 30 is decided by the output signal H when an instruction program which is firmware that is previously written into ROM 41 and which judges the state H/L of the flag is executed, and the clock is transmitted from the latch 30 as a positive H flag F0.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor DSP for processing digital signals in data transmission, and in particular, compares the arithmetic result of an ALU arithmetic unit, which is the main part thereof, with a predetermined threshold value to judge the magnitude. The present invention relates to a flag control circuit that outputs a positive / negative polarity flag H / L as a result signal. As for the flag control circuit, it is desired that the scale of the firmware which is the control program for operating the flag control circuit is as small as possible, even if the hardware circuit configuration becomes unavoidably large.

[0002]

2. Description of the Related Art As an example of firmware of a conventional digital signal processing DSP, FIG. 4 shows a case where an ALU arithmetic unit for performing arithmetic and logical operations of two data A and B is generated in an accumulator C of its output. A processing flow in the case of comparing the calculation result Cres and the arbitrary threshold value Th to judge the magnitude is shown. FIG. 5 shows the hardware configuration for performing the determination process of FIG. When the ALU calculator 10 of FIG. 5 compares the calculation result Cres generated in the accumulator C of its output with an arbitrary threshold value Th to judge the magnitude, the processing program of (100) of FIG. The arithmetic result Cres generated in the accumulator C of the output is calculated by (1
In the processing program of 01), transfer to the save register B,
Next, the threshold value Th, which is the reference value for the magnitude comparison, is assigned to the arithmetic register A. After that, in the processing program of (102), the ALU calculator again subtracts the threshold value Th of the output of the register A for calculation from the value Cres of the accumulator C of the output of the save register B, and the subtraction result Ccmp is used as the accumulator C. Leave on. Subtraction result Cc remaining in this accumulator C
mp is the comparison result between the calculated calculation result Cres of the ALU calculator 10 and the threshold value Th. Then, in order to determine the positive or negative of this subtraction result Ccmp, in the processing program of (103), ground GN
Comparing the magnitude of D value 0 with the comparator 20
When the subtraction result Ccmp is greater than 0 and is equal to 0, that is, when Cres ≥0, the output "H" of the comparator 20A is the D flip-flop which is the data latch 30. It is used as the D input of FF, and the signal H / L of the Q output of the FF is output by the defined clock input CLK, and the flag F of the positive / negative H / L signal that represents the address of the conditional branch of the magnitude comparison
_1, and selects the flag F ₁ of its positive H flag monitor FM, the state of the flag F ₁ of its positive H, determines the output value of the program counter PC, executes the instruction from its address It was a composition.

[0003]

In the case of comparing a certain calculation result with an arbitrary threshold value by the ALU calculator of the main part of the conventional digital signal processing DSP and judging the magnitude,
As described above, in order to compare the operation result Cres of the ALU operation generated in the accumulator C of the output of the ALU operator 10 with an arbitrary threshold value Th and judge the magnitude of the threshold value Th again, the ALU operator again. At 10, it is necessary to subtract the previous calculation result Cres from the predetermined threshold Th. Therefore, in order to write the processing program for operating these hardware circuits into the ROM 40 of a certain capacity and to make it the firmware,
The processing program, like the processing program flow
The number of 100-103 is large, and R of a certain capacity to write it
There was a problem that the load on the OM40 would be heavy and a problem that processing would take time.

The object of the present invention is to provide a digital signal processing DSP.
The firmware that must be written in ROM to operate each circuit when comparing the calculation result Cres generated in the accumulator C with the arbitrary threshold Th by the ALU calculator of the main part of As a result, the number of processing programs is as small as possible, resulting in high-speed processing, and the result of ALU calculation Cres
It is to realize a flag control circuit that outputs a flag F ₀ indicating a conditional branch H / L as a result of the judgment of the magnitude of the threshold value Th and the threshold value Th.

[0005]

The basic configuration of the flag control circuit of the present invention for achieving this object is shown in the principle diagram of FIG. In the principle diagram of FIG. 1, reference numeral 10 denotes two input data A and B which are main parts of a processor DSP which processes digital signals.
Is an ALU arithmetic unit for performing arithmetic and logical operations of, and 20 is a comparison for comparing the arithmetic result Cres stored in the accumulator C of the output of the ALU arithmetic unit (10) with the arbitrary threshold Th of the reference input. It is a vessel. 1 is a threshold value register that stores an arbitrary threshold value Th of the reference input of the comparator (20),
ALU computing unit (10) stored in the accumulator (C)
Comparing the result of calculation (Cres) with the threshold value (Th) stored in the threshold value register (1), the hardware comparator (2
0) and the comparison result of the output of the comparator is (Cres ≧
The output (H) at the time of (Th) is input to the D input of the D flip-flop FF (30) of the data latch (30), and the comparison result of the magnitude comparison written in advance as firmware in the ROM (41) is displayed. The input signal (H) of the FF (30) determines the input of the input clock (CLK) of the FF (30) by the output signal (H) when the instruction program that determines the state (H) of the flag F It is configured to be sent as a positive (H) flag (F ₀ ) from the Q output of 30).

[0006]

The function of the ALU arithmetic unit 10 is the same as in the conventional example.
The calculation result Cres generated in C and any reference
In the present invention, when comparing the threshold value Th to judge the magnitude
From the beginning, the threshold value Th is set as the reference input of the comparator 20.
Load threshold register 1. Comparator 20
Threshold Th and ALU loaded in threshold register 1
The operation result generated in the accumulator C at the output of the operation unit 10
Enter the result Cres, subtract both and compare,
Data latch output (H) when comparison result (Cres ≥ Th)
Input to D input of (30) flip-flop FF (30)
Decoder 42 decodes the firmware in ROM 41.
This is done independently. And comparison of comparator 20
The resulting output H when Cres ≥ Th is
Positive F flag F via flip-flop FF₀Is output as
It And this positive H flag F₀The actual output of R
It is controlled by the firmware written in OM (41). Immediately
Of the firmware written in ROM 41 in advance
Command to judge the flag state H / L of the output of the comparator 20
Decode the program with the decoder (42), and flag status
When the flag state H is detected by the detector (43) and executed
The output signal (H) of the latch causes the input clock of FF (30) of that latch.
Clock (CLK) input, positive output from the Q output of the FF (30).
(H) flag F₀As. After this, the firmware
A is the positive flag F ₀Based on the state H of
Two thresholds of the threshold judgment Th
Perform conditional branching of the dress. Because of this, the flag of the present invention
The hardware control circuit is included in the comparator 20 as its hardware.
ROM 41
Number of firmware processing programs written to
Is as shown in the flow chart of the processing program of the present invention in FIG.
Load threshold TH into threshold register 1 of (202)
One processing program to execute is the conventional processing program of FIG.
Register (101) accumulator C value Cres in ram
Processing program to be saved in data B and the (102) Accumulation
Processing program that subtracts the threshold value Th from the value Cres of the data C
Performs processing equivalent to the two processing programs of
Decrease the number of processing programs by one. Therefore, that
Write the processing program as firmware in advance R
The load on the OM 41 can be reduced, and the processing speed can be increased.
You can

[0007]

FIG. 3 is a block diagram showing the configuration of a flag control circuit according to an embodiment of the present invention. In FIG. 3, circuits having the same symbol numbers as in FIG. 1 represent circuits having the same function. New installation in Figure 3
44 is an AND gate for the input clock CLK for controlling the H / L of the flag F ₀ of the Q output of the D flip-flop FF 30 which is a latch that outputs data from the Q output in synchronization with the input clock CLK. , One input is the clock CL
K is the other input, which is the output when the judgment command of the flag state H in the firmware written in advance in the ROM 41 is detected and executed, and the logical product of these two inputs is taken. The comparator of the comparator 20 subtracts the threshold value Th from the accumulated operation result Cres of the accumulator C of the output of the ALU operation unit 10 for comparison with the threshold value Th of the output of the threshold value register 1. . And the output of the comparator 20 becomes (Cres
-Th ≥ 0), the output H of the comparator 20 when it is positive is
Latch in D flip-flop FF 30 and input clock CLK
In order to output it in synchronization with, the output H of the comparator 20 when the output of the comparator 20 is positive (Cres − Th ≧ 0) is input to its D input, and from the Q output to positive H in synchronization with the clock CLK of the CLK input. In order to turn on / off the input clock CLK of the D flip-flop FF 30 that outputs the flag F ₀ of
An AND gate 44 is provided. And the AND gate 44 is a ROM
Only when judging the state H / L of the flag F ₀ by the conditional branch instruction by the firmware written in 41, that is, the flag state H / L of the output of the comparator 20 which is the firmware written in the ROM 41 in advance is determined. The output of the AND gate 44 is H only when the decoder 42 decodes the instruction program and the flag state detector 43 detects the state H of the flag F ₀ and outputs the output signal H when it is executed.
And its output H is the latch of the output of comparator 20
It is supplied as an input clock CLK to 30 D flip-flops FF to operate the D flip-flops FF. When the flag state detector 43 does not detect the state H of the flag F ₀ , its output signal becomes L, so the output of the AND gate 44 becomes L and the output L of the AND gate 44 becomes the comparator 20.
The input clock CLK is not supplied to the D flip-flop FF of the output latch 30, and the D flip-flop FF is deactivated. Therefore, the status register 50 that holds the subsequent flag F ₀ from the D flip-flop FF of the latch 30 and the circuit such as the flag monitor FM that monitors the positive / negative H / L of the flag F ₀ are also inactive, and the flag control is performed. The power consumption of the circuit is reduced. If the threshold value TH, which is the reference input of the comparator 20 that compares the accumulated calculation result Cres of the accumulator C output from the ALU calculator 10, changes for each calculation of the ALU calculator 10, The threshold register 1 may be a variable threshold register that stores a variable threshold.

[0008]

As described above, according to the present invention, A
As a firmware for comparing the accumulated value of the accumulator of the operation result of the LU arithmetic unit with the size of _an arbitrary threshold, as the firmware for comparing the saved amount of the accumulated value of the accumulator to the register and the threshold Since the amount of subtraction is unnecessary, it is possible to reduce the load on the ROM of a fixed capacity in which the firmware is written and to speed up the process.

[Brief description of drawings]

FIG. 1 is a principle diagram showing a basic configuration of a flag control circuit of the present invention.

FIG. 2 is a flowchart of a processing program for operating a flag control circuit of the present invention.

FIG. 3 is a block diagram showing a configuration of a flag control circuit according to an embodiment of the present invention.

FIG. 4 is a flowchart of a processing program of a conventional flag control circuit.

FIG. 5 is a block diagram showing a configuration of a conventional flag control circuit.

[Explanation of symbols]

1 is a threshold register, 10 is an ALU calculator, 20 is a comparator, 30 is a latch and D flip-flop FF, 41 is ROM, 42
Is a decoder, 43 is a flag state detector, and 44 is an AND gate.

Claims (2)

[Claims] 1. A processor (D) for processing digital signals
The arithmetic result (Cres) accumulated in the accumulator (C) of the output of the ALU arithmetic unit (10) that performs arithmetic and logical operations on the two input data (A, B) that is the main part of SP) Threshold
It becomes the reference input of the comparator (20) in the flag control circuit that compares the magnitude of (Th) with the comparator (20) and controls the polarity (H / L) of the flag that is the signal of the comparison result. Any threshold
(Th) is provided with a threshold value register (1), the calculation result (Cres) accumulated in the accumulator (C) and the threshold value (Th) stored in the threshold value register (1) The size comparison of the two is performed by a hardware comparator (20), the signal (H) of the comparison result is input to the latch (30), and the ROM (4
The state of the flag (H which is the firmware written in 1) (H
/ L), the input clock (CLK) of the latch (30) is determined by the output signal (H) when the instruction program is decoded and executed, and the positive (H) is output from the latch (30). ) Flag (F ₀ ) is transmitted as a flag control circuit. 2. The threshold value register (1) is variable when the threshold value (TH) serving as a reference input of the comparator (20) changes for each processing of the ALU calculator (10). The flag control circuit according to claim 1, wherein the flag control circuit is a variable threshold value register (1A) for storing a threshold value.