JPH06196949A - Semiconducotor amplifier - Google Patents

Semiconducotor amplifier

Info

Publication number
JPH06196949A
JPH06196949A JP24111891A JP24111891A JPH06196949A JP H06196949 A JPH06196949 A JP H06196949A JP 24111891 A JP24111891 A JP 24111891A JP 24111891 A JP24111891 A JP 24111891A JP H06196949 A JPH06196949 A JP H06196949A
Authority
JP
Japan
Prior art keywords
circuit
coupler
output side
waveguide
side circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24111891A
Other languages
Japanese (ja)
Other versions
JP3158214B2 (en
Inventor
Seigo Sano
征吾 佐野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Quantum Devices Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Quantum Devices Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Quantum Devices Ltd filed Critical Fujitsu Ltd
Priority to JP24111891A priority Critical patent/JP3158214B2/en
Publication of JPH06196949A publication Critical patent/JPH06196949A/en
Application granted granted Critical
Publication of JP3158214B2 publication Critical patent/JP3158214B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To attain a semiconductor amplifier capable of executing F class operation by which high efficiency can be obtained by a simple circuit constitution. CONSTITUTION:The semiconductor amplifier is provided with a semiconductor chip 1 consisting of a transistor(TR) to be an amplifier circuit connecting an input side circuit 2 to an output side circuit 3, a coupler 4A constituted of arranging a line with lambdag/8 electric length in parallel to an input side waveguide 5 through a slight gap, a coupler 4B constituted of arranging a line with lambdag/8 electric length in parallel to an output side waveguide 6 through a light gap, and a line 7 connecting both the couplers 4A, 4B and constituted so that the power of higher harmonic 2f0 corresponding to twice of reference frequency f0 sent from the output side is injected to the input side through the couplers 4B, 4A.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、トランジスタの高効率
動作を可能にする回路が付加された半導体増幅装置に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor amplifier device to which a circuit that enables highly efficient transistor operation is added.

【0002】現在、携帯電話や自動車電話などで代表さ
れる移動体通信、或いは、衛星を利用した衛星通信など
に於いては、情報量が拡大化されるにともなって高出力
の半導体増幅装置が要求され、また、携帯電話機で使用
されている電池に於ける容量の限界、或いは、衛星で使
用されている太陽電池に於ける容量の制限などから、効
率(入力された電力及び出力として取り出される電力の
割合)が良好な半導体増幅装置が要求されている。
[0002] At present, in mobile communication represented by mobile phones, car phones, etc., or satellite communication using satellites, semiconductor output devices of high output are required as the amount of information is expanded. Efficiency (extracted as input power and output) due to the required capacity of the battery used in the mobile phone or the limited capacity of the solar battery used in the satellite. There is a demand for a semiconductor amplifier device having a good power ratio).

【0003】[0003]

【従来の技術】従来、半導体増幅装置を高出力化及び高
効率化する為、トランジスタをB級で動作させることが
行われてきたが、近年、B級動作時に発生する高調波の
処理を行って更に高効率化するF級動作の採用が提案さ
れている。
2. Description of the Related Art Conventionally, transistors have been operated in class B in order to increase the output and efficiency of semiconductor amplifier devices. In recent years, however, harmonics generated during class B operation have been processed. It has been proposed to employ class F operation to further improve efficiency.

【0004】一般に、B級動作の半導体増幅装置に於け
る理論効率は約78〔%〕(要すれば「日経エレクトロ
ニクス 1976.8.23号 第121頁〜第143
頁」を参照)であり、また、F級動作の半導体増幅装置
に於けるそれは100〔%〕(要すれば「日経エレクト
ロニクス 1976.9.20号 第117頁〜第12
7頁」を参照)であるとされている。
Generally, the theoretical efficiency of a semiconductor amplifier device of class B operation is about 78% (if necessary, "Nikkei Electronics 1976.8.23, pages 121-143."
Page)), and in the class F operation semiconductor amplifier device, it is 100% (if necessary, "Nikkei Electronics 1976.9.20, pages 117 to 12").
Page 7)).

【0005】[0005]

【発明が解決しようとする課題】前記説明したB級動作
の半導体増幅装置、或いは、F級動作の半導体増幅装置
に於ける理論効率は、配線に於ける電力損失や各デバイ
スに於ける抵抗成分の存在などで実現不可能な値であ
る。従って、現在、B級動作の半導体増幅装置に於ける
効率は、要求されるところに到底応えうるものではな
く、また、F級動作の半導体増幅装置はB級動作の半導
体増幅装置に比較して高効率の動作が可能ではあるが、
その回路構成は大変に煩雑である。
The theoretical efficiency of the class B semiconductor amplifier or class F semiconductor amplifier described above depends on the power loss in the wiring and the resistance component in each device. It is an unrealizable value due to the existence of. Therefore, at present, the efficiency in the class B operation semiconductor amplifying device cannot fully meet the demand, and the class F operation semiconductor amplifying device is less than the class B operating semiconductor amplifying device. It is possible to operate with high efficiency,
The circuit configuration is very complicated.

【0006】本発明は、高効率が得られるF級動作の半
導体増幅装置を簡単な回路構成で実現しようとする。
The present invention is intended to realize a semiconductor amplifier device of class F operation which can obtain high efficiency with a simple circuit configuration.

【0007】[0007]

【課題を解決するための手段】図1は本発明の原理を解
説する為の半導体増幅装置の要部回路説明図を表してい
る。図に於いて、1は増幅回路をなす半導体チップ、2
は入力側回路、3は出力側回路、4A及び4Bは本発明
が特徴とする結合器、5は入力側導波路、6は出力側導
波路、7は結合器4A及び4B間を結ぶ線路をそれぞれ
示している。
FIG. 1 shows a circuit diagram of an essential part of a semiconductor amplifier device for explaining the principle of the present invention. In the figure, 1 is a semiconductor chip forming an amplifier circuit, 2
Is an input side circuit, 3 is an output side circuit, 4A and 4B are couplers characterized by the present invention, 5 is an input side waveguide, 6 is an output side waveguide, and 7 is a line connecting the couplers 4A and 4B. Shown respectively.

【0008】この半導体増幅装置に於いては、結合器4
Bが出力側回路3の出力側に於ける導波路と僅少な空隙
を維持しつつ進行方向に対してλg /8(λg :導波路
中の波長)の長さ分だけ平行に配置され、その進行方向
側の端は50〔Ω〕で終端している。
In this semiconductor amplifying device, the coupler 4
B is arranged in parallel with the waveguide on the output side of the output side circuit 3 by a length of λ g / 8 (λ g : wavelength in the waveguide) with respect to the traveling direction while maintaining a slight gap. The end on the traveling direction side is terminated with 50 [Ω].

【0009】前記の構成にした場合、基本周波数f
0 (増幅しようとする周波数)に対してはλg /8の電
気長であるが、二倍の高調波2f0 に対してはλg /4
の電気長をもっていることになり、従って、二倍の高調
波2f0 に対しては、所謂、方向性結合器として作用す
る。
With the above arrangement, the fundamental frequency f
The electrical length is λ g / 8 for 0 (the frequency to be amplified), but λ g / 4 for the double harmonic 2f 0 .
Therefore, it acts as a so-called directional coupler with respect to the double harmonic wave 2f 0 .

【0010】また、結合器4Bと導波路6との空隙を密
にすることで二倍の高調波電力の半分を結合器4Bに於
ける線路7中に結合することが可能である。尚、基本周
波数f0 に対しては、電気長がλg /8となるから、結
合率は充分に小さく、基本周波数電力には影響を与える
ことがない。
Further, by making the gap between the coupler 4B and the waveguide 6 dense, it is possible to couple half the double harmonic power into the line 7 in the coupler 4B. Since the electrical length is λ g / 8 for the fundamental frequency f 0 , the coupling rate is sufficiently small and the fundamental frequency power is not affected.

【0011】さて、結合器4Bの線路7中に結合した二
倍の高調波電力は、入力側回路2の入力側に於ける導波
路5に対し、出力側回路3についての前記説明と同様、
僅少な空隙を維持して平行に配置され電気長がλg /8
であって50〔Ω〕で終端された結合器4Aに導かれ
る。この入力側に配置した結合器4Aに依って、入力側
回路2には二倍の高調波を注入することができる。
Now, the doubled harmonic power coupled in the line 7 of the coupler 4B is applied to the waveguide 5 on the input side of the input side circuit 2 in the same manner as described above for the output side circuit 3.
The electrical length is λ g / 8, which are arranged in parallel while maintaining a small gap.
And is led to the coupler 4A terminated with 50 [Ω]. Due to the coupler 4A arranged on the input side, double harmonics can be injected into the input side circuit 2.

【0012】前記説明した動作に依って、出力側電圧並
びに出力側電流はそれぞれ矩形波並びに半波正弦波に近
づくことになる。前記説明したように、二倍の高調波を
注入することでF級動作が実現されることは次のように
説明される。尚、理論的には、二倍以上の高次の高調
波、例えば三倍、四倍・・・・などの高調波についても
処理を行うべきであるが、レベルが飛び抜けて大きいの
は二倍の高調波であるから、実際面からすると、他の高
調波については考慮する必要がない。次に示す式は、二
倍の高調波を注入した場合にF級動作が実現されること
を記述している。
According to the operation described above, the output side voltage and the output side current come close to the rectangular wave and the half-wave sine wave, respectively. As described above, it is explained as follows that the class F operation is realized by injecting the double harmonic. Theoretically, processing should be performed for higher-order harmonics that are more than double, such as triple, quadruple, ... Since it is a higher harmonic wave, in practice, it is not necessary to consider other higher harmonic waves. The following equation describes that class F operation is achieved when a double harmonic is injected.

【0013】[0013]

【数1】 [Equation 1]

【0014】[0014]

【数2】 [Equation 2]

【0015】前記したところから、本発明の半導体増幅
装置に於いては、整合をとる為の入力側回路(例えば入
力側回路2)及び出力側回路(例えば出力側回路3)が
接続されたトランジスタからなる増幅回路(例えば半導
体チップ1)と、該入力側回路における導波路(例えば
入力側導波路5)に電気長がλg /8(λg :導波路中
の波長)である線路を僅少な空隙を介して平行に配置し
て構成した第一の結合器(例えば結合器4A)と、該出
力側回路における導波路(例えば出力側導波路6)に電
気長がλg /8(λg :導波路中の波長)である線路を
僅少な空隙を介して平行に配置して構成した第二の結合
器(例えば結合器4B)と、該各結合器(結合器4A及
び結合器4B)間を結ぶ線路(例えば線路7)とを備え
て該出力側回路から送出される基本周波数f0 の二倍の
高調波2f0 の電力を第二の結合器及び第一の結合器を
介して該入力側回路に注入することを特徴とする。
From the above, in the semiconductor amplifier device of the present invention, the transistor to which the input side circuit (for example, the input side circuit 2) and the output side circuit (for example, the output side circuit 3) for connection are connected. The amplifier circuit (for example, the semiconductor chip 1) and the waveguide (for example, the input-side waveguide 5) in the input-side circuit have few lines having an electrical length of λ g / 8 (λ g : wavelength in the waveguide). The electrical lengths of the first coupler (for example, the coupler 4A) and the waveguide in the output side circuit (for example, the output side waveguide 6) that are arranged in parallel with each other with a gap between them are λ g / 8 (λ g : wavelength in the waveguide) and a second coupler (for example, coupler 4B) configured by arranging lines that are parallel to each other with a small air gap, and each of the couplers (coupler 4A and coupler 4B). ) With a line (for example, line 7) connecting between the output side circuit and Twice the power of the harmonic 2f 0 of the fundamental frequency f 0 issued through the second coupler and the first coupler, characterized in that injected into the input side circuit.

【0016】[0016]

【作用】前記手段を採ることに依り、既存の半導体増幅
装置に於ける回路を殆ど変更することなく、簡単な電気
長λg /8なる線路を付加するだけで基本周波数f0
二倍の高調波2f0 の電力を出力側から入力側に注入し
て高効率のF級動作を実現することができ、携帯電話や
自動車電話などの移動体通信、或いは、衛星通信などに
用いる機器など、電源に制約がある機器には好適であ
る。
By adopting the above-mentioned means, the basic frequency f 0 can be doubled by simply adding a line having a simple electric length λ g / 8 without changing the circuit in the existing semiconductor amplifier device. High-efficiency class F operation can be realized by injecting the electric power of the harmonic wave 2f 0 from the output side to the input side, and equipment used for mobile communication such as mobile phones and car phones, or for satellite communication, etc. It is suitable for devices with limited power supply.

【0017】[0017]

【実施例】図2は本発明一実施例を解説する為の半導体
増幅装置の要部回路説明図を表していて、図1に於いて
用いた記号と同記号は同部分を表すか或いは同じ意味を
持つものとする。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a circuit diagram of a main part of a semiconductor amplifying device for explaining one embodiment of the present invention. The same symbols as those used in FIG. 1 represent the same parts or the same. It has meaning.

【0018】図から明らかなように、半導体チップ1は
トランジスタQからなる増幅回路であり、入力側回路2
及び出力側回路3は通常のスタブ整合回路であり、結合
器4A及び4Bは本発明の原理として説明した通りの構
成になっている。この図からすると、本発明に依る半導
体増幅装置が、従来の半導体増幅装置の構成に結合器4
A及び4Bと線路7とを或る条件の下に付加したに過ぎ
ないことが知得され、この他には何ら特殊な構成はな
く、その実施は容易であることが看取されよう。
As is apparent from the figure, the semiconductor chip 1 is an amplifier circuit composed of a transistor Q, and an input side circuit 2
The output side circuit 3 is an ordinary stub matching circuit, and the couplers 4A and 4B are configured as described as the principle of the present invention. According to this figure, the semiconductor amplifying device according to the present invention has the same structure as that of the conventional semiconductor amplifying device.
It will be appreciated that A and 4B and line 7 have only been added under certain conditions, there is no special construction other than this, and it will be appreciated that its implementation is easy.

【0019】本実施例に於いても、前記説明した本発明
の原理に於ける半導体増幅装置と同様、入力側回路2及
び出力側回路3に於ける入力側導波路及び出力側導波路
には電気長がλg /8である線路を沿わせた結合器4A
及び4Bが設けてあり、その結合器4A並びに4Bは、
基本周波数f0 の電力に対しては何らの作用も及ぼさ
ず、出力側回路3からの二倍の高調波2f0 に対しての
み方向性結合器として動作し、その二倍の高調波2f0
の電力を入力側回路2に注入して出力側電圧を矩形波
に、また、出力側電流は半波正弦波にそれぞれ近づける
ように作用して、半導体増幅装置は効率が理想状態に近
づくように動作する。
Also in this embodiment, the input side waveguide and the output side waveguide in the input side circuit 2 and the output side circuit 3 are connected to the input side circuit 2 and the output side circuit 3 as in the semiconductor amplifier device according to the principle of the present invention described above. Coupler 4A along a line with an electrical length of λ g / 8
And 4B are provided, and the couplers 4A and 4B are
Without adversely whatsoever of action for the power of the fundamental frequency f 0, and operates as only the directional coupler with respect to the double harmonic 2f 0 from the output-side circuit 3, harmonic 2f 0 of the double
Power is injected into the input side circuit 2 so that the output side voltage becomes a rectangular wave and the output side current becomes close to a half-wave sine wave, so that the efficiency of the semiconductor amplifier device approaches an ideal state. Operate.

【0020】図3は図2に見られる実施例に於ける効率
改善の様子を説明する為の線図を表し、横軸には効率
〔%〕を、また、横軸にはトランジスタの出力〔dB
m〕をそれぞれ採ってある。図に於いて、+印は本発明
一実施例の特性線、□印は比較の為に付加した従来例の
特性線をそれぞれ示している。ここで、効率とは、トラ
ンジスタの出力を固定しておき、最大の効率が得られる
ように半導体増幅装置の回路を調整した場合の値であ
る。
FIG. 3 is a diagram for explaining the state of efficiency improvement in the embodiment shown in FIG. 2, where the horizontal axis shows the efficiency [%] and the horizontal axis shows the output of the transistor [%]. dB
m] are taken respectively. In the figure, + indicates the characteristic line of the embodiment of the present invention, and □ indicates the characteristic line of the conventional example added for comparison. Here, the efficiency is a value when the output of the transistor is fixed and the circuit of the semiconductor amplifying device is adjusted so that the maximum efficiency is obtained.

【0021】図から明らかなように、本発明の実施例に
依ると、従来の技術に依って半導体増幅装置の回路を調
整した場合に比較して効率が確実に向上している。とこ
ろで、図示のデータに於いて、トランジスタ出力が30
〔dBm〕である場合、本発明に依る効率の改善は1
〔%〕であるが、同じく34〔dBm〕に於いては約6
〔%〕の向上が見られる。この数値のみでは余り大きな
改善とは見えないかも知れぬが、現在、携帯電話に使用
されているトランジスタの出力は約2〔W〕(33〔d
Bm〕)であり、そして、電池の寿命に依存する通話時
間は約12〔時間〕程度であることから、効率が6
〔%〕改善されたことは、通話時間にして約1〔時間〕
の延長に相当し、そこに充分な改善の存在が認識されよ
う。
As is apparent from the figure, according to the embodiment of the present invention, the efficiency is surely improved as compared with the case where the circuit of the semiconductor amplifying device is adjusted by the conventional technique. By the way, in the data shown, the transistor output is 30
If it is [dBm], the improvement in efficiency according to the present invention is 1
[%], But also at 34 [dBm], about 6
There is an improvement in [%]. Although this value alone may not seem to be a significant improvement, the output of the transistor currently used in mobile phones is about 2 [W] (33 [d
Bm]), and the talk time depending on the battery life is about 12 [hours], so the efficiency is 6
[%] The improvement is about 1 [hours] in talk time.
It will be recognized that there is a sufficient improvement there.

【0022】[0022]

【発明の効果】本発明に依る半導体増幅装置に於いて
は、入力側回路及び出力側回路が接続されたトランジス
タからなる増幅回路と、入力側の導波路に電気長がλg
/8である線路を僅少な空隙を介して平行に配置して構
成した第一の結合器と、出力側の導波路に電気長がλg
/8である線路を僅少な空隙を介して平行に配置して構
成した第二の結合器と、各結合器間を結ぶ線路とを備え
て出力側から送出される基本周波数f0 の二倍の高調波
2f0 の電力を第二の結合器及び第一の結合器を介して
入力側に注入している。
In the semiconductor amplifying device according to the present invention, the electric length is λ g in the amplifying circuit composed of the transistor to which the input side circuit and the output side circuit are connected and the input side waveguide.
/ 8 line is arranged in parallel with a slight gap, and the electrical length is λ g in the output side waveguide and the first coupler.
A second coupler composed of / 8 lines arranged parallel to each other with a slight air gap, and a line connecting the couplers to each other, and is twice the fundamental frequency f 0 transmitted from the output side. The power of the harmonic wave 2f 0 is injected into the input side through the second coupler and the first coupler.

【0023】前記構成を採ることに依り、既存の半導体
増幅装置に於ける回路を殆ど変更することなく、簡単な
電気長λg /8なる線路を付加するだけで基本周波数f
0 の二倍の高調波2f0 の電力を出力側から入力側に注
入して高効率のF級動作を実現することができ、携帯電
話や自動車電話などの移動体通信、或いは、衛星通信な
どに用いる機器など、電源に制約がある機器には好適で
ある。
By adopting the above-mentioned structure, the basic frequency f can be obtained by adding a simple electric length λ g / 8 line without changing the circuit in the existing semiconductor amplifier device.
Is injected into the input side of twice the power of the harmonic 2f 0 of 0 from the output side can be realized F class operation with high efficiency, a mobile communication such as cellular phones and car phones, or satellite communications, etc. It is suitable for equipment with a limited power supply, such as equipment used for.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の原理を解説する為の半導体増幅装置の
要部回路説明図である。
FIG. 1 is an explanatory diagram of a main circuit of a semiconductor amplifier device for explaining the principle of the present invention.

【図2】本発明一実施例を解説する為の半導体増幅装置
の要部回路説明図である。
FIG. 2 is a circuit diagram of a main part of a semiconductor amplifier device for explaining an embodiment of the present invention.

【図3】図2に見られる実施例に於ける効率改善の様子
を説明する為の線図である。
FIG. 3 is a diagram for explaining a state of efficiency improvement in the embodiment seen in FIG.

【符号の説明】[Explanation of symbols]

1 増幅回路をなす半導体チップ 2 入力側回路 3 出力側回路 4A 結合器 4B 結合器 5 入力側導波路 6 出力側導波路 7 線路 1 semiconductor chip forming an amplifier circuit 2 input side circuit 3 output side circuit 4A coupler 4B coupler 5 input side waveguide 6 output side waveguide 7 lines

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】整合をとる為の入力側回路及び出力側回路
が接続されたトランジスタからなる増幅回路と、 該入力側回路における導波路に電気長がλg /8
(λg :導波路中の波長)である線路を僅少な空隙を介
して平行に配置して構成した第一の結合器と、 該出力側回路における導波路に電気長がλg /8
(λg :導波路中の波長)である線路を僅少な空隙を介
して平行に配置して構成した第二の結合器と、 該各結合器間を結ぶ線路とを備えて該出力側回路から送
出される基本周波数f0 の二倍の高調波2f0 の電力を
第二の結合器及び第一の結合器を介して該入力側回路に
注入することを特徴とする半導体増幅装置。
1. An amplifier circuit comprising a transistor to which an input side circuit and an output side circuit are connected for matching, and a waveguide in the input side circuit has an electrical length of λ g / 8.
g : wavelength in the waveguide) and a first coupler configured by arranging the lines in parallel with a slight air gap, and the waveguide in the output side circuit has an electrical length of λ g / 8
The output side circuit is provided with a second coupler configured by arranging a line (λ g : wavelength in the waveguide) in parallel with a slight air gap, and a line connecting the respective couplers. A semiconductor amplifying device, characterized in that electric power of a harmonic wave 2f 0 that is twice as high as the fundamental frequency f 0 transmitted from the device is injected into the input side circuit via the second coupler and the first coupler.
JP24111891A 1991-09-20 1991-09-20 Semiconductor amplifier Expired - Fee Related JP3158214B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24111891A JP3158214B2 (en) 1991-09-20 1991-09-20 Semiconductor amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24111891A JP3158214B2 (en) 1991-09-20 1991-09-20 Semiconductor amplifier

Publications (2)

Publication Number Publication Date
JPH06196949A true JPH06196949A (en) 1994-07-15
JP3158214B2 JP3158214B2 (en) 2001-04-23

Family

ID=17069555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24111891A Expired - Fee Related JP3158214B2 (en) 1991-09-20 1991-09-20 Semiconductor amplifier

Country Status (1)

Country Link
JP (1) JP3158214B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5767743A (en) * 1995-10-13 1998-06-16 Matsushita Electric Industrial Co., Ltd. Radio frequency power amplifier having a tertiary harmonic wave feedback circuit
JP2007173956A (en) * 2005-12-19 2007-07-05 Toshiba Corp High-frequency output monitor circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5767743A (en) * 1995-10-13 1998-06-16 Matsushita Electric Industrial Co., Ltd. Radio frequency power amplifier having a tertiary harmonic wave feedback circuit
JP2007173956A (en) * 2005-12-19 2007-07-05 Toshiba Corp High-frequency output monitor circuit device
JP4599286B2 (en) * 2005-12-19 2010-12-15 株式会社東芝 High frequency output monitor circuit device

Also Published As

Publication number Publication date
JP3158214B2 (en) 2001-04-23

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