JPH06196505A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a plurality of MESFET or the like wherein the distance between a gate and a source can be designed independently of the distance between the gate and a drain, and different distances between the gates and the sources are set on the same wafer in the same process. CONSTITUTION:An SiNx film 2 is formed on the surface of an operating layer 1a of a substrate 1, and a gate pattern 3a, a source pattern 3b, and a drain pattern 3c are opened in the SiNx film 2. After an SiO2 film 4 is deposited on the SiNx film 2 and buried in each of the patterns 3a, 3b, 3c, the source pattern 3b and the drain pattern 3c are again opened. By implanting ions in the opened patterns 3b, 3c, a source side N<+> layer 1b and a drain side N<+> side layer 1c are formed, and an source electrode 6b and a drain electrode 6c are formed on the source side N<+> layer 1b and the drain side N<+> layer 1c, respectively. Then the SiO2 film 4 in the gate pattern 3a is eliminated, and a gate electrode 8 is formed in the gate pattern 3a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. Specifically, GaAs-MESFET and H
The present invention relates to a method for manufacturing a compound semiconductor device such as EMT.

[0002]

2. Description of the Related Art MESFET (metal-semiconductor FE)
In T), the distance between the gate electrode and the source region (hereinafter referred to as the gate-source distance) and the distance between the gate electrode and the drain region (hereinafter referred to as the gate-drain distance) are reduced. Will improve the characteristics of the device. However, in the conventional method for manufacturing a MESFET, a source pattern and a drain pattern are opened in a protective film formed on a semiconductor substrate, and ion implantation is performed to form a source and a drain region. Since the gate pattern is opened between them to form the gate electrode, there is a limit to how small the gate-source distance and the gate-drain distance can be set from the accuracy of mask alignment when forming the gate pattern, and to set them accurately. there were.

For this reason, various manufacturing methods by self-alignment have been conventionally proposed. Fig.3 (a)-
Shown in (j) is a method for manufacturing a MESFET by the sidewall gate self-alignment method. This manufacturing method is to manufacture the MESFET 38 as follows. First, semi-insulating GaAs in which the operating layer 31a is formed by the epitaxial growth method or the ion implantation method.
After the SiN _X film 32a is deposited on the substrate 31, by processing the SiN _X film 32a by photolithography or the like to form a dummy gate 32 for forming the gate electrode [3
(A)]. Next, a SiO ₂ film 33 is deposited on the surface of the wafer from above the dummy gate 32 [FIG.
The SiO ₂ film 33 is anisotropically etched by the (reactive ion etching) method to form sidewalls 33 of the dummy gate 32.
b and 33c are formed [FIG. 3 (c)].

After that, the dummy gate 32 and the side wall 33 are formed.
Ions are implanted using the masks b and 33c as a mask, as shown in FIG.
As shown in (d), a source side n ⁺ layer (source region) 31b and a drain side n ⁺ layer (drain region) 31c are formed on both sides of the dummy gate 32, and annealing is performed in an As atmosphere. Then, a photoresist film 3 is formed on the surface of the wafer.
4 is formed, the source electrode pattern and the drain electrode pattern are opened in the photoresist film 34 by the photolithography method, and then the source / drain metal 35 is deposited [FIG. 3 (e)]. Then, the photoresist film 34 is removed, and the source side n ⁺ layer 31b and the drain side n ⁺ layer 31 are removed.
A source electrode 35b and a drain electrode 35c are formed on c (FIG. 3 (f)).

Dummy gate 32 and side walls 33b and 33c
A photoresist film 36 is formed on the surface of the wafer until it is hidden [FIG. 3 (g)], and the photoresist film 36 is etched to expose only the dummy gate 32 and the tops of the side walls 33b and 33c [FIG. 3 (h)]. . Then, the dummy gate 32 and the side walls 33b and 33c are removed by etching to open a gate pattern 36a in the photoresist film 36, and a gate metal 37 is vapor-deposited on the photoresist film 36 [FIG. 3 (i)]. At this time, the gate electrode 37a having the bottom surface of the dummy gate 32 as a mold is formed in the gate pattern 36a.
Is formed. Therefore, when the photoresist film 36 is removed, the MESFET 38 is completed [FIG.
(J)].

[0006]

MESF as described above
In the ET manufacturing method, the distance between the gate and the source and the distance between the gate and the drain are both sidewalls 33b and 33b.
The width of the side walls 33b and 33c is RI.
It can be set within a certain range by operating the conditions in the etching process by the E method.

However, in the above conventional manufacturing method, since the side walls 33b and 33c are formed by anisotropically etching the SiO ₂ film 33 by the RIE method, the side walls left on both sides of the dummy gate 32 are formed. 33b, 3
The width of 3c cannot be set independently. For this reason,
The distance between the gate and the source and the distance between the gate and the drain cannot be independently set to arbitrary values.
Therefore, according to the conventional method, the distance between the gate and the source and the distance between the gate and the drain are significantly different asymmetrically, or a plurality of MESFETs having different distances between the gate and the source are manufactured in the same process on the same wafer. I couldn't.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and an object of the present invention is to design the gate-source distance and the gate-drain distance independently of each other. Moreover, a plurality of MEs having different gate-source distances in the same process on the same wafer
It is to provide a method of manufacturing a semiconductor device capable of manufacturing SFET and the like.

[0009]

According to a method of manufacturing a semiconductor device of the present invention, a first protective film is formed on a compound semiconductor substrate having an operation layer, and a gate pattern, a source pattern and a first protective film are formed on the first protective film. A step of simultaneously opening a drain pattern, a step of filling and closing a gate pattern opened in the first protective film with a second protective film, and a source pattern of the substrate using the first and second protective films as a mask Implanting an impurity into the region and the drain pattern region to form a source region and a drain region, forming a source electrode and a drain electrode on the source region and the drain region, and then performing the second protection And removing the film to form a gate electrode in the gate pattern region of the substrate.

[0010]

In the method of manufacturing a semiconductor device according to the present invention, the gate pattern, the source pattern and the drain pattern are simultaneously opened in the first protective film, and then the gate pattern is once closed by the second protective film. The source region and the drain region are formed by using the protective film and the second protective film as a mask, and then the second protective film is removed and the gate pattern is opened again to form the gate electrode.

Therefore, the source region and the drain region can be formed by self-alignment with reference to the gate pattern for forming the gate electrode, and the gate-source distance and the gate-drain distance can be accurately formed. it can.

In addition, since the pattern and dimensions of the gate electrode, the source region, the drain region, etc. can be set arbitrarily and independently at the time of patterning the first protective film, the gate-source distance and the gate-drain can be set. The distances can be set independently of each other to have arbitrary dimensions. Therefore, it is possible to form a semiconductor device in which the gate-source distance and the gate-drain distance are different, and to fabricate devices with different gate lengths and gate-source distances simultaneously on the same wafer in the same process. You can also

[0013]

1A to 1I show a method of manufacturing a MESFET according to an embodiment of the present invention. Here, for convenience, the gate length is 0.5 μm, the gate electrode 8 and the source side n ⁺ layer 1b
A description will be given of a case where the distance (gate-source distance) is 0.5 μm and the distance between the gate electrode 8 and the drain side n ⁺ layer 1c (gate-drain distance) is 1.0 μm.

First, as shown in FIG. 1 (a), Si is formed on a semi-insulating GaAs substrate 1 having an operating layer 1a formed on the surface by epitaxial growth or ion implantation technique.
The N _x film 2 is deposited. At this time, the film thickness of the SiN _x film 2 is set to be substantially the same as the gate length, and here it is set to 0.5 μm.

Next, a photoresist film 3 is formed on the SiN _x film 2, and the gate pattern 3a and the source pattern 3 are formed on the photoresist film 3 by photolithography.
b and the drain pattern 3c are opened [Fig. 1
(B)]. The gate length is determined by the opening width of the gate pattern 3a at this time (when a sidewall is provided, the gate length is shortened by the width of the sidewall), and the width of the photoresist film 3 between the gate pattern 3a and the source pattern 3b is determined. Determines the gate-source distance, and the width of the photoresist film 3 between the gate pattern 3a and the drain pattern 3c determines the gate-drain distance.

Then, the SiN _x film 2 exposed from each of the patterns 3a, 3b and 3c is removed by etching, and the gate pattern 3a, the source pattern 3b and the drain pattern 3c of the photoresist film 3 are deepened to the SiN _x film 3, respectively. By removing the photoresist film 3, each pattern 3a,
3b and 3c are transferred to the SiN _x film 2 [FIG. 1 (c)].

Next, as shown in FIG. 1 (d), SiO ₂ gaps 4 are deposited on the entire surface. The deposition at this time needs to be isotropic, and the thickness is about 0.5 μm, which is about the same as the SiN _x film 2. Thereby, the gate pattern 3a
It is completely filled with the SiO ₂ film 4, the SiO ₂ film 4 having a thickness of approximately twice the other part is deposited in a portion of the gate pattern 3a.

After that, when the SiO ₂ film 4 is removed by about 0.5 μm by anisotropic etching such as RIE, the SiO ₂ film 4 filling the gate pattern 3a remains.
The SiO ₂ film 4 filling the source pattern 3b and the drain pattern 3c is almost completely removed.

Then, ions are implanted into the operating layer 1a of the GaAs substrate 1 through the source pattern 3b and the drain pattern 3c to form the source side n ⁺ layer 1b and the drain side n ⁺ layer 1c.
After forming the film, it is annealed in an As atmosphere [Fig.
(E)].

In the step of anisotropically etching the SiO ₂ film 4, the source and drain patterns 3b and 3c are formed.
The SiO ₂ film 4 in the inside may not be completely removed, the SiO ₂ film 4 may be left thin, and the thin SiO ₂ film 4 may be transmitted to perform ion implantation. In this case, the source side and the drain side n ⁺
Since the evaporation of As from the layers 1b and 1c can be suppressed by the SiO ₂ film 4, the annealing can be performed in the air.

Next, as shown in FIG. 1 (f), SiO ₂
A photoresist film 5 is formed on the entire surface of the wafer from above the film 4, and the source and drain electrode patterns are opened by a photolithography method to partially expose the source side and drain side n ⁺ layers 1b and 1c. The source / drain metal 6 is vapor-deposited on the resist film 5. At this time, the source and drain electrodes 6b and 6c are formed in the source and drain electrode pattern.

Then, as shown in FIG. 1G, the unnecessary photoresist film 5 is removed, and heat treatment is applied to the source and drain electrodes 6b and 6c and the source side and drain side n ⁺ layers 1b and 1c. Are alloyed to bring the source electrode 6b and the drain electrode 6c into ohmic contact with each other.

Next, as shown in FIG. 1H, the exposed SiO ₂ film 4 is completely removed by selective etching. Then, a photoresist film 7 is formed on the surface, and the gate electrode pattern 7a is opened to expose the operating layer 1a of the GaAs substrate 1 in the gate pattern 3a. When the gate metal is deposited here, the gate electrode 8 is formed in the gate electrode pattern 7a and the gate pattern 3a.

At this time, the opening width of the gate electrode pattern 7a is made larger than the opening width of the gate pattern 3a, that is, the gate length, and both sides of the gate pattern 3a are exposed from the surface of the GaAs substrate 1 exposed in the gate pattern 3a. If the gate electrode 8 is formed so as to have a T-shaped cross section over the surfaces of the SiN _x films 2 and 2, the gate resistance can be reduced, and the high frequency characteristics of the MESFET 9 can be improved. Finally, the photoresist film 7
To complete the fabrication of MESFET 9 [FIG.
(I)].

In the MESFET manufacturing method according to this embodiment, the gate electrode 8 of the MESFET and the source side n ⁺
The layer 1b and the drain side n ⁺ layer 1c are the gate pattern 3a, the source pattern 3b and the drain pattern 3 which are simultaneously opened in the SiN _x film 2 by the photolithography method.
Since it is formed by c, a position error due to mask alignment does not occur, the gate-source distance and the gate-drain distance can be obtained with high accuracy by self-alignment, and the reproducibility of MESFET manufacturing is improved.

Further, by patterning the SiN _x film 2, the dimensions and positions of the gate electrode 8, the source side n ⁺ layer 1b and the drain side n ⁺ layer 1c can be determined, so that the gate length and the gate-source distance can be determined. The gate-drain distance can be independently set to an arbitrary dimension, and can be set to an arbitrary length from the minimum line width that is approximately the same as the gate length. Moreover, the gate-source distance and the gate-drain distance can be arbitrarily changed depending on the mask for patterning the SiN _x film 2, and the MESFETs 9 having different gate-source distances can be simultaneously formed on the same wafer by the same process. It can also be produced.

2 (a) and 2 (b) are sectional views showing a method of manufacturing a MESFET according to another embodiment of the present invention. In the method of manufacturing the MESFET 10 of this embodiment, the steps up to forming the source electrode 6b and the drain electrode 6c are the same as the steps of FIGS. 1A to 1G of the above-described embodiment.

In this embodiment, as shown in FIG.
Similarly to (g), after forming the source electrode 6b and the drain electrode 6c on the source side n ⁺ layer 1b and the drain side n ⁺ layer 1c, respectively, the SiO ₂ film 4 remaining on the gate pattern 3a is selected. By etching. At this time, the SiO ₂ film 4 is not completely removed by etching, and
As shown in (a), a part of the SiO ₂ film 4 is replaced with the SiN _x film 2
The sidewall 4a of the gate pattern 3a is left in the gate pattern 3a.
Then, a photoresist film 7 is formed on the surface, the gate electrode pattern 7a is opened, and Ga in the gate pattern 3a is formed.
The operating layer 1a of the As substrate 1 is exposed. A gate metal is vapor-deposited here, the photoresist film 7 is removed, and the gate electrode 8 is formed [FIG.2 (b)].

In this embodiment, the gate length of the gate electrode 8 can be shortened by the width of the side walls 4a on both sides in the gate pattern, and the gate electrode 8 having a short gate length can be formed.

[0030] In the above embodiment, by using the SiN _X film as a first protective film, Si as the second protective film
Although the O ₂ film was used, conversely, SiO ₂ was used as the first protective film.
Using the film, it may be used SiN _X film as a second protective film. Further, although the lift-off method is used for forming the drain, source and gate electrodes, it may be formed by an etching method. Further, in the above embodiment, MESFET
However, the present invention can be applied to a device having a similar gate electrode, such as HEMT. Further, the recess structure may be combined so that the gate electrode is provided in the recess portion recessed in the surface of the substrate.

Although not shown, when a large number of devices are to be manufactured on the same wafer, in the mask pattern for patterning the first protective film, the design values of the gate length and the gate-source distance are set for each device. If changed, elements having different gate lengths and different gate-source distances can be simultaneously formed on the same wafer by the same process.

[0032]

According to the present invention, the source region and the drain region can be formed by self-alignment, and the gate-source distance and the gate-drain distance can be accurately formed.

Moreover, since the pattern and dimensions of the gate electrode, the source region, the drain region and the like can be set arbitrarily and independently at the time of patterning the first protective film, the distance between the gate and the source and the gate and the drain can be set. The distances can be set independently of each other to have arbitrary dimensions. Therefore, it is possible to form a semiconductor device in which the distance between the gate and the source and the distance between the gate and the drain are different from each other, and to fabricate devices having different gate lengths and different distances between the gate and the source simultaneously on the same wafer by the same process. You can also As a result, it becomes possible to manufacture a semiconductor device having a structure that cannot be manufactured by the sidewall gate method or the like.

[Brief description of drawings]

1 (a) (b) (c) (d) (e) (f) (g)
(H) (i) is a MESFET according to an embodiment of the present invention
FIG. 6 is a cross-sectional view showing the method of manufacturing.

2A and 2B are MEs according to another embodiment of the present invention.
It is sectional drawing which shows a part of manufacturing method of SFET.

3 (a) (b) (c) (d) (e) (f) (g)
(H) (i) (j) is sectional drawing which shows the manufacturing method of MESFET by a prior art example.

[Explanation of symbols]

1 GaAs substrate 1b Source side n ⁺ layer 1c Drain side n ⁺ layer 2 SiN _x film 3a Gate pattern 3b Source pattern 3c Drain pattern 4 SiO ₂ film 6b Source electrode 6c Drain electrode 8 Gate electrode

Claims (1)

[Claims] 1. A step of forming a first protective film on a compound semiconductor substrate having an operating layer, and simultaneously opening a gate pattern, a source pattern and a drain pattern in the first protective film, and the first protective film. Filling the gate pattern opened in the film with a second protective film to close the gate pattern; and implanting an impurity into the source pattern region and the drain pattern region of the substrate using the first and second protective films as a mask, Forming a drain region; forming a source electrode and a drain electrode on the source region and the drain region; and thereafter, removing the second protective film to form a gate pattern region on the substrate. And a step of forming an electrode.