JPH06195989A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To quickly confirm the data erasure as to each of plural memory- blocks capable of writing-in and erasing electrical information. CONSTITUTION:A circuit by which a flag is raised when data are erased and flag-read circuits 17a to 17e detecting whether the flag is raised in the circuit or not at the time of a write-in are provided on each of plural memory-blocks 1a to 1e capable of writing-in and erasing in a batch electrical information in a memory array 1. Thus, confirmation, that is, an erasure checking whether data in each of memory-blocks 1a to 1e are erased or not is confirmed by whether the flag is raised or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to the electrical writing of information,
The present invention relates to a nonvolatile semiconductor memory device having a erasable and readable nonvolatile memory.

[0002]

2. Description of the Related Art FIG. 4 shows the IEEE Journal of Solid-State Ci
rcuits, Vol.23, No5 October 1988. Block diagram showing a conventional flash EEPROM shown on pages 1157 to 1163,
FIG. 5 is a sectional structural view of a memory transistor having a floating gate which constitutes a memory cell, and FIG. 6 is a block diagram showing details of the memory block 1a shown in FIG. In the figure, reference numeral 1 denotes a memory cell array, and the memory cell array 1 has a large number of memory cells each composed of a memory transistor having a floating gate as shown in FIG. 5 arranged in a matrix with a plurality of rows and columns. It is divided into a plurality of memory blocks 1a to 1d, which are arranged in an array and are the smallest blocks that can be electrically collectively erased.

In the memory transistor, as shown in FIG. 5, a source diffusion region 22 and a drain diffusion region 23 are formed on a semiconductor substrate 21 at predetermined intervals, and the source diffusion region is formed.
22 and the drain diffusion region 23, each having a thickness of 100 Å
The floating gate 24 and the control gate 25 are arranged with a certain degree of oxide film between them, and it is possible to inject electrons into the floating gate 24 and emit electrons from the floating gate 24 by utilizing the tunnel phenomenon. . At the time of electron injection, a program voltage of about 6.5 V is applied to the drain diffusion region 23, a write voltage V _pp (12 V) is applied to the control gate 25, and the source diffusion region 22 is grounded.

As a result, electron-hole pairs are generated near the drain diffusion region 23, the holes flow to the ground potential through the semiconductor substrate 21, and the electrons flow in the channel direction to flow into the drain diffusion region 23. Also, some electrons are accelerated by the electric field between the floating gate 24 and the drain diffusion region 23 and injected into the floating gate 24. As a result, the threshold voltage of the memory cell transistor is increased. This state is defined as storage of information "0".

On the other hand, when electrons are emitted, the drain diffusion region 23 is opened, the control gate 25 is grounded, and the write voltage V _pp is applied to the source diffusion region 22. A tunnel phenomenon occurs due to the potential difference between the source diffusion region 22 and the floating gate 24, and electrons are extracted from the floating gate 24, which lowers the threshold value of the memory cell transistor. This state is defined as storage of information "1".

The memory blocks 1a to 1d in the memory cell array 1 have substantially the same structure.
1a will be specifically described. Memory block 1a is third
As shown in the figure, the drains of the memory transistors forming the memory cells arranged in the same column are bit lines B for each column.
Bit lines BL ₁ , BL ₂ ~ B connected to L ₁ , BL ₂ ~ BL ₃ …
One end of L ₃ ... Is connected to the Y gate 2, and the sources of the memory transistors are bundled and connected to the ground or high potential via the source line switch 3.

On the other hand, the control gates of the memory transistors forming the memory cells arranged in the row direction are connected to the X decoder 4 via the word lines WL ₁ , WL _{2 to} WL ₃ ... For each row, and each Y gate is also connected. 2 is the signal lines Y ₁ , Y ₂ , Y ₃
Are connected to the Y-decoder 5 via, and column selection signals and row selection signals are respectively supplied from these.
An address signal is input from the address register 6 to the Y decoder 5 and the X decoder 4. The Y gate 2 is composed of a switch transistor, and is connected to a data input / output line I / O as shown in FIG. 6 via a write circuit 7, a sense amplifier 8 and an input / output buffer 9.

As shown in FIG. 4, the input / output buffer 9 has D ₀₀ to
While inputting / outputting D ₀₇ , the command signal of the input data is given to the command register 11, and the command register 11 gives the command signal to the command decode 12.

Reference numeral 10 is an input signal buffer, which includes a write enable signal / WE and an output enable signal / O.
E and the chip enable signal / CE are input, and control signals are output to the address register 6, the command register 11, the command decoder 12, the input / output buffer 9 and the write circuit 7 based on these signals.

The command decoder 12 is an input / output signal buffer
Based on the control signal from 10, a command signal is output to the source line switch 3, the verify voltage generating circuit 13, and the program voltage generating circuit 14. The verify voltage generation circuit 13 outputs the generated verify voltage to the X decoder 4, and the program voltage circuit 14 outputs the generated program voltage to the X decoder 4.
It outputs to the decoder 4, the Y decoder 5, and the Y gate 2.

Next, the operation of the conventional apparatus will be described based on the flowcharts shown in FIGS. 7 and 8 and the timing charts shown in FIGS. 9 (h) and 10 (h) correspond to the steps shown in FIGS. 7 and 8. In this type of flash EEPROM, the programming / erasing mode is set by a combination of input data, that is, the rising data of the write enable signal / WE shown in FIGS. 9 (d) and 10 (d).

First, the write operation will be described with reference to FIGS. 7 and 9. First, the voltage V shown in Fig. 9 (f) and 9 (g)
_cc and _Vpp are raised in step S1, and then the write enable signal / WE is lowered. At the timing of the fall of the write enable signal / WE, the input data 40H instructing the write mode (program mode) shown in FIG. 9 (e) is latched in the command register 11. afterwards,
The input data is decoded by the command decoder 12 or the like, and the operation mode becomes the program mode.

Next, in step S2, the write enable signal / WE is fallen again, the addresses A _{0 to} A ₁₄ externally input to the address register 6 are latched, and the data D is risen at the rising edge of the write enable signal / WE. _in is latched by the write circuit 7. In step S3, a program pulse is generated from the program voltage generation circuit 14 and applied to the decoder 4 and the Y decoder 5, and the above-mentioned write operation, that is, the write operation of "0" is performed.

After the write time in step S3,
The write enable signal / WE is dropped at S4, and the result is shown in Figure 9 (e).
The data (C
OH) is input and latched in the command register 11.
Then, as the write enable signal / WE rises, the operation mode becomes program verify as shown in FIG. 9 (a). At this time, a program verify voltage (up to 6.5 V) is generated inside the chip by a verify voltage generating circuit or the like, and applied to the decoder 4 and the Y decoder 5. As a result, the voltage applied to the control gate of the memory cell array 1 becomes higher than that during normal reading (up to 5 V), and those exhibiting an insufficient threshold shift are easily turned on, and a write failure can be found.

In step S6, the data is read and the write data is checked. If it is determined in step S7 that the writing is defective, further steps S1 to S6 are performed.
The process is performed to write. If the writing has been done in the determination in step S7, the mode is set to the reading mode in step S8, and the program ends.

Next, the erase operation will be described with reference to FIGS. First, V _cc and V _pp are raised, and step S11
Then, "0" is written in all the bits according to the writing process shown in FIG. This is to prevent the memory cells from being over-erased when the erased memory cell data is further erased.

In step S12, the write enable signal / WE shown in FIG. 10 (d) is lowered and the erase command 20H shown in FIG. 10 (e) is input. Subsequently, in step S13, an erase confirmation (verify) command is input, and an erase pulse is internally generated at the rise of the write enable signal / WE. Via the source line switch 3, V _pp is applied to the source of the memory transistor that constitutes the memory cell. After that, V _pp is applied to the source line until the write enable signal / WE falls. At the same time, the address signal is latched in the address buffer 6 at the fall.

After the erase operation is executed in step S14, the erase verify command AOH shown in FIG. 10 (e) is input at the fall of the write enable signal / WE in step S15 to set the erase verify mode. In this erase verify mode, an erase verify voltage (up to 3.2 V) is applied to the X decoder 4 by the verify voltage generating circuit 13, and the voltage applied to the control gates of the memory transistors forming the memory cell is set at the normal read time (5
It becomes lower than V), and it becomes difficult to turn on a memory cell which is not sufficiently erased. In this way, erasure is confirmed.

Next, in step S16, the data is read to confirm the erasure. If it is determined in step S17 that the erasure is insufficient, the process returns to step S12 to repeat the erasure, and if the erasure is sufficient, step S18
In step S19, it is determined whether the verified address is the final address. If the final address is not the final address, the address is incremented in step S19, and the process returns to step S15 to input the verify code of the erase data of the next address. On the other hand, if it is determined in step S18 that the address is the final address, the read mode is executed in step S20 to confirm the erase and end.

[0020]

By the way, in the conventional device as described above, when writing in block units,
There is a problem in that whether or not the data in the block has been erased is checked by performing a reading process in the block, and if the data is not erased, the block must be written after the erase. The present invention has been made in view of the above circumstances, and its object is to provide means for setting a flag when data is erased for each block, and means for detecting whether or not the flag is set at the time of writing. By providing the above, when writing to a predetermined block, it is possible to confirm by detecting a flag set by erasing instead of reading and confirming whether the data in the block is erased or not. A semiconductor memory device.

[0021]

A nonvolatile semiconductor memory device according to the present invention is a memory cell array having one or a plurality of memory blocks formed by arranging a large number of memory cells in an array in the row and column directions. And an address signal input from the outside is decoded, and row and column directions are selected.
In a device that includes a decoder and a Y decoder, and a sense amplifier that detects the content of information stored in a memory cell, and is capable of electrically writing and erasing in each memory block, Means for setting a flag when the data in the memory block is erased, and means for detecting the flag when writing to the memory cell in the block and confirming whether or not the data in the memory block is erased And is provided.

[0022]

According to the present invention, this makes it possible to check whether or not the data in the memory block is erased by checking whether or not a flag is set, and the data writing process can be swiftly completed.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to the present invention, and FIG. 2 is a partial detailed block diagram thereof. In the figure, 1 is a memory cell array, 2 is a Y gate, 3
Indicates a source line switch. Memory cell array 1
Is composed of a plurality of memory cells each composed of a memory transistor having a floating gate 24 similar to that shown in FIG. It is divided into unit memory blocks 1a to 1e.

Flag read circuits 17a to 17e are provided between the memory cell array 1 and the Y gate 2 in correspondence with the memory blocks 1a to 1e. The drains of the memory transistors of the memory cells arranged in the column direction that form the memory cell array 1 are connected to bit lines BL ₁ , BL ₂ , BL ₃ ...
One end of L ₁ , BL ₂ , BL ₃ ... Is connected to the Y gate 2. The sources of the memory transistors are bundled and connected to the ground or high potential via the source line switch 3.

On the other hand, the gates of the memory transistors forming the memory cells arranged in the row direction are word lines WL for each row.
₁ , WL ₂ , WL ₃ ... Is connected to the X decoder 4, and the Y gate 2 is connected to the Y decoder 5 via signal lines Y ₁ , Y ₂ , Y ₃ ... , Row selection signal is given.

An address signal is inputted from the address register 6 to the X decoder 4 and the Y decoder 5, and the Y gate 2 is composed of a switch transistor interposed in each bit line BL ₁ , BL ₂ , BL ₃ ... I / O via the write circuit 7, the sense amplifier 8 and the input / output buffer 9
It is connected to the O line.

In the nonvolatile semiconductor memory device according to the present invention, as shown in FIG. 2, the bit line BL ₁ of the memory block 1a is connected to the flag setting circuit 16 constituted by the memory transistor. The memory transistors that form the flag setting circuit 16 have a drain on the bit line BL ₁
, And the source is connected to the source line switch 3, respectively,
Further, the control gate is connected to the flag read circuit 17a.

In the memory transistor constituting the flag setting circuit 16, the control gate is grounded when the data in the memory block 1a is erased, and the write voltage is applied to the source diffusion region to extract electrons from the floating gate. "1" is memorized. Further, the flag read circuit 17a reads out data from the memory transistor forming the flag setting circuit 16 at the time of writing data, and when the information "1" is stored,
In other words, if the flag is set, it is possible to confirm that the memory block 1a is in the erased state.

The relationship between the other memory blocks 1b to 1e and the flag read circuits 17b to 17e is the same as the relationship between the memory block 1a and the flag read circuit 17a described above. Other configurations are substantially the same as those of the conventional device shown in FIGS. 4 and 5, and corresponding parts are designated by the same reference numerals. That is, the input / output buffer 9 outputs the command signal of the input data to the command register 11, and the command register 11 outputs the command signal to the command decode 12.
Reference numeral 10 is an input signal buffer to which the write enable signal / WE, the output enable signal / OE, and the chip enable signal / CE are input, and based on this, the address register 6, the command register 11, the command decoder 12,
Control signals are output to the input buffer 9 and the writing circuit 7, respectively.

The command decoder 12 is an input signal buffer 10.
An instruction signal is output to the source line switch 3, the verify voltage generation circuit 13, and the program voltage generation circuit 14 based on the control signal from the. The verify voltage generation circuit 13 outputs the generated verify voltage to the X decoder 4, and the program voltage circuit 14 outputs the generated program voltage to the X decoder 4.
It outputs to the decoder 4, the Y decoder 5, and the Y gate 2.

Next, the write operation of the nonvolatile semiconductor memory device according to the present invention will be described with reference to the flow chart shown in FIG. First, in step S31, the flag read circuit 17a reads the flag read prior to the write operation, and in step S31 it is determined whether the information of the memory transistor in the flag setting circuit 16 is "1" and it is not "1". In this case, erase the blocks 1a to 1e in step S33,
If it is "1", the voltages V _cc and V _pp are raised, and then the write enable signal / WE is lowered in step S34. After that, at the fall timing of the write enable signal / WE, the input data instructing the write mode (program mode) is latched in the command register 11. After that, the input data is decoded by the command decoder 12 or the like, and the operation mode becomes the program mode.

Next, in step S34, the write enable signal / WE is fallen again, and the addresses A _{0 to} A ₁₄ externally input to the address register 6 are latched.
Data D ₀₀ ~ at the rising edge of the write enable signal / WE
D ₀₇ is latched by the writing circuit 7. In step S35,
A program pulse is generated from the program voltage generation circuit 14 and applied to the X decoder 4 and the Y decoder 5, and a write operation, that is, a write operation of "0" is performed.

After the write time in step S36, the write enable signal / WE is lowered in step S37, the data instructing the program verify mode shown in FIG. 9 (e) is input and latched in the command register 11. .
Then, when the write enable signal / WE rises, the operation mode becomes program verify. At this time, a program verify voltage (up to 6.5 V) is generated inside the chip by a verify voltage generating circuit or the like, and applied to the X decoder 4 and the Y decoder 5. As a result, the voltage applied to the control gate of the memory cell array 1 becomes higher than that at the time of normal reading (5V), and those exhibiting an insufficient threshold shift are easily turned on, and a write failure can be found.

Next, in step S38, the data is read and the write data is checked. If it is determined in step S39 that the writing is defective, the processes of steps S34 to S38 are further performed to perform writing. If writing is done in the judgment of step S39, step S4
At 0 the mode is set to read mode and the program ends.

[0035]

As described above, in the device of the present invention, means for setting a flag when the data in the memory block corresponding to each of the divided memory blocks in the memory cell array 1 is erased, and a flag for writing the flag Since a means for confirming whether or not is set up is provided, it is possible to perform erasure check by a flag instead of confirmation by reading at the time of writing data, which enables quick writing. Is played.

[Brief description of drawings]

FIG. 1 is a block diagram of a device of the present invention.

FIG. 2 is a detailed block diagram showing the connection relationship of one memory block of the device of the present invention shown in FIG.

FIG. 3 is a flowchart showing a processing process at the time of writing by the device of the present invention.

FIG. 4 is a block diagram of a conventional device.

FIG. 5 is a cross-sectional structure diagram of a memory transistor that constitutes a memory cell.

FIG. 6 is a detailed block diagram showing the connection relationship of one memory block of the conventional device shown in FIG.

FIG. 7 is a flowchart showing a processing process at the time of writing in the conventional device.

FIG. 8 is a flowchart showing a processing process at the time of erasing of the conventional device.

FIG. 9 is a timing chart of signals at the time of writing.

FIG. 10 is a timing chart of signals at the time of erasing.

[Explanation of symbols]

 1 memory cell array 1a to 1e memory block 2 Y gate 3 source line switch 4 X decoder 5 Y decoder 6 address register 16 flag setting circuit 17a to 17d flag read circuit

Claims (1)

[Claims] 1. A memory cell array having one or a plurality of memory blocks configured by arranging a large number of memory cells in an array in the row and column directions, and an address signal input from the outside to decode the row and A non-volatile semiconductor that includes an X-decoder and a Y-decoder for selecting in the column direction and a sense amplifier that detects the content of information stored in a memory cell, and is capable of electrically writing and erasing for each memory block. In the storage device, means for setting a flag for each memory block when the data in the memory block is erased, and data for the memory block by detecting the flag when writing to the memory cell in the block And a means for confirming whether or not the data has been erased.