JPH06195204A - Multilevel multiplier - Google Patents

Abstract

PURPOSE:To share plural multilevel signals by means of setting a bit signal to be a multilevel without enlarging a circuit scale by providing logic circuit means and multilevel circuit means which are connected to the logic circuit means and output the prescribed multilevel signal based on a logical result. CONSTITUTION:A ternary multiplier consists of AND circuit elements (AND elements) 11-26 be ing the logic circuit means, multilevel function elements 27-78 being the multilevel circuit means, AND circuit elements (AND elements) 79-84, OR circuit elements (OR elements) 85 and 86, AND circuit elements (AND elements) 87-89, OR circuit elements (OR elements) 90-92, a one-bit delay circuit 93 and input/output elements 94-110. The AND element 11 inputs binary input signals Xo, Yo, xo and yo and outputs AND, for example. The multilevel function element 27 inputs output from the AND element 11 and outputs a ternary threshold. The multilevel function element 28 inputs output from the AND element 11 and outputs a binary threshold.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier which can be used for image processing, signal processing for communication, font processing for laser printers, microprocessors and the like.

[0002]

2. Description of the Related Art In general, a multiplier is a kind of arithmetic and logic unit of a computer and is a circuit dedicated to multiplication. Here, multiplication refers to formation of partial products obtained as a product of a multiplicand and a part (one or more bits) of a multiplier and addition of these formed partial products.

In recent computers, multiplication has been incorporated as a standard function, and various methods have been used to increase the speed for improving arithmetic performance.

As a method for speeding up the above, the number of partial products and the number of generating mechanisms are reduced, and the booth method in which each mechanism is made simple, or addition of partial products is parallelized as much as possible. A method based on a Wallis tree with a reduced addition time is known.

Further, as a method applied to a very large scale integrated circuit (VLSI), there is a method in which a basic circuit is arranged in a regular two-dimensional array, and a multiplier using this method is generally an array. Multipliers are known.

[0006]

However, in the above-described conventional multiplication method that handles only binary signals, there is a problem in that it is not possible to theoretically create a time margin and to perform multiplication stably at high speed. was there.

In the conventional serial and parallel multiplication methods, 2
There is a problem that the value signal and the quaternary signal can be shared and multiplication cannot be performed at high speed.

In the conventional binary electronics, if the amount of information to be processed increases dramatically, it is required to develop electronic devices and arithmetic units constituting hardware at high speed and with high functionality. However, there is a limit to information processing using binary electronics technology, and in binary electronics, if the amount of data processing increases, it is extremely difficult to realize high speed and high functionality. there were.

In view of the problems in the above-described conventional multiplication method, the present invention provides a multi-valued multiplier that can share a plurality of multi-valued signals by making the bit signals multi-valued without increasing the circuit scale.

[0010]

According to the present invention, there are provided a logic circuit means for inputting a plurality of signals and outputting a predetermined logic result, and a predetermined multi-valued signal connected to the logic circuit means based on the logic result. And multi-valued circuit means for outputting

[0011]

In the multivalued multiplier of the present invention, the logic circuit means inputs a plurality of signals and outputs a predetermined logic result, and the multivalued circuit means is connected to the logic circuit means and predetermined based on the logic result. The multi-valued signal of is output.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multilevel multiplier according to the present invention will be described below with reference to the drawings.

FIG. 1 constituted by FIGS. 1a and 1b
FIG. 1 is a block diagram showing a configuration of a ternary multiplier that is a first embodiment of a multivalued multiplier of the present invention.

The ternary multiplier shown in FIG. 1 includes logical product circuit elements (AND elements) 11 to 26 which are logical circuit means, multivalued functional elements 27 to 78 which are multivalued circuit means, and logical product circuit elements (AND element). ) 79 to 84, OR circuit elements (OR elements) 85 and 86, AND circuit elements (AND elements) 87 to 89, OR circuit elements (O
R element) 90 to 92, 1-bit delay circuit 93, input / output element 94 to
It is composed of 110.

Next, the above-mentioned components will be described in detail.

The input / output element 94 inputs a ternary output signal X and outputs a binary input signal X _0.
Is a binary input signal X by inputting a ternary output signal X
_1/2 is output, and the input / output element 96 inputs the ternary output signal X and outputs the binary input signal X ₁ .

The input / output element 97 inputs the ternary output signal Y and outputs the binary input signal Y _0.
Is a binary input signal Y by inputting a ternary output signal Y
_1/2 is output, and the input / output element 99 inputs the ternary output signal Y and outputs the binary input signal Y ₁ .

The input / output element 100 inputs a binary output signal x and outputs a binary input signal x _0.
1 inputs a binary output signal x and outputs a binary input signal x ₁ .

The input / output element 102 inputs a binary output signal y and outputs a binary input signal y _0.
3 inputs binary output signal y and outputs binary input signal y ₁ .

The AND element 11 has a binary input signal X
₀ , Y ₀ , x ₀ , y ₀ are input and the logical product of them is output.

The AND element 12 has a binary input signal X.
₀ , Y _1/2 , x ₀ , y ₀ are input and the logical product of them is output.

The AND element 13 has a binary input signal X.
₀ , Y ₁ , x ₀ , y ₀ are input and the logical product of them is output.

The AND element 14 has a binary input signal X.
₀ , Y ₀ , x ₀ , y ₁ are input and the logical product of them is output.

The AND element 15 has a binary input signal X
Input _1/2 , Y ₀ , x ₀ , y ₀ and output the logical product of them.

The AND element 16 has a binary input signal X.
Input _1/2 , Y _1/2 , x ₀ , y ₀ , take the logical product of them, and output them.

The AND element 17 has a binary input signal X.
Input _1/2 , Y ₁ , x ₀ , y ₀ and output the logical product of them.

The AND element 18 has a binary input signal X.
Input _1/2 , Y ₀ , x ₀ , y ₁ and output the logical product of them.

The AND element 19 has a binary input signal X.
Input ₁ , Y ₀ , x ₀ , y ₀ and output the logical product of them.

The AND element 20 has a binary input signal X.
₁ , ₁ , Y _1/2 , x ₀ , y ₀ are input and the logical product of them is output.

The AND element 21 has a binary input signal X
₁ , ₁ , Y ₁ , x ₀ , y ₀ are input and the logical product of them is output.

The AND element 22 has a binary input signal X.
₁ , ₁ , Y ₀ , x ₀ , y ₁ are input and the logical product of them is output.

The AND element 23 receives the binary input signal X
₀ , Y ₀ , x ₁ , y ₀ are input and the logical product of them is output.

The AND element 24 has a binary input signal X.
₀ , Y _1/2 , x ₁ , y ₀ are input and the logical product of them is output.

The AND element 25 receives the binary input signal X
Input ₀ , Y ₁ , x ₁ , y ₀ and output the logical product of them.

The AND element 26 has a binary input signal X.
₀ , Y ₀ , x ₁ , y ₁ are input and the logical product of them is output.

The multi-valued functional element 27 inputs the output from the AND element 11 and outputs a ternary threshold value.
Receives the output from the AND element 11 and outputs a binary threshold value.

The multi-valued functional element 29 inputs the output from the AND element 12 and outputs a ternary threshold value.
Receives the output from the AND element 12 and outputs a binary threshold value.

The multi-valued functional element 31 inputs the output from the AND element 13 and outputs a ternary threshold value.
Receives the output from the AND element 13 and outputs a binary threshold value.

The multi-valued functional element 33 inputs the output from the AND element 14 and outputs a ternary threshold value.
Inputs the output from the AND element 14 and outputs a binary threshold value.

The multi-valued functional element 35 inputs the output from the AND element 15 and outputs a ternary threshold value.
Receives the output from the AND element 15 and outputs a binary threshold value.

The multi-valued functional element 37 inputs the output from the AND element 16 and outputs a ternary threshold value.
Outputs the binary threshold value by inputting the output from the AND element 16, and the multi-valued functional element 39 inputs the output value from the AND element 16 and outputs the binary threshold value.

The multi-valued functional element 40 inputs the output from the AND element 17 and outputs a ternary threshold value, and the multi-valued functional element 41
Outputs the binary threshold value by inputting the output from the AND element 17, and the multi-level functional element 42 inputs the output value from the AND element 17 and outputs the binary threshold value.

The multi-valued functional element 43 inputs the output from the AND element 18 and outputs a ternary threshold value.
Outputs the ternary threshold value by inputting the output from the AND element 18, and the multi-valued functional element 45 inputs the output value from the AND element 18 and outputs the ternary threshold value. Value Function element 46
Receives the output from the AND element 18 and outputs a binary threshold value.

The multi-valued functional element 47 inputs the output from the AND element 19 and outputs a ternary threshold value.
Receives the output from the AND element 19 and outputs a binary threshold value.

The multi-valued functional element 49 inputs the output from the AND element 20 and outputs a ternary threshold value.
Outputs the binary threshold value by inputting the output from the AND element 20, and the multi-valued functional element 51 inputs the output value from the AND element 20 and outputs the binary threshold value.

The multi-valued functional element 52 inputs the output from the AND element 21 and outputs a ternary threshold value, and the multi-valued functional element 53
The multi-valued functional element 54 inputs the output from the AND element 21 and outputs a three-valued threshold, and outputs the three-valued threshold by inputting the output from the AND element 21. Value function element 55
Outputs the ternary threshold value by inputting the output from the AND element 21, and the multi-valued functional element 56 inputs the output value from the AND element 21 and outputs the binary threshold value.

The multi-valued functional element 57 inputs the output from the AND element 22 and outputs a ternary threshold value, and the multi-valued functional element 58
Outputs the ternary threshold value by inputting the output from the AND element 22, and the multi-valued functional element 59 inputs the output value from the AND element 22 and outputs the binary threshold value. Value Function element 60
Outputs the binary threshold value by inputting the output from the AND element 22, and the multi-level functional element 61 inputs the output value from the AND element 22 and outputs the binary threshold value.

The multi-valued functional element 62 inputs the output from the AND element 23 and outputs a ternary threshold value.
Inputs the output from the AND element 23 and outputs a binary threshold value.

The multi-valued functional element 64 inputs the output from the AND element 24 and outputs a ternary threshold value, and the multi-valued functional element 65
The multi-valued functional element 66 inputs the output from the AND element 24 and outputs the three-valued threshold value, and outputs the three-valued threshold value by inputting the output from the AND element 24. Value Function element 67
Inputs the output from the AND element 24 and outputs a binary threshold value.

The multi-valued functional element 68 inputs the output from the AND element 25 and outputs a ternary threshold value.
The multi-valued functional element 70 inputs the output from the AND element 25 and outputs a ternary threshold value, and the multi-valued functional element 70 inputs the output from the AND element 25 and outputs a binary threshold value. Value Function element 71
Outputs the binary threshold value by inputting the output from the AND element 25, and the multi-valued functional element 72 inputs the output value from the AND element 25 and outputs the binary threshold value.

The multi-valued functional element 73 inputs the output from the AND element 26 and outputs a binary threshold value.
Outputs the binary threshold value by inputting the output from the AND element 26, and the multi-level functional element 75 inputs the output value from the AND element 26 and outputs the binary threshold value. Value Function element 76
Outputs the ternary threshold value by inputting the output from the AND element 26, and the multi-valued functional element 77 inputs the output value from the AND element 26 and outputs the binary threshold value. Value Function element 78
Receives the output from the AND element 26 and outputs a binary threshold value.

The input / output element 104 is a ternary carry input C.
Is input to output a carry input signal C ₀ ,
Reference numeral 105 denotes a ternary carry input C, which outputs a carry input signal C _1/2 , and input / output element 106, which receives a ternary carry input C, outputs a carry input signal C ₁ . .

The AND element 79 is a multi-valued functional element 52, 57, 6
Inputting one of the outputs from 8 and 73 and input / output element 104
The carry input signal C ₀ output from the above is input and the logical product of them is output.

The AND element 80 is a multi-valued functional element 43, 53, 5
One of the outputs from 8, 64, 69, and 74 is input, and the carry input signal C _1/2 output from the input / output element 105 is input and the logical product of them is output.

The AND element 81 is a multi-valued functional element 40, 44, 4
One of the outputs from 9, 54, 59, 65, 70, and 75 is input and the carry input signal C output from the input / output element 106 is input.
Input ₁ and output the logical product of them.

The OR element 85 inputs the outputs from the AND elements 79, 80 and 81 and outputs a carry output signal (C ') which is the logical sum of them.

The 1-bit delay circuit 93 inputs the carry output signal (C ') output from the OR element 85 and outputs the carry output C'.

Input / output element 109 receives carry output C ′ output from 1-bit delay circuit 93 and outputs carry output C ′ ₂ , and input / output element 110 represents 1-bit delay circuit.
The carry output C ′ output from 93 is input and the carry output C ′ ₁ is output.

The AND element 82 is a multi-valued functional element 37, 41, 5
One of the outputs 0, 60, 71, and 76 is input, and the carry input signal C ₀ output from the input / output element 104 is input to output a logical product of them.

The AND element 83 is a multi-valued functional element 27, 29, 3
One of the outputs from 1, 33, 35, 38, 47, 55, 62, 77 is input, and the carry input signal C _1/2 output from the input / output element 105 is input and the logical product of them is calculated. Output.

The AND element 84 is a multi-valued functional element 28, 30, 3
One of the outputs from 2, 34, 36, 45, 48, 56, 63 and 66 is input and the carry input signal C ₁ output from the input / output element 106 is input and the logical product of them is output. .

The OR element 86 inputs the outputs from the AND elements 82, 83 and 84 and outputs a multiplication output Z which is the logical sum of them.

The input / output element 107 receives the multiplication output Z, outputs the multiplication output Z ₁ to the OR element 90, and outputs the input / output element 108.
Inputs the multiplication output Z and outputs the multiplication output Z _1/2 as an OR element 91
Output to.

The AND element 87 inputs one of the outputs from the multi-valued functional elements 46 and 67, inputs the carry input signal C ₀ output from the input / output element 104, and outputs a logical product of them. .

The AND element 88 is a multi-valued functional element 42, 51, 6
Input / output element 105 while inputting one of the outputs from 1, 72
The carry input signal C _1/2 output from the above is input and the logical product of them is output.

The AND element 89 inputs one of the outputs from the multi-valued functional elements 39 and 78, inputs the carry input signal C ₁ output from the input / output element 106, and outputs a logical product of them. .

The OR element 92 inputs the outputs from the AND elements 87, 88 and 89 and outputs the multiplication output Z'which is the logical sum of them to the OR elements 90 and 91, respectively.

The OR element 90 outputs the multiplication result Z ₂ which is the logical sum of the output from the input / output element 107 and the multiplication output Z ′ from the OR element 92.

The OR element 91 outputs the multiplication result Z ₁ which is the logical sum of the output from the input / output element 108 and the multiplication output Z ′ from the OR element 92.

As the multi-level functional element, a quantizing functional element can be used. Quantization functional element is an element that uses the quantum mechanical property that the wave nature of electrons and electrons can only be in discontinuous energy states as the operating principle and has multivalued logic. Level element,
This is called a quantum wave device.

The inputs X and x in FIG. 1 are obtained by the binary input circuit in FIG.

The binary input circuit shown in FIG. 2 includes NOT circuit elements (NOT elements) 111 and 112, AND elements 113 to 115,
It is composed of an AND element 116 and an OR element 117.

Next, the operation of the binary input circuit shown in FIG. 2 will be described.

The NOT element 111 inputs and outputs the 2-bit parallel binary input signal X ₂ , and the NOT element 112
Inputs and outputs a 2-bit parallel binary input signal X ₁ .

The AND element 113 inputs the output from the NOT element 111 and the binary input signal X ₁ and outputs a logical product of them.
The AND element 114 outputs the logical product of the inputs of the output from the element 113 and 1/2 as well as the NOT element.
Input the output from 112 and input binary signal X
Input ₂ and output the logical product of them.

The OR element 117 inputs the output from the AND element 116 and the output from the AND element 114 and outputs a ternary output signal X which is the logical sum of them.

The AND element 115 outputs the binary input signal X
_A binary input signal X ₂ is input while ₁ is input, and a binary output signal x which is a logical product of them is output.

The inputs Y and y in FIG. 1 are obtained by the binary input circuit in FIG.

The binary input circuit of FIG. 3 is similar to the binary input circuit of FIG. 2 in that the NOT elements 118, 119, AN.
It is composed of D elements 120 to 122, an AND element 123, and an OR element 124.

Next, the operation of the binary input circuit of FIG. 3 will be described.

The NOT element 118 receives and outputs a 2-bit parallel binary input signal Y ₂ , and outputs the NOT element 119.
Inputs and outputs a 2-bit parallel binary input signal Y ₁ .

The AND element 120 inputs the output from the NOT element 118 and the binary input signal Y ₁ and outputs a logical product of them.
The AND element 121 inputs the output from the element 120 and 1/2 to input the logical product of them, and the AND element 121
Input the output from 119 and input binary signal Y
Input ₂ and output the logical product of them.

The OR element 124 inputs the output from the AND element 123 and the output from the AND element 121, and outputs a ternary output signal Y which is the logical sum of them.

The AND element 122 receives the binary input signal Y
_A binary input signal Y ₂ is input while ₁ is input, and a binary output signal y which is a logical product of them is output.

Further, the input C of FIG. 1 is obtained by the binary input circuit of FIG.

The binary input circuit of FIG. 4 is a NOT element.
125, 126, AND elements 127, 128, AND element 129,
It is composed of an OR element 130.

Next, the operation of the binary input circuit of FIG. 4 will be described.

The NOT element 125 inputs and outputs a 2-bit parallel binary input signal C ₂ , and outputs the NOT element 126.
Inputs and outputs a 2-bit parallel binary input signal C ₁ .

The AND element 127 inputs the output from the NOT element 125 and the binary input signal C ₁ and outputs a logical product of them.
The AND element 128 inputs the output from the element 127 and 1/2 to input the logical product of them, and the AND element 128
Input the output from 126 and input binary signal C
Input 2 and output the logical product of them.

The OR element 130 inputs the output from the AND element 129 and the output from the AND element 128 and outputs a ternary output signal C which is the logical sum of them.

Table 1 shows 2-bit parallel binary input signals X ₂ , X ₁ , Y ₂ , Y ₁ and ternary output signals X, x,
The code assignments of Y, y, and carry C ₂ , C ₁ , C are shown.

[0092]

[Table 1]

The equations (1), (2) and (3) are
The logical formula corresponding to Table 1 is shown.

[0094]

[Equation 1]

[0095]

[Equation 2]

[0096]

[Equation 3]

Table 2 shows the logic of the ternary multiplier, and Table 3 shows
The carry output is shown respectively.

[0098]

[Table 2]

[0099]

[Table 3]

The symbols attached to the multi-valued functional elements in FIG. 1 indicate the physical functions as shown in Table 4, but various logic elements can be used as these multi-valued functional elements.

[0101]

[Table 4]

These logic elements are shown in FIG. 2, FIG. 3 and FIG.
In addition to the binary input circuit shown in FIG. 1, it can be applied to a ternary logic circuit (equivalent circuit, OR circuit, AND circuit, etc.) that constitutes the ternary multiplier of FIG.

Table 5 shows the ternary multiplication outputs <Z ', Z> and the binary multiplication outputs <Z ₂ , Z ₁ >, and at the same time, shows the relation between the codes.

[0104]

[Table 5]

Although x ₀ and x _{1 in} FIG. 1 are shown by an equal value circuit, since they are binary signals in this case, they may be output signals of x bar and x. The same applies to y ₀ and y ₁ in FIG.

In Table 1, (1 / 2,0) is assigned to (1,0) of (x, X) and (1/2) is assigned to (1,0) of (y, Y). , 0) can be assigned.

In this embodiment, since the same synthesis can be performed in the case of (1/2, 0), the description will be omitted. In Table 2, the blank part is "0", but "1" is 1/2, "2" is 1 and "3" is (10), and the ternary multiplier of FIG. 1 is configured. Has been done.

Table 3 shows the carry output, but the blank is "0", "1" is 1/2, and "2" is 1 to form a ternary multiplier.

FIG. 5 is a permutation for outputting carry outputs C ₂ ′ and C ₁ ′, which is composed of 1-bit delay circuit 93 and input / output elements 109 and 110 shown in the ternary multiplier of FIG. The replacement circuit shown in FIG.
(B)) can be replaced.

[0110] substitution circuit of FIG. 5 (b), a carry output (C ') by entering the carry output C _1' output device 131 for outputting a carry output C ₁ output from the input element 131 ' Input, delay 1 bit, carry output C
Delay circuit 132 for outputting ₂ ', input / output element 13 for inputting carry output (C') and outputting carry output C1 _{/ 2} '
3, carry output C output from input / output element 133
Carry output C ₁ ′ by inputting _1/2 ′ and delaying it by 1 bit
Is formed by a delay circuit 134 that outputs

FIG. 6 is a block diagram showing the configuration of a ternary multiplier which is the second embodiment of the multivalued multiplier of the present invention.

The ternary multiplier shown in FIG. 6 has the same structure as the ternary multiplier shown in FIG. 1 except that the AND elements 211 to 226 are the same.
The input configuration of is different.

The inputs to the AND elements 211 to 226 shown in FIG. 6 will be described below. Since the other parts are the same as those in FIG. 1, description thereof will be omitted.

The AND element 211 outputs the binary input signal X
₀ , Y ₀ , x ₀ , y ₀ are input and the logical product of them is output, and the AND element 212 outputs the binary input signals X ₀ , Y
Input _1/2 and x ₀ , output the logical product of them, and AND
The element 213 inputs the binary input signals X ₀ , Y ₁ , x ₀ and outputs a logical product of them, and the AND element 214 inputs the binary input signals X ₀ , Y ₀ , x ₀ , y ₁ and outputs them. An AND element 215 outputs a logical product, and an AND element 215 inputs a binary input signal X _1/2 , Y ₀ , y ₀ , and outputs a logical product thereof, and an AND element 216 outputs a binary input signal X _1/2 , Y 0.
Input _1/2 and output the logical product of them and AND element 21
The AND element 218 inputs the binary input signals X _1/2 , Y ₁ and outputs a logical product of them, and the AND element 218 inputs the binary input signals X _1/2 , Y ₀ , y ₁ and calculates a logical product of them. The AND element 219 outputs the binary input signals X ₁ , Y ₀ ,
y ₀ is input, the logical product of them is output, and AND element 22
0 inputs binary input signals X ₁ and Y _1/2 and outputs a logical product of them, and AND element 221 inputs binary input signals X ₁ and Y ₁ and outputs a logical product of them, and AN
The D element 222 inputs the binary input signals X ₁ , Y ₀ , y ₁ and outputs a logical product of them, and the AND element 223 inputs the binary input signals X ₀ , Y ₀ , x ₁ , y ₀ and outputs them. AND element 224 inputs binary input signals X _O , Y _1/2 and x ₁ and outputs a logical product of them, and AND element 225 outputs binary input signals X ₀ and Y
_1, type x ₁ outputs a logical product of them, the AND element 226 is configured to output a logical product of them inputs the binary input signal X _0, Y _0, x _1, y ₁ There is.

FIG. 6 shows a case where the binary input and binary output circuits shown in FIGS. 7, 8 and 9 are used.
Indicates a value multiplier.

In FIGS. 2, 3 and 4, the binary input signal is converted into a ternary output signal, but in FIGS. 7, 8 and 9 the input is also binary and the output is a binary signal. To be

Tables 6 and 7 are almost the same as the multiplier logic already shown, except that x ₀ X
₀ , X _1/2 , X ₁ , x ₁ X ₀ are used, and y ₀
That is, Y ₀ , Y _1/2 , Y ₁ , and y ₁ Y ₀ are used.

[0118]

[Table 6]

[0119]

[Table 7]

Tables 6 and 7 also show the logical expressions from which the ternary multiplier of FIG. 6 is obtained.

The output signals X ₀ , x ₁ , X _1/2 , X of FIG.
₁ , x ₀ can be used as the binary input signals X ₀ , X _1/2 , X ₁ , x ₀ , x ₁ of the ternary multiplier of FIGS. 1 and 6, and the output signal Y _{0 of} FIG. y ₁ , Y _1/2 , Y ₁ , y ₀
Can also be used as Y ₀ , y ₁ , Y _1/2 , Y ₁ , y ₀ . Further, C ₀ , C _1/2 , and C ₁ in FIG. 9 can be replaced with the output signals C ₀ , C _1/2 , and C ₁ of the equivalent circuit in FIG.

The binary signal and the ternary signal are not used at the same time, but they can be used in combination.

FIG. 10, which is constituted by FIGS. 10a and 10b, is a block diagram showing the structure of a four-valued multiplier which is the third embodiment of the multivalued multiplier of the present invention.

In the four-valued multiplier of FIG. 10, a quantizing functional element (hereinafter referred to as a quantizing element) is used as a multi-valued functional element for explanation.

The four-valued multiplier shown in FIG.
307, AND elements 308 to 323, quantizing elements 324 to 375,
Input / output elements 376 to 378, AND elements 379 to 384, OR elements 385 and 386, input / output elements 387 to 390, OR element 391,
392 includes a 1-bit delay circuit 393 and input / output elements 394 and 395.

Next, the above components will be described in detail.

The input / output element 300 inputs the four-valued output signal X and outputs the binary input signal X _0.
1 inputs the four-value output signal X and outputs the binary input signal X _1/3 , and the input / output element 302 uses the four-value output signal X
Is input to output a binary input signal X _2/3 , and the input / output element 303 inputs a four-valued output signal X and outputs a binary input signal X ₁ .

The input / output element 304 inputs the four-valued output signal Y and outputs the binary input signal Y _0.
5 inputs a 4-value output signal Y and outputs a binary input signal Y _1/3 , and the input / output element 306 outputs a 4-value output signal Y 1.
, And outputs a binary input signal Y _2/3 , and the input / output element 307 inputs a four-valued output signal Y and outputs a binary input signal Y ₁ .

The AND element 308 outputs the binary input signal X
Input ₀ and Y ₀ and output the logical product of them.

The AND element 309 outputs the binary input signal X
Input ₀ and Y _1/3 and output the logical product of them.

The AND element 310 outputs the binary input signal X
Input ₀ and Y _2/3 and output the logical product of them.

The AND element 311 outputs the binary input signal X
Input ₀ and Y ₁ and output the logical product of them.

The AND element 312 receives the binary input signal X
Input _1/3 and Y ₀ and output the logical product of them.

The AND element 313 outputs the binary input signal X
_1/3 and Y _1/3 are input and the logical product of them is output.

The AND element 314 outputs the binary input signal X
Input _1/3 and Y _2/3 and output the logical product of them.

The AND element 315 outputs the binary input signal X
Input _1/3 and Y ₁ and output the logical product of them.

The AND element 316 outputs the binary input signal X
Input _2/3 and Y ₀ and output the logical product of them.

The AND element 317 outputs the binary input signal X
_2/3 and Y _1/3 are input and the logical product of them is output.

The AND element 318 outputs the binary input signal X
_2/3 and Y _2/3 are input and the logical product of them is output.

The AND element 319 outputs the binary input signal X
_2/3 and Y ₁ are input and the logical product of them is output.

The AND element 320 outputs the binary input signal X
Input ₁ and Y ₀ and output the logical product of them.

The AND element 321 outputs the binary input signal X
Input ₁ and Y _1/3 and output the logical product of them.

The Lee input signals X ₁ and Y _2/3 are input and the logical product of them is output.

The AND element 323 has a binary input signal X.
Input ₁ and Y ₁ and output the logical product of them.

The quantizing element 324 inputs the output of the AND element 308 and outputs a quaternary threshold value.
Inputs the output of the AND element 308 and outputs a four-valued threshold value.

The quantizing element 326 inputs the output of the AND element 309 and outputs a quaternary threshold value.
Inputs the output of the AND element 309 and outputs a four-valued threshold value.

The quantizing element 328 inputs the output of the AND element 310 and outputs a quaternary threshold value.
Inputs the output of the AND element 310 and outputs a four-valued threshold value.

The quantizing element 330 inputs the output of the AND element 311 and outputs a quaternary threshold value.
Inputs the output of the AND element 311 and outputs a four-valued threshold value.

The quantizing element 332 inputs the output of the AND element 312 and outputs a quaternary threshold value.
Inputs the output of the AND element 312 and outputs a four-valued threshold value.

The quantizing element 334 inputs the output of the AND element 313 and outputs a quaternary threshold value.
The input of the AND element 313 outputs a four-valued threshold value, and the quantizing element 336 inputs the output of the AND element 313 and outputs a binary threshold value.

The quantizing element 337 inputs the output of the AND element 314 and outputs a quaternary threshold value.
The input of the output of the AND element 314 outputs a quaternary threshold value, and the quantizing element 339 inputs the output of the AND element 314 and outputs a binary threshold value.

The quantizing element 340 inputs the output of the AND element 315 and outputs a quaternary threshold value.
Is an input of the output of the AND element 315 and outputs a four-valued threshold value. A quantizing element 342 is an input of the output of the AND element 315 and outputs a two-valued threshold value. Is A
The output of the ND element 315 is input and a four-valued threshold value is output.

The quantizing element 344 inputs the output of the AND element 316 and outputs a quaternary threshold value.
Inputs the output of the AND element 316 and outputs a four-valued threshold value.

The quantizing element 346 inputs the output of the AND element 317 and outputs a quaternary threshold value.
Outputs the four-valued threshold value by inputting the output of the AND element 317, and the quantizing element 348 inputs the output of the AND element 317 and outputs the binary threshold value.

The quantizing element 349 inputs the output of the AND element 318 and outputs a quaternary threshold value.
Is the input of the output of the AND element 318 and outputs a four-valued threshold value. The quantizing element 351 is the input of the output of the AND element 318 and outputs a four-valued threshold value. Is A
The output of the ND element 318 is input to output a quaternary threshold value, and the quantizing element 353 inputs the output of the AND element 318 to output a quaternary threshold value.

The quantizing element 354 inputs the output of the AND element 319 and outputs a quaternary threshold value.
The input of the output of the AND element 319 outputs a four-valued threshold value, and the quantizing element 356 inputs the output of the AND element 319 and outputs a four-valued threshold value. Is A
The output of the ND element 319 is input to output a four-valued threshold value, and the quantization element 358 inputs the output of the AND element 319 to output a two-valued threshold value.

The quantizing element 359 inputs the output of the AND element 320 and outputs a quaternary threshold value.
Inputs the output of the AND element 320 and outputs a four-valued threshold value.

The quantizing element 361 inputs the output of the AND element 321 and outputs a quaternary threshold value.
Is an input of the output of the AND element 321 and outputs a four-valued threshold value. A quantizing element 363 is an input of the output of the AND element 321 and outputs a two-valued threshold value. Is A
The output of the ND element 321 is input and a four-valued threshold value is output.

The quantizing element 365 inputs the output of the AND element 322 and outputs a quaternary threshold value.
Input the output of the AND element 322 and output a 4-valued threshold value. The quantizing element 367 inputs the output of the AND element 322 and outputs a 4-valued threshold value. Is A
The output of the ND element 322 is input to output a four-valued threshold value, and the quantizing element 369 inputs the output of the AND element 322 to output a two-valued threshold value.

The quantizing element 370 inputs the output of the AND element 323 and outputs a four-valued threshold value.
Is the input of the output of the AND element 323 and outputs a four-valued threshold value. The quantizing element 372 is the input of the output of the AND element 323 and outputs a four-valued threshold value. Is A
The output of the ND element 323 is input to output a four-valued threshold value, the quantization element 374 is input to the output of the AND element 323 to output a four-valued threshold value, and the quantization element 375 is AND
The output of the element 323 is input and a binary threshold value is output.

The input / output element 376 is a four-value carry input C.
Is input to output a carry input signal C ₀ ,
The 377 inputs the 4-value carry input C and outputs the carry input signal C _1/3 , and the input / output element 378 inputs the 4-value carry input C and outputs the carry input signal C _2/3 . Output.

The AND element 379 is the quantizing elements 349 and 354.
, 365, 370, and carry input signal C ₀ output from input / output element 376, and outputs a logical product of them.

The AND element 380 is the quantizing elements 340 and 350.
, 355, 361, 366, 371, and carry input signal C output from input / output element 377.
Input _1/3 and output the logical product of them.

The AND element 381 is the quantizing element 337, 341.
, 346, 351, 356, 362, 367, 372, the carry input signal C _2/3 output from the input / output element 378, and a logical product of them.

The OR element 385 is the AND element 379, 380,
It inputs the output of 381 and outputs a carry output signal (C ') which is the logical sum of them.

The 1-bit delay circuit 393 inputs the carry output signal (C ') output from the OR element 385 and outputs the carry output C'.

The input / output element 394 is a 1-bit delay circuit 393.
'Enter the carry output C' has been a carry output C output from the outputs _2, input-output device 395, a 1-bit delay circuit 393 'to input the carry output C' has been a carry output C output from the ₁ Output.

The AND element 382 is the quantizing elements 334 and 338.
, 342, 347, 357, 363, 368, 373, and the carry input signal C ₀ output from the input / output element 376, and outputs a logical product of them.

The AND element 383 is the quantizing elements 324 and 326.
, 328, 330, 332, 335, 339, 344, 348, 352
, 358, 359, 369, 374, and carry input signal C output from the input / output element 377.
Input _1/3 and output the logical product of them.

The AND element 384 is the quantizing elements 325 and 327.
, 329, 331, 333, 336, 343, 345, 353, 360
, 364, 375, the carry input signal C _2/3 output from the input / output element 378, and a logical product of them.

The OR element 386 is composed of AND elements 382, 383,
Multiply output Z which is the logical sum of the outputs of 384
Is output.

The input / output element 387 inputs the multiplication output Z and outputs the multiplication output Z _2/3 to the OR element 391.
9 inputs the multiplication output Z and outputs the multiplication output Z ₁ to the OR element 39.
The input / output element 390 inputs the multiplication output Z and outputs the multiplication output Z _1/3 to the OR element 392.

The input X of FIG. 10 is obtained by the binary input circuit of FIG.

The binary input circuit shown in FIG. 11 includes NOT circuit elements (NOT elements) 396 and 397 and AND elements 398 to 400.
, AND elements 401, 402, and OR element 403.

Next, the operation of the binary input circuit shown in FIG. 11 will be described.

The NOT element 396 inputs and outputs a 2-bit parallel binary input signal X ₂ , and outputs the NOT element 397.
Inputs and outputs a 2-bit parallel binary input signal X ₁ .

The AND element 398 inputs the output of the NOT element 396 and the binary input signal X ₁ and outputs a logical product of them, and the AND element 401 outputs the AND element.
The AND element 399 inputs the output of 398 and 1/3 to output the logical product of them, and the AND element 399 inputs the output of the NOT element 397 and the binary input signal X ₂ to calculate the logical product of them. Then, the AND element 402 inputs the output of the AND element 399 and 2/3 and outputs the logical product of them.

The OR element 403 inputs the output of the AND element 401, the output of the AND element 402 and the output of the AND element 400, and outputs a 4-valued output signal X which is the logical sum of them.

The input Y of FIG. 10 is obtained by the binary input circuit of FIG.

The binary input circuit of FIG. 12 is similar to the binary input circuit of FIG. 11 in that NOT elements 404, 405,
It is composed of AND elements 406 to 408, AND elements 409 and 410, and an OR element 411.

Next, the operation of the binary input circuit shown in FIG. 12 will be described.

The NOT element 404 inputs and outputs the 2-bit parallel binary input signal Y ₂ , and outputs the NOT element 405.
Inputs and outputs a 2-bit parallel binary input signal Y ₁ .

The AND element 406 inputs the output of the NOT element 404 and the binary input signal Y ₁ and outputs a logical product of them.
An AND element 407 inputs the output of 406 and 1/3 and outputs a logical product of them, and an AND element 407 inputs an output of the NOT element 405 and a binary input signal Y ₂ and calculates a logical product of them. Then, the AND element 410 inputs the output of the AND element 407 and 2/3 and outputs the logical product of them.

The OR element 411 inputs the output of the AND element 409, the output of the AND element 410, and the output of the AND element 408, and outputs a 4-valued output signal Y which is the logical sum of them.

Further, the input C of FIG. 10 is obtained by the binary input circuit of FIG.

The binary input circuit of FIG. 13 includes NOT elements 412 and 413, AND elements 414 and 415, and an AND element 416.
, 417, and an OR element 418.

Next, the operation of the binary input circuit of FIG. 13 will be described.

The NOT element 412 inputs and outputs the 2-bit parallel binary input signal C ₂ , and outputs the NOT element 413.
Inputs and outputs a 2-bit parallel binary input signal C ₁ .

The AND element 414 inputs the output of the NOT element 412 and the binary input signal C ₁ and outputs a logical product of them, and the AND element 416 outputs the AND element.
The AND element 415 inputs the output of 414 and 1/3 and outputs a logical product of them, and the AND element 415 inputs the output of the NOT element 413 and a binary input signal C ₂ and calculates a logical product of them. Then, the AND element 417 inputs the output of the AND element 415 and 2/3 and outputs the logical product of them.

The OR element 418 inputs the output of the AND element 416 and the output of the AND element 417 and outputs a 4-valued output signal C which is the logical sum of them.

Table 8 shows the code assignments of 2-bit parallel binary input signals X ₂ , X ₁ , Y ₂ , Y ₁ and quaternary output signals X, Y and carry inputs C ₂ , C ₁ , C respectively. Show.

[0192]

[Table 8]

Expressions (4), (5) and (6) are logical expressions corresponding to Table 8.

[0194]

[Equation 4]

[0195]

[Equation 5]

[0196]

[Equation 6]

Table 9 shows the logic of the quaternary multiplier, Table 10
Indicate carry outputs, respectively.

[0198]

[Table 9]

[0199]

[Table 10]

The symbols attached to the quantizing elements in FIG. 10 indicate physical functions as shown in Table 11, but various logical elements can be used as these quantizing elements.

[0201]

[Table 11]

These logic elements are, in addition to the binary input circuits shown in FIGS. 11, 12 and 13, four-valued logic circuits (equivalent circuit, OR circuit, which compose the four-valued multiplier of FIG. 10).
AND circuit).

Table 12 shows not only the four-valued multiplication output <Z> and the two-valued multiplication output <Z ₂ , Z ₁ >, but also the relation between the codes.

[0204]

[Table 12]

Although x ₀ and x _{1 in} FIG. 6 are shown by an equal value circuit, since they are binary signals in this case, they may be output signals of x and x bars. The same applies to y ₀ and y ₁ in FIG.

In Table 9, the blank part is "0", but "1" is 1/3, "2" is 2/3, and "3" is 1 and the four-value multiplier of FIG. It is configured.

Table 10 shows the carry output, but the blank part is "0", "1" is 1/3 and "2" is 2/3, and the four-value multiplier shown in FIG. 10 is constructed. ing.

FIG. 14 is a permutation circuit which is composed of a 1-bit delay circuit 393 and input / output elements 394 and 395 shown in the four-valued multiplier of FIG. 10, and which outputs carry outputs C ₂ ′ and C ₁ ′. It is shown that (Fig. 14 (a)) can be replaced with a replacement circuit (Fig. 14 (b)) indicated by a mark.

In the replacement circuit of FIG. 14B, the carry output (C ′) is input and the carry output C _2/3 ′ is output, and the carry output C ₂ output from the input / output element 419. _{/ 3} delay circuit 420 'inputted by one-bit delay carry output C ₂ a' and outputs a carry output (C ')
Input / output device which inputs carry and outputs carry output C _1/3 ′
421, carry output C output from the input / output element 421
Carry output C ₁ ′ by inputting _1/3 ′ and delaying it by 1 bit
Is formed by a delay circuit 422 that outputs Since most parts can be described in the same manner as the ternary multiplier, detailed description will be omitted.

FIGS. 15, 16 and 17 show the case where a binary input and a binary output are used.
The output signals X ₀ , X _1/3 , X _2/3 and X ₁ of FIG.
Input signals X ₀ , X _1/3 , X of the four-valued multiplier of
It can be used as _2/3 , X ₁ . In addition, the output signals Y ₀ , Y _1/3 , Y _2/3 , and Y ₁ of FIG. 16 and C ₀ and C of FIG.
_The same applies to _1/3 and C _2/3 . Note that the binary signal and the quaternary signal are not used at the same time, but they can be used in combination.

FIG. 18 shows a multi-value converter 601, a binary converter 60.
2, a configuration example of an arithmetic unit including a multilevel signal input unit 603, a multilevel arithmetic unit 604, and a multilevel signal output unit 605 will be shown.
When using only three-valued input signals, the multi-valued signal input section 60
It suffices to input a ternary signal from 3 and the ternary multiplier shown in FIG. 1 or FIG.
Further, when using only the four-valued input signal, it is sufficient to input the four-valued signal from the multi-valued signal input unit 603, and the four-valued multiplier shown in FIG. 10 can be used for the multi-valued operation unit 604.

In addition to the usage described here, if the input signal and the output signal are combined with the binary signal and the multi-valued signal, they can be used in various combinations as shown in FIG.

According to the above-mentioned embodiment, the multiplication speed can be doubled, and even if the clock frequency is halved, the multiplication speed does not change. This is the same as the reduction in power consumption. The fact that the circuit scale does not become large means that it is possible to reduce the number of logic elements (or circuit elements) that form the multiplier, which enables lower power consumption.

Further, in order to increase the amount of bit signal processing that can be executed at the same time, the signal is multi-valued so that a multi-valued functional element is used in the circuit that constitutes the multiplier, and high-speed operation is possible without increasing the hardware scale. Is possible.

Further, the multi-valued multiplier of the present invention can also be used for multiplication included in a multiplication circuit, a division circuit, a square root arithmetic circuit, etc. already applied for by the present inventor.

Next, a squaring circuit for executing a squaring operation, that is, one of multiplications according to the fourth embodiment of the present invention will be described. The squaring circuit corresponds to the above-mentioned ternary multiplier when X = Y and x = y or the above-mentioned quaternary multiplier when X = Y. That is, this squaring circuit inputs only the signals indicated by X and x in the ternary multiplier and only the signal indicated by X in the quaternary multiplier. This square circuit is a circuit that functions independently.

FIG. 19 shows the logic of squared <Z>, and FIG. 20 shows the logic of carry <C '>. Figure 2
Reference numeral 1 denotes a four-valued squaring circuit which operates with a synthesized logic as shown in FIGS. 19 and 20.

The four-valued squaring circuit shown in FIG. 21 includes input / output elements 2101-2104, 2121-2123 and 2133-2137.
And multi-valued functional elements 2105 to 2120 and an AND circuit element (AN
D element) 2124 to 2129 and OR circuit element (OR element) 213
0, 2131, a 1-bit delay circuit 2132, and OR circuit elements (OR elements) 2138, 2139.

Next, each of those components will be described.

The input / output element 2101 inputs a four-valued signal X and outputs a binary signal X ₀ . The input / output element 2102 is
The four-valued signal X is input and the binary signal X _1/3 is output. The input / output element 2103 inputs a four-valued signal X and outputs a binary signal X _2/3 . The input / output element 2104 inputs the four-valued signal X and outputs the binary signal X ₁ .

The multi-level function element 2105 inputs the signal of “1/3” value and the binary signal X ₀ from the input / output element 2101 and outputs a binary threshold value. Multi-level functional element 2106
Inputs a "2/3" value signal and the binary signal X ₀ from the input / output element 2101 and outputs a binary threshold value.

The multi-level function element 2107 inputs a signal of “1/3” value and the binary signal X _1/3 from the input / output element 2102 and outputs a binary threshold value. Multi-level functional element 2108
Inputs a signal of "2/3" value and the binary signal X _1/3 output from the input / output element 2102 and outputs a binary threshold value. The multi-valued functional element 2109 inputs the binary output signal X _1/3 output from the input / output element 2102 and outputs a binary threshold value.

The multi-level function element 2110 outputs a signal of “1/3” value and the binary signal X _2/3 output from the input / output element 2103.
To output a binary threshold. The multi-level function element 2111 inputs the signal of “1/3” value and the binary signal X _2/3 output from the input / output element 2103 and outputs a binary threshold value. Multi-valued functional element 2112 is "1/3"
The value signal and the binary signal X _2/3 output from the input / output element 2103 are input and a binary threshold value is output.
The multi-level function element 2113 is a "1/3" value signal and input / output element.
The binary signal X _2/3 output from 2103 is input and a binary threshold value is output. The multi-level functional element 2114 is
The signal of "2/3" value and the binary signal X _2/3 output from the input / output element 2103 are input and a binary threshold value is output.

The multi-level function element 2115 outputs a signal of “2/3” value and the binary output signal X output from the input / output element 2104.
Input ₁ and to output the binary threshold. The multi-valued functional element 2116 inputs the “2/3” value signal and the binary signal X ₁ output from the input / output element 2104 and outputs a binary threshold value. The multi-valued functional element 2117 has “2 /
The signal of "3" value and the binary signal X ₁ output from the input / output element 2104 are input and a binary threshold value is output. The multi-valued functional element 2118 inputs the “1/3” value signal and the binary signal X ₁ output from the input / output element 2104 and outputs a binary threshold value. Multi-level functional element 2119
Inputs a signal of "2/3" value and the binary signal X ₁ output from the input / output element 2104 and outputs a binary threshold value. The multi-level function element 2120 inputs the binary signal X ₁ output from the input / output element 2104 and outputs a binary threshold value.

The input / output element 2121 is a four-value carry input C.
And carry signal C ₀ is output. I / O element 212
2 is a carry signal C by inputting a four-value carry input C.
Output _1/3 . The input / output element 2123 inputs the 4-value carry input C and outputs the carry signal C _2/3 .

The AND element 2124 is a multi-valued functional element 2110, 21.
Any one of the outputs from 15 and the carry signal C ₀ from the input / output element 2121 are input and the logical product (AND) of these two signals is output.

The AND element 2125 is a multi-valued functional element 2111, 21.
Any one of the outputs from 16 and the carry signal C _1/3 from the input / output element 2122 are input and the logical product (AND) of these two signals is output.

The AND element 2126 is a multi-valued functional element 2112, 21.
Any one of the outputs from 17 and the carry signal C _2/3 from the input / output element 2123 are input and the logical product (AND) of these two signals is output.

The OR element 2130 inputs the outputs from the AND elements 2124, 2125 and 2126 and outputs a carry signal (C ') corresponding to the logical sum (OR) of these signals.
The 1-bit delay circuit 2132 inputs the carry signal (C ′) from the OR element 2130, delays it by 1 bit, and outputs another carry signal C ′.

The input / output element 2133 is a 1-bit delay circuit 2132.
'Enter the carry signal C' carry signal C from ₂
Is output. I / O element 2134 is also a 1-bit delay circuit
'Enter the carry output C' carry signal C from 2132 outputs _1.

The AND element 2127 is a multi-valued functional element 2107, 21.
Any one of the outputs from 18 and the carry signal C ₀ from the input / output element 2121 are input and the logical product of these two signals is output.

The AND element 2128 is a multi-valued functional element 2105, 21.
One of the outputs from 08, 2113, and 2119 and an input / output element
The carry signal C _1/3 from 2122 is input and the logical product (AND) of these two signals is output.

The AND element 2129 is a multi-valued functional element 2106, 21.
Any one of the outputs from 09, 2114, 2120 and input / output element
The carry signal C _2/3 from 2123 is input and the logical product (AND) of these two signals is output.

The OR element 2131 is composed of AND elements 2127, 2128,
And 2129 are input and the multiplication output Z corresponding to the logical sum (OR) of those signals is input / output elements 2135 to 2137.
Output to each.

The input / output element 2135 inputs the multiplication output Z from the OR element 2131 and outputs a new multiplication output Z _2/3 to the OR element 213.
Output to 8. The input / output element 2136 inputs the multiplication output Z from the OR element 2131 and outputs a new multiplication output Z ₁ to the OR element 213.
Output to 8 and 2139 respectively. Input / output element 2137 is OR
The multiplication output Z _1/3 from the element 2131 is input and a new multiplication output Z _1/3 is output to the OR element 2139.

The OR element 2138 outputs a multiplication output Z ₂ corresponding to the logical sum (OR) of the output from the input / output element 2135 and the output from the input / output element 2136. The OR element 2139 outputs a multiplication output Z ₁ corresponding to the logical sum of the output from the input / output element 2136 and the output from the input / output element 2137.

The four-valued squaring circuit shown in FIG. 21 is composed of a multi-valued functional element or a quantizing element similarly to the above-mentioned four-valued squaring circuit.

FIG. 22 shows another embodiment of a four-value square circuit composed of a four-value OR circuit. This four-valued squaring circuit has the same squaring function as that shown in FIG. 21, but has a different configuration.

The four-valued square circuit shown in FIG. 22 includes input / output elements 2201 to 2207 and AND circuit elements (AND elements).
2208 to 2219, multi-level functional elements 2220 to 2235, 1-bit delay circuit 2236, input / output elements 2237 to 2241, and OR circuit elements (OR elements) 2242 and 2243.

Next, each of those constituent parts will be described.

The input / output element 2201 inputs a 4-valued signal X and outputs a binary signal X ₀ . The input / output lion 2202 is
The four-valued signal X is input and the binary signal X _1/3 is output. The input / output element 2203 inputs a four-valued signal X and outputs a binary signal X _2/3 . The input / output element 2204 inputs a four-valued signal X and outputs a binary signal X ₁ .

Input / output element 2205 inputs quaternary signal C and outputs carry signal C ₀ . Input / output element 2206 is 4
The value signal C is input and the carry signal C _1/3 is output.
The input / output element 2207 inputs the four-valued signal C and outputs the carry signal C _2/3 .

The AND element 2208 outputs the binary signal X ₀ ,
C ₀ is input and the logical product (AND) of these two signals is output. The AND element 2209 outputs the binary signals X ₀ and C.
Input _1/3 and output the logical product of these two signals.

The AND element 2210 outputs the binary signal X ₀ ,
Input C _2/3 and AND of these two signals
Is output. The AND element 2211 inputs the binary signals X _1/3 and C ₀ and outputs a logical product of these two signals.

The AND element 2212 inputs the binary signals X _1/3 and C _1/3 and the logical product (A
ND) is output. The AND element 2213 inputs the binary signals X _1/3 and C _2/3 and outputs a logical product of these two signals.

The AND element 2214 inputs the binary signals X _2/3 and C ₀ and inputs the logical product (AN) of these two signals.
D) is output. The AND element 2215 outputs the binary signal X.
_2/3 and C _1/3 are input and the logical product of these two signals is output.

The AND element 2216 inputs the binary signals X _2/3 and C _2/3 and inputs the logical product (A
ND) is output. The AND element 2217 inputs the binary signals X ₁ and C ₀ and outputs a logical product of these two signals.

The AND element 2218 outputs the binary signal X ₁ ,
Input C _1/3 and AND the two signals
Is output. The AND element 2219 outputs the binary signal X ₁ ,
C _2/3 is input and the logical product of these two signals is output.

The multi-valued functional element 2220 inputs the signal of “1/3” value and the output from the AND element 2209 and outputs a binary threshold value. The multi-valued functional element 2221 inputs the signal of “2/3” value and the output from the AND element 2210 and outputs a binary threshold value.

The multi-valued functional element 2222 inputs a signal of "1/3" value and the output from the AND element 2211 and outputs a binary threshold value. The multi-valued functional element 2223 inputs the signal of “2/3” value and the output from the AND element 2212 and outputs a binary threshold value.

The multi-level function element 2224 inputs the output from the AND element 2213 and outputs a binary threshold value. The multi-valued functional element 2225 is provided with an AND element 2214 and a signal of “1/3” value
Input the output from and output the binary threshold.

The multi-level function element 2226 inputs the signal of “1/3” value and the output from the AND element 2215 and outputs a binary threshold value. The multi-valued functional element 2227 inputs the signal of “1/3” value and the output from the AND element 2215 and outputs a binary threshold value.

The multi-level function element 2228 inputs the signal of “1/3” value and the output from the AND element 2216 and outputs a binary threshold value. The multi-valued functional element 2229 inputs the “2/3” value signal and the output from the AND element 2216 and outputs a binary threshold value.

The multi-level function element 2230 inputs the signal of “2/3” value and the output from the AND element 2217 and outputs a binary threshold value. The multi-level function element 2231 inputs the signal of “1/3” value and the output from the AND element 2217 and outputs a binary threshold value.

The multi-level function element 2232 inputs the signal of “2/3” value and the output from the AND element 2218 and outputs a binary threshold value. The multi-valued functional element 2233 inputs the signal of “2/3” value and the output from the AND element 2218 and outputs a binary threshold value.

The multi-level function element 2234 inputs the signal of “2/3” value and the output from the AND element 2219 and outputs a binary threshold value. The multi-level function element 2235 is an AND element 22
Input the output from 19 and output the binary threshold.

The 1-bit delay circuit 2236 includes a multi-level functional element 22.
The carry signal (C ') from any one of 25, 2226, 2228, 2230, 2232 and 2234 is input and another carry signal C'is output to the input / output elements 2237 and 2238, respectively.

The input / output element 2237 is a 1-bit delay circuit 2236.
'Enter the carry signal C' carry signal C outputted from the output _2. Similarly, the input / output element 2238 inputs the carry signal C ′ output from the 1-bit delay circuit 2236 and outputs the carry output C ′ ₁ .

The input / output element 2239 is a multi-level functional element 2220, 22.
21, 2222, 2223, 2224, 2227, 2229, 2231, 2233, 2235
And outputs a new multiplication value Z _2/3 to the OR element 2242.

The input / output element 2240 is a multi-valued functional element 2220, 22.
21, 2222, 2223, 2224, 2227, 2229, 2231, 2233, 2235
The multiplication value Z output from any one of them is input and a new multiplication value Z ₁ is output to the OR elements 2242 and 2243.

The input / output element 2241 is a multi-level functional element 2220, 22.
21, 2222, 2223, 2224, 2227, 2229, 2231, 2233, 2235
And outputs a new multiplication value Z _1/3 to the OR element 2243.

The OR element 2242 outputs a multiplication output Z ₂ corresponding to the logical sum (OR) of the output from the input / output element 2239 and the output from the input / output element 2240. The OR element 2243 outputs a multiplication output Z ₁ corresponding to the logical sum (OR) of the output from the input / output element 2240 and the output from the input / output element 2241.

FIG. 23 is a four-valued circuit having a binary OR circuit in which the squaring circuit corresponds to the squaring circuit shown in FIG. 21 and operates independently (details are different). The squaring circuit is shown.

The four-valued square circuit shown in FIG. 23 includes input / output elements 2301 to 2304, multi-valued functional elements 2305 to 2318, input / output elements 2319 to 2321, and an AND circuit element (AND element).
2322 to 2324, OR circuit element (OR element) 2325, 1-bit delay circuit 2326, AND elements 2327 to 2329, OR element 2330, 1-bit delay circuit 2331, and AND element 2332
And an OR element 2333, AND elements 2334 to 2336, and an OR element 2337.

Next, each of those components will be described.

The input / output element 2301 inputs a four-valued signal X and outputs a binary signal X ₀ . The input / output element 2302 is
The four-valued signal X is input and the binary signal X _1/3 is output. The input / output element 2303 inputs a four-valued signal X and outputs a binary signal X _2/3 . The input / output element 2304 inputs the four-valued signal X and outputs the binary signal X ₁ .

The multi-level function element 2305 inputs the binary signal X ₀ output from the input / output element 2301 and outputs a binary threshold value.

The multi-level function element 2306 inputs the binary signal X _1/3 output from the input / output element 2302 and outputs a binary threshold value. The multi-level function element 2307 is an input / output element.
The binary signal X _1/3 output from 2302 is input and a binary threshold value is output. The multi-level functional element 2308 inputs the binary signal X _1/3 output from the input / output element 2302 and outputs a binary threshold value.

The multi-level functional element 2309 inputs the binary signal X _2/3 output from the input / output element 2303 and outputs a binary threshold value. The multi-level function element 2310 is an input / output element.
The binary signal X _2/3 output from 2303 is input and a binary threshold value is output. The multi-level functional element 2311 inputs the binary signal X _2/3 output from the input / output element 2303 and outputs a binary threshold value. Multi-level functional element 23
12 is a binary signal X output from the input / output element 2303
Input _2/3 and output the binary threshold.

The multi-level function element 2313 inputs the binary signal X ₁ output from the input / output element 2304 and outputs a binary threshold value. The multi-level functional element 2314 is the input / output element 23.
The binary signal X ₁ output from 04 is input and the binary threshold value is output. The multi-level functional element 2315 inputs the binary signal X ₁ output from the input / output element 2304 and outputs a binary threshold value. The multi-level functional element 2316 is
The binary signal X ₁ output from the input / output element 2304 is input and a binary threshold value is output. Multi-level functional element 23
17 is a binary signal X output from the input / output element 2304
Input ₁ to output the binary threshold. The multi-level functional element 2318 inputs the binary signal X ₁ output from the input / output element 2304 and outputs a binary threshold value.

Input / output element 2319 inputs quaternary signal C and outputs carry signal C ₀ . Input / output element 2320 is 4
The value signal C is input and the carry signal C _1/3 is output.
The input / output element 2321 inputs a four-valued signal C and outputs a carry signal C _2/3 .

The AND element 2322 inputs the outputs from the multi-level function element 2313 and the input / output element 2319 and outputs the logical product of these two signals to the OR element 2325. AND element 23
Reference numeral 23 denotes an OR element 2325 which inputs the outputs from the multi-valued functional element 2314 and the input / output element 2320 and calculates the logical product of these two signals.
Output to. The AND element 2324 inputs the outputs from the multi-level function element 2315 and the input / output element 2321 and outputs the logical product of these two signals to the OR element 2325.

The OR element 2325 is the AND element 2322, 2323,
The three signals output from the 2324 are input and the logical sum of these three signals is output to the 1-bit delay circuit 2326.

[0274] 1-bit delay circuit 2326 outputs a carry signal C _'2 inputs an output signal from the OR element 2325.

The AND element 2327 inputs the outputs from the multi-valued functional element 2309 and the input / output element 2319 and outputs the logical product of these two signals to the OR element 2330. AND element 2328
Inputs the outputs from the multi-level function element 2310 and the input / output element 2320 and outputs the logical product of these two signals to the OR element 2330. The AND element 2329 inputs the outputs from the multi-valued functional element 2311 and the input / output element 2321 and outputs the logical product of these two signals to the OR element 2330.

The OR element 2330 is composed of AND elements 2327, 2328,
The three output signals from the 2329 are input and the logical sum of these three signals is output to the 1-bit delay circuit 2331.

[0277] 1-bit delay circuit 2331 outputs a carry signal C _'1 by inputting the signal output from the OR element 2330.

The AND element 2332 is a multi-valued functional element 2306, 23.
The output from any one of 16 and the output from the input / output element 2320 is input and the logical product of these two signals is ORed
Output to 33.

The OR element 2333 inputs the output signal from the AND element 2332 and the output from the input / output element 2321 and outputs a multiplication signal Z ₂ as the logical sum of these two signals.

The AND element 2334 is a multi-valued functional element 2307, 23.
The output from any one of 17 and the output from the input / output element 2319 are input, and the logical product of these two signals is ORed.
Output to 37. The AND element 2335 is a multi-valued functional element 2305,
The output from any one of 2312 and the output from the input / output element 2320 are input, and the logical product of these two signals is ORed.
Output to 2337. The AND element 2336 is a multi-valued functional element 230.
The output from any one of 8 and 2318 and the output from the input / output element 2321 are input, and the logical product of these two signals is ORed.
Output to element 2337.

The OR element 2337 is the AND element 2334, 2335,
The three output signals from 2336 are input, and the multiplication signal Z ₁ is output as the logical sum of these three signals.

FIG. 24 shows the logic of squared <Z ', Z>, and FIG. 25 shows the logic of carry <C'>.

FIG. 26 shows a ternary square circuit having the synthesized logic shown in FIGS. 24 and 25. Similar to the above-mentioned three-value multiplier, the three-value square circuit shown in FIG. 26 has a three-value OR circuit composed of multi-valued functional elements or quantization elements.

The ternary square circuit shown in FIG. 26 includes input / output elements 2601-2605 and AND circuit elements (AND elements).
2606, 2607, multi-valued functional elements 2608 to 2623, input / output elements
2624 to 2626, AND elements 2627 to 2632, OR circuit elements (OR elements) 2633 and 2634, and a 1-bit delay circuit 2635,
Input / output elements 2638 and 2639, AND element 2640, OR element
It is composed of 2641 and 2642.

Next, each of those components will be described.

The input / output element 2601 inputs a ternary signal X and outputs a binary signal X ₀ . The input / output element 2602 is
The ternary signal X is input and the binary signal X _1/2 is output. The input / output element 2603 inputs a ternary signal X and outputs a binary signal X ₁ .

The input / output element 2604 inputs the binary signal x and outputs the binary signal x ₀ . I / O element 2605
Inputs a binary signal x and outputs a binary signal x ₁ .

The AND element 2606 outputs the binary signal X ₀ ,
x ₀ is input, and the logical product (AN
D) is output.

The AND element 2607 outputs the binary signal X ₀ ,
x ₁ is input and the logical product of those binary signals is output.

Multi-valued functional element 2608 inputs the signal of “½” value and the output from AND element 2606 and outputs a three-valued threshold value. The multi-valued functional element 2609 inputs the output from the AND element 2606 and outputs a binary threshold value.

The multi-valued functional element 2610 has a “1/2” value signal and the binary signal X _1/2 output from the input / output element 2602.
Input and to output a ternary threshold value. Multi-level functional element
2611 inputs the binary signal X _1/2 output from the input / output element 2602 and outputs a binary threshold value. The multi-level function element 2612 inputs the binary signal X _1/2 output from the input / output element 2602 and outputs a binary threshold value.

The multi-valued functional element 2613 inputs the signal of “½” value and the binary signal X ₁ output from the input / output element 2603 and outputs a ternary threshold value. Multi-level functional element 26
Reference numeral 14 inputs a "1/2" value signal and the binary signal X ₁ output from the input / output element 2603 and outputs a ternary threshold value. The multi-valued functional element 2615 inputs the signal of “½” value and the binary signal X ₁ output from the input / output element 2603 and outputs a three-valued threshold value. Multi-level functional element 2616
Inputs a "1/2" value signal and the binary signal X ₁ output from the input / output element 2603 and outputs a ternary threshold value. The multi-level functional element 2617 inputs the binary signal X ₁ output from the input / output element 2603 and outputs a binary threshold value.

The multi-level function element 2618 inputs the signal output from the AND element 2607 and outputs a binary threshold value. The multi-valued functional element 2619 inputs the signal output from the AND element 2607 and outputs a binary threshold value. The multi-level function element 2620 inputs the signal output from the AND element 2607 and outputs a binary threshold value.

Multi-valued functional element 2621 inputs the signal of “½” value and the signal output from AND element 2607 and outputs a three-valued threshold value. The multi-valued functional element 2622 inputs the output signal from the AND element 2607 and outputs a binary threshold value. The multi-valued functional element 2623 inputs the output signal from the AND element 2607 and outputs a binary threshold value.

The input / output element 2624 is a ternary carry input C.
And carry signal C ₀ is output. I / O element 262
5 is a carry signal C by inputting a ternary carry input C.
Outputs _1/2 . Input / output element 2626 inputs ternary carry input C and outputs carry signal C ₁ .

The AND element 2627 is a multi-valued functional element 2613, 26.
Any one of the outputs from 18 and the carry signal C ₀ from the input / output element 2624 are input and the logical product (AND) of these two signals is output.

The AND element 2628 is a multi-valued functional element 2614, 26.
Any one of the outputs from 19 and the carry signal C _1/2 from the input / output element 2625 are input, and the logical product (AND) of these two signals is output.

The AND element 2629 is a multi-valued functional element 2615, 26.
Any one of the outputs from 20 and the carry signal C ₁ from the input / output element 2626 are input and the logical product (AND) of these two signals is output.

The OR element 2633 inputs the outputs from the AND elements 2627, 2628 and 2629 and outputs a carry signal (C ') corresponding to the logical sum (OR) of these signals.
The 1-bit delay circuit 2635 receives the carry signal (C ′) from the OR element 2633, delays it by 1 bit, and outputs another carry signal C ′.

Input / output element 2636 inputs carry signal C ′ output from the 1-bit delay circuit and outputs carry signal C ′ ₂ . Output device 2637 similarly 'Enter the carry output C' carry signal C from 1-bit delay circuit outputs a _1.

The AND element 2630 is a multi-valued functional element 2610, 26.
Any one of the outputs from 21 and the carry signal C ₀ from the input / output element 2624 are input, and the logical product (AND) of these two signals is output.

The AND element 2631 is a multi-valued functional element 2608, 26.
Any one of the outputs from 11, 2616, 2622 and input / output element
The carry signal C _1/2 from the 2625 is input and the logical product (AND) of these two signals is output.

The AND element 2632 is a multi-valued functional element 2609, 26.
Any one of the outputs from 17 and the carry signal C ₁ from the input / output element 2626 are input and the logical product (AND) of these two signals is output.

The OR element 2634 inputs the outputs from the AND elements 2630, 2631 and 2632 and outputs a multiplication signal Z corresponding to the logical sum (OR) of those signals.

The input / output element 2638 inputs the multiplication output Z and outputs a new multiplication output Z ₁ to the OR element 2641. The input / output element 2639 inputs the multiplication output Z and outputs a new multiplication output Z.
_1/2 is output to the OR element 2642.

The AND element 2640 is a multi-valued functional element 2612, 26.
One of the outputs from 23 and the carry signal C ₁ output from the input / output element 2626 are input, and a new multiplication signal Z ′ as the logical product of these two signals is input to the OR elements 2641, 26.
Output to 42 respectively.

The OR element 2641 is the input / output element 2638 and A
The outputs from the ND element 2640 are input and the multiplication output Z ₂ corresponding to the logical sum (OR) of those outputs is output.

The OR element 2642 is the input / output element 2639 and A
The outputs from the ND element 2640 are input and the multiplication output Z ₁ corresponding to the logical sum (OR) of those outputs is output.

Similar to the above-mentioned multiplier, each square circuit shown in FIG. 21, FIG. 22 or FIG. 26 can form an arithmetic unit having a binary / multivalue conversion unit.

[0310]

According to the multi-valued multiplier of the present invention, a logic circuit means for receiving a plurality of signals and outputting a predetermined logic result, and a predetermined multi-valued logic circuit connected to the logic circuit means are provided. Since the multi-valued circuit means for outputting a signal is provided, a high multiplication speed can be achieved without increasing the circuit scale of the multiplier and a substantial multiplication can be achieved even if the amount of signals that can be executed simultaneously is increased. It is possible to reduce the number of circuit elements used for, and as a result, it is possible to reduce power consumption. Furthermore, since the number of signals can be reduced, the number of wirings in the LSI is small, so high integration is possible, and multilevel signals such as binary signals, ternary signals, and quaternary signals can be shared.

[Brief description of drawings]

FIG. 1a is a circuit diagram which constitutes a part of FIG. 1 and shows a partial configuration of a ternary multiplier which is a first embodiment of a multivalued multiplier of the present invention.

FIG. 1b is a circuit diagram showing a configuration of another part of the ternary multiplier which is a part of FIG. 1 and is the first embodiment of the multilevel multiplier of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a ternary binary-input / output circuit applicable to the ternary multiplier of FIG.

FIG. 3 is a circuit diagram showing a configuration example of a ternary binary-input / output circuit applicable to the ternary multiplier of FIG.

FIG. 4 is a circuit diagram showing a configuration example of a ternary binary-input / output circuit applicable to the ternary multiplier of FIG.

5 is a circuit diagram showing a configuration of a replacement circuit of FIG.

FIG. 6 is a circuit diagram showing a configuration of a ternary multiplier that is a second embodiment of the multivalued multiplier of the present invention.

7 is a circuit diagram showing a configuration example of a binary binary-input / output circuit applicable to the ternary multiplier of FIG. 1 or FIG.

8 is a circuit diagram showing a configuration example of a binary binary input / output circuit applicable to the ternary multiplier of FIG. 1 or FIG.

9 is a circuit diagram showing a configuration example of a binary binary input / output circuit applicable to the ternary multiplier of FIG. 1 or FIG.

FIG. 10a is a circuit diagram which constitutes a part of FIG. 10 and shows a part of the configuration of a four-valued multiplier which is a third embodiment of the multi-valued multiplier of the present invention.

10B is a circuit diagram showing a part of FIG. 10 and showing another part of the configuration of the four-valued multiplier which is the third embodiment of the multivalued multiplier of the present invention. FIG.

11 is a circuit diagram showing a configuration example of a 4-value binary-input / output circuit applicable to the 4-value multiplier shown in FIG.

12 is a circuit diagram showing a configuration example of a 4-value binary-input / output circuit applicable to the 4-value multiplier shown in FIG.

13 is a circuit diagram showing a configuration example of a 4-value binary-input / output circuit applicable to the 4-value multiplier shown in FIG.

14 is a circuit diagram showing a configuration of a replacement circuit of FIG.

15 is a circuit diagram showing another example of the configuration of a binary binary-input / output circuit applicable to the 4-value multiplier shown in FIG.

16 is a circuit diagram showing another configuration example of a binary binary-input / output circuit applicable to the four-valued multiplier of FIG.

17 is a circuit diagram showing another configuration example of a binary binary-input / output circuit applicable to the four-valued multiplier of FIG.

FIG. 18 is a circuit diagram showing a configuration example of an arithmetic unit using the multilevel multiplier of the present invention.

FIG. 19 is a chart showing a squared <Z> logic executed by a squared circuit according to a fourth example of the present invention.

FIG. 20 is a chart showing the logic of carry <C ′> in the squaring circuit.

21 is a circuit diagram of a four-value square circuit configured by combining the logics shown in FIGS. 19 and 20. FIG.

FIG. 22 is a circuit diagram showing another configuration of a four-value square circuit.

FIG. 23 is a binary O composed of a binary functional element.
It is a circuit diagram which shows the structure of the four-value square circuit which has R circuit.

FIG. 24 is a table showing the logic of squared <Z ′, Z> used in the three-valued square circuit according to the fifth example of the present invention.

FIG. 25 is a chart showing a logic of a carry <C ′> in a three-value square circuit.

26 is a circuit diagram of a ternary square circuit configured by combining the logics shown in FIGS. 24 and 25. FIG.

[Explanation of symbols]

 11-26 AND circuit element 27-78 Multi-level functional element 79-84 AND circuit element 85, 86 OR circuit element 87-89 AND circuit element 90-92 OR circuit element 93 1-bit delay circuit 94-110 Input / output element (etc. Value circuit)

Claims (1)

[Claims] 1. A logic circuit means for inputting a plurality of signals and outputting a predetermined logic result, and a multivalued circuit connected to the logic circuit means for outputting a predetermined multivalued signal based on the logic result. And a multi-valued multiplier.