JPH0619343U - Noise suppress circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a noise suppressor circuit that can accurately extract H / L of received data even if the received data waveform shows a ringing phenomenon. [Configuration] Binary reception data of H level and L level,
When the shift register 10 of multiple bits sampled by the basic clock and input, and the output of each bit of the shift register are input, and the number of H level bits is equal to or more than the first reference value that is set to be larger than the majority, the H level is set. And a comparison circuit 30 that outputs a second comparison signal that becomes L level when it is less than or equal to a second reference value that is determined to be smaller than a majority, and a first comparison signal when making a transition from H level to L level. A flip-flop circuit 40 that outputs a comparison signal and outputs a second comparison signal when transitioning in the opposite phase is provided, and this output signal is output as reception data.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a noise suppression circuit that is suitable for use in a PLL (Phase Lock Loop) circuit that extracts a clock from received data, and that eliminates noise mixed in a serial signal. Regarding improvements that can extract data.

[0002]

[Prior art]

The present applicant has proposed a noise suppressor circuit in Japanese Patent Application No. 3-56163. FIG. 4 is a circuit diagram proposed in the application. In the figure, the shift register 10 receives the received data 1 and shifts the data to the right every time the basic clock 2 is input, and here, it has 7 bits Q _{A to} Q _G. The majority circuit 20 receives the data of each bit of the shift register 10 and outputs "H" or "L", whichever is larger, and outputs the noise-removed data 3 for each input of the basic clock 2. It is outputting. Here, it is known that the bit width (window) of the majority circuit 20 is most effective when the bit width (window) is smaller than the quarter cycle of the extraction clock of the digital PLL by 1 to 2 bits (1 bit is one cycle of the basic clock 2). ing. Therefore, assuming that the average of the extracted clocks of the digital PLL circuit is about 32 of the basic clock 2, the majority circuit 20 having a window of {(32/4) -1} = 7-bit width is desirable.

Next, the operation of the apparatus thus configured will be described. FIG. 5 is a waveform diagram for explaining the operation of the device of FIG. 4, where (A) is the received data, (B) is the basic clock, (C) is the Q _A bit output of the shift register 10, and (D) is the majority decision circuit. A series of "H" numbers of 20 bits, (E) is noise-removed data. The received data is initially "H", then "L", and finally "H" again. Noise is generated three times during "L" and is erroneously in the "H" state as shown by the diagonal lines. Since the shift register 10 samples the received data in accordance with the basic clock, the influence of the first noise A does not reach the Q _A bit, but the noises B and C after that remain in the Q _A bit as residual noise. . The majority circuit 20 integrates “H” of each bit Q _{A to} Q _G of the shift register 10, outputs “H” if 4 or more and outputs “L” if 3 or less, and noise is eliminated. I have data.

[0004]

[Problems to be solved by the device]

However, in the actual received data, the influence of current reflection may be significant due to impedance mismatch. 6A and 6B are explanatory diagrams of the ringing phenomenon of received data due to current reflection. FIG. 6A shows an input pulse signal and FIG. 6B shows an output signal showing the ringing phenomenon. The ringing phenomenon occurs when the load capacitance of the transmission line is large or when the difference between the low level output current I _OL and the high level output current I _OH is too large. Oscillates in the direction of convergence. In this case, overshoot or undershoot may cause a phenomenon that the threshold voltage for identifying H / L is crossed on the receiving circuit side, and the conventional noise suppressor circuit can obtain accurate received data. There was a problem that I could not do it.

The present invention solves such a problem, and an object thereof is to provide a noise suppressor circuit which can accurately extract H / L of received data even if the received data waveform shows a ringing phenomenon. To do.

[0006]

[Means for Solving the Problems]

 The present invention which achieves such an object is provided with a plurality of bits of binary received data (1) of H level and L level which are sampled and input by a basic clock (2) having a frequency higher than the received data. The shift register (10) and the output of each bit of the shift register are input in synchronization with the basic clock, and the number of H-level bits and the first reference value set to be larger than the majority and the number set to be smaller than the majority are set. A first comparison signal that is H level when the number of bits is equal to or larger than the first reference value, and a second comparison signal that is L level when the number of bits is less than or equal to the second reference value as compared with the second reference value. A comparison circuit (30) that outputs a comparison signal, and inputs the first comparison signal and the second comparison signal in synchronization with the basic clock, and outputs the first comparison signal when transitioning from H level to L level Then L When transitioning to the H level are provided with a flip-flop circuit for outputting a second comparison signal (40) from the bell. The output signal of the flip-flop circuit is output as the received data.

[0007]

[Action]

 The shift register serves as a data buffer for the simplification number determined by the extraction clock of the digital PLL to be used and the basic clock, and constitutes a time window together with the comparison circuit. The comparator circuit has two types of reference values, large and small, and outputs a comparison signal by comparing with the simple integrated value of each bit of the shift register, and has a hysteresis characteristic. The flip-flop circuit extracts the received data from which the influence of the ringing phenomenon has been removed by the two comparison signals output from the comparison circuit.

[0008]

【Example】

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. In FIG. 1, the same reference numerals are given to those having the same functions as those in FIG. 4 described above, and the description thereof will be omitted. Comparator circuit 30 has each bit Q _A to Q _G and connected bit X _A to X _G to one-to-one shift register 10, of each bit X _A ~X _G "H" level The total number is compared with the first reference value and the second reference value. The first reference value is set to be larger than the majority of the total number of bits (7/2), and is 6 here. The first comparison signal 31 becomes H level when the number of H level bits is equal to or larger than the first reference value. On the other hand, the second comparison signal 32 becomes L level when the number of H level bits is equal to or less than the second reference value.

The flip-flop circuit 40 is a JK type here, and the first comparison signal 31 is input to the J terminal and the second comparison signal is input to the K terminal. Then, the basic clock is applied to the clock terminal CLK to determine the sampling timing. Although noise-removed data is output from the Q terminal, the first comparison signal is output here when transitioning from H level to L level, and the second comparison signal is transitioned when transitioning from L level to H level. It is a connection that outputs a signal.

The operation of the device configured as above will be described below. FIG. 2 is a waveform diagram for explaining the operation of the apparatus of FIG. 1, where (A) is the waveform on the transmission path, (B) is the received data, and (C) is the bits X _{A to} X _G of the comparison circuit 30. The total number of H "levels, (D) represents the noise-removed data. Due to the ringing phenomenon, the waveform on the transmission line may fall below the H / L threshold voltage of the receiving circuit even when it should originally be at the H level. Then, the received data is at the L level in this section. Then, the total number of "H" level of the bits X _A to X _G of the comparator circuit 30 illustrated in each basic clock becomes three small remote by majority. However, the hysteresis effect of the comparison circuit 30 and the flip-flop circuit 40 causes the noise-removed data to shift to the H level because the total number of the “H” level of each bit X _{A to} X _G of the comparison circuit 30 is 6. Since this is the case, it is possible to prevent the phenomenon similar to the hunting phenomenon from occurring. It is assumed here that the ringing frequency is lower than the basic clock and higher than the received data frequency.

FIG. 3 is an explanatory diagram of the hysteresis action of the comparison circuit 30 and the flip-flop circuit 40. The transition from H level to L level is when the total number of "H" level of the bits X _A ~ X _G of the comparison circuit 30 becomes six of five. On the other hand, the transition from L level to H level is when the total number of "H" level of the bits X _A to X _G of comparator circuit 30 is changed from two to one. Even if the ringing phenomenon occurs in this way, stable reception data can be extracted by adding hysteresis.

[0012]

[Effect of device]

 As described above, according to the present invention, even if the overshoot or the undershoot is superimposed on the transmission waveform due to the current reflection, the hysteresis effect of the comparison circuit 30 and the flip-flop circuit 40 provides a good noise removal effect. The effect is that the received data can be accurately extracted.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating the operation of the device of FIG.

FIG. 3 is an explanatory diagram of a hysteresis function of a comparison circuit 30 and a flip-flop circuit 40.

FIG. 4 is a circuit diagram disclosed in the prior application.

5 is a waveform chart explaining the operation of the apparatus of FIG.

FIG. 6 is an explanatory diagram of a ringing phenomenon due to current reflection.

[Explanation of symbols]

 10 shift register 30 comparison circuit 40 flip-flop circuit

Claims (1)

[Scope of utility model registration request] 1. A multi-bit shift register (10) for inputting binary reception data (1) of H level and L level by sampling with a basic clock (2) having a frequency higher than this reception data, The output of each bit of the shift register is input in synchronization with the basic clock, and the number of bits at the H level is compared with the first reference value set larger than the majority and the second reference value set smaller than the majority. , A comparison circuit that outputs a first comparison signal that becomes an H level when the number of bits is greater than or equal to a first reference value and a second comparison signal that becomes an L level when the number of bits is less than or equal to a second reference value ( 30), and inputs the first comparison signal and the second comparison signal in synchronization with the basic clock, outputs the first comparison signal when transitioning from H level to L level, and transitions from L level to H level Rutoki noise suppression circuit, characterized in that comprises a flip-flop circuit (40), and outputs an output signal of the flip-flop circuit as the received data to output a second comparison signal.