JPH061910B2 - Wireless selective call receiver - Google Patents

Description

The present invention relates to a radio selective call receiver used for radio calling.

In recent years, advances in integration technology have been remarkable, and even in this kind of radio selective call receiver, downsizing, multi-functionalization and low power consumption of equipment are being realized. And 1 of multifunctionality
In recent years, in addition to the conventional service using only a selective call signal (a specific number assigned to a subscriber), a service for adding a message signal together with the selective call signal can be provided. The selective call signal and the message signal are digitally encoded in order to expand the demand range and enhance the reliability of communication.

After the selective call signal is received, the display of the message signal in the receiver is performed simultaneously with the operation of the function of notifying the reception. In addition, a plurality of message signal storage circuits are provided in the receiver, because the receiver may be called frequently and the subscriber may not take any action immediately after receiving the message signal. As a message reading method in the case where such a memory circuit is provided, as a method of preparing n reading switches and reading an arbitrary message signal by this, or the owner of the receiver uses one reading switch. There is a method of reading out an arbitrary message signal by operating once a total of n times. A radio selective call receiver having such a function is very convenient for the owner because it can receive and display a message and store the message to perform a plurality of treatments over a certain period of time. It is a thing.

However, the number of memory circuits used cannot be increased too much due to the limitation of elements or software,
When more message signals than the number of memory circuits are received, the oldest message signals must be erased. In order to eliminate this inconvenience, there has been proposed a radio selective call receiver capable of retaining important message information among a plurality of stored message signals which is desired to be stored for a long time. (Reference: Showa 57
By the way, the treatment of the message contents is not always performed from the old message contents, and may be variously changed depending on the situation at that time, the difficulty level and the importance level of the message. Therefore, the fact that the message contents that have been dealt with remain stored in the memory is actually
Many will be seen. This cannot be said to make the most effective use of the few storage elements.

An object of the present invention is to eliminate the above-mentioned drawbacks and further improve the above-mentioned proposal, and to provide a radio selective call receiver capable of making the most effective use of a limited number of storage elements.

According to the invention, each receives a digitally encoded selective call signal and a subsequent message signal,
It includes storage means for respectively storing a plurality of different contents of the received message signal, means for reading the contents of the storage means by a switch operation, and means for notifying the contents read by the reading means by voice or display. In the radio selective calling receiver, there is provided a radio selective calling receiver characterized by adding a means for erasing or holding specific contents among a plurality of contents stored in the storage means.

Next, a radio selective calling receiver according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a radio selective call receiver according to the present invention. The radio signal received by the antenna 1 is amplified and demodulated by the radio unit 2. The demodulated signal is converted by the waveform shaping circuit 3 into a waveform readable by the decoder 4.

The decoder 4 is a writable read-only memory (Programm
(Available-Read Only Memory: P-ROM) 5 compares its own calling number with a signal from the waveform shaping circuit 3 in advance, and when both match, an amplifier 6 is provided to notify the calling. A sound signal is supplied to drive the speaker 7. The decoder 4 also decodes the message signal following the selective call number and drives the LCD 8 to provide the recipient with visible information. The reset switch 9 and the mode changeover switch 10 are connected to the decoder 4, and stop the sound, stop and start the LCD display, and hold and erase the memory contents. The crystal oscillator 11 is a clock generating oscillator that operates the decoder 4.

Next, the configuration of the decoder 4 will be described in more detail with reference to FIG. The decoder 4 is a one-chip central processing unit (Cent
Ral Processing Unit (CPU), a series of operation instructions as a decoder is written in the program memory 401, the content of the address corresponding to the program counter 402 is output to the control unit 403, and by this content,
The control unit 403 sends a control signal C to each unit. The program counter 402 increments by one each time the content of the program memory 401 is sent to the control unit 403, but when there is a jump instruction or the like, it follows it.

The interface between the external circuit and the data bus 408 includes an output port a (404), an input port b (405), and an output port c (4).
06) and the input port d (407). The output port a (404) sends a sound signal, and the input port b (405) reads the data from the waveform shaping circuit 3 and reads the states of the reset switch (RS) 9 and the mode changeover switch (MS) 10. The output port c (406) is P-R
Send the read pulse of OM5 to input port d (407) at P-
Read data from ROM5 respectively. Further, the data bus 408 includes a program counter 402, a data memory 409, an accumulator 410, and an arithmetic unit (Arithemeti).
C and Logic Unit (ALU) 411 is also connected to transfer data. The synchronization clock required for reading data from the waveform shaping circuit 3 is generated by the crystal oscillator 11, the oscillator 413, and the timer 412. L
The CD control / driver 414 is a control / driver circuit for displaying a specific one of the data stored in the memory 409 on the LCD 8.

FIG. 3 is a diagram conceptually showing a part of the data memory 409 in the decoder. In the figure, MDATA1 to 4 are message memories, and MAD1 to 4 are memory addresses designating any one of MDATA1 to 4, for example, MDATA.
If the content of AD1 is "3", MDATA3 is indicated. R
C is a MAD counter at the time of reading operation by the reset switch, and TM is a temporary memory for temporarily storing the contents of MAD1 to MAD4. Further, PF is a protect flag, and when the flag is set, any of the stored messages is protected.

In addition, MDATAx (x =
1 to 4) and x indicating the message reception order are displayed.

Next, the operation at the time of receiving the call signal will be described with reference to FIG. The step numbers in the flowchart are
In the following description, it is shown in parentheses after the explanation phrase or sentence.

In FIG. 4, the contents of each memory are initialized when the power is connected (501). “4” is entered in MAD1, “3” is entered in MAD2, “2” is entered in MAD3, “1” is entered in MAD4, and MDATA1 to 4, PF, RC and TM are all cleared. Then, when the ringing signal is received (503), a message receiving operation is next performed (504), and ringing and message display are started (505). When RS9 is pressed (506), only the sound stops (507), and when RS9 is released (508), the display timer starts (50).
9). Further, it is checked whether MAD1 is protected (510), and if not, MAD1 to AMD are checked.
4 is rotated one by one to store the message in the memory MDATAx designated by MAD1. If MAD
If 1 is protected, set MAD2 to MAD4 to 1.
Memory MDAT specified by MAD2
Store the message in Ax and protect MAD1 (5
11-514). After that, the display timer times out (5
The display is erased (517) by pressing 15) or RS9 (516).

Next, the standby operation and the memory protect and memory erase operations will be described with reference to the flowcharts of FIGS. 5-1 to 5-3. In the standby state (601), it is constantly checked whether or not the RS9 is pushed (602), and when it is pushed, the memory content reading operation is started. First, RC (read counter) is set to "1" (603), the contents of RC are put in the x register, and MDATAz specified by MADx (= z) is set.
If the message is stored in, the contents of MDATAz are displayed (605, 613). MDAT specified by MADx
If no message is stored in Az, it is judged whether x is 1 (606), and when x = 1, no message is stored in the memory to indicate that no message is stored in the display. Display all "8". The display timer is started by releasing RS9 (609,610) and the display is erased by the timer timing out or by pressing RS9 again (611,612). When x ≠ 1, the display is erased.

After the contents of MDATAz are displayed, the display timer is started by releasing RS9 (614, 615). After that, it is monitored whether RS9 and MS10 are pushed (616,6
19), depending on whether RS9 is pressed (616) or the display timer times out (620), RC becomes "RC + 1".
Is set (618), and then it is determined whether RC is greater than 4 (618). When RC ≦ 4, the process returns to step 604 and the same operation is repeated. When RC> 4, the display is erased and the state returns to the standby state (601).

When the MS 10 is pressed (619) after the display timer starts (615), the mode switching timer starts (621). When the MS 10 is kept pressed for a certain time or longer, the displayed message and x start blinking (622, 623, 624).
At the same time, the memory protection timer is set (62
Five). When MS10 is pressed in this state, the memory protect operation starts and the contents of MADx shift to MAD1. Then, the contents of the other three MADs are shifted by one. For example, when the contents of the memory specified by MAD3 are protected, the contents of MAD3 are temporarily moved to TM, and then the contents of MAD2 are transferred to MAD3 and MAD3.
The contents of 1 are moved to MAD2, and finally the contents of TM are moved to MAD1 (627). Then, the protect flag is set (628) in MAD1, and the contents of the memory designated by MAD1 and 1 are displayed. That is, the blinking of the contents of the blinking display is stopped, and x changes to 1 to stop the blinking (629).

If RS9 is pressed while the memory protection timer is set (630), the blinking display of the memory contents designated by MADx is erased (631) and the memory erase timer is set (632). When the MS 10 is pressed in this state, the memory erase operation starts (635). First, it is determined whether x is 1 (650), and when x = 1, MAD1
It is determined whether or not the protect flag is set in (651), and if the protect flag is set, the protect flag is cleared (652).

Next, the memory erase operation will be described in detail. First, the contents of MADx are transferred to TM. And step 65
Shift the contents of MAD as shown in the flow from 4 to 659. For example, when erasing the memory contents specified by MAD2, the contents of MAD2 are temporarily moved to TM. Then, the contents of MAD3 are moved to MAD2, the contents of MAD4 are moved to MAD3, and the contents finally stored in TM are moved to MAD4 (659). Then, the contents of the memory specified by MAD4 are erased, and the blinking display of x on the display is erased to indicate that the memory is erased.
Complete memory erase (660, 661).

Also, if RS9 and MS10 are not pressed until the timer times out after the memory protection timer and memory deletion timer are set (633), M
Display (634) the content of memory specified by ADx and x,
Return to step 615.

As described above, according to the present invention, the contents of the memory can be protected and erased by a simple operation, and the contents of the memory that are no longer needed can be erased. Therefore, it is possible to make the most effective use of the limited number of memories.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention, FIG. 2 is a conceptual block diagram of a decoder section in FIG. 1,
FIG. 3 is a conceptual diagram showing a part of the data memory in FIG.
FIG. 4 and FIGS. 5-1 to 5-3 are flowcharts showing the operation of the receiver shown in FIGS. In the figure, 1 ... Antenna, 2 ... Radio section, 3 ... Waveform shaping circuit, 4 ... Decoder section, 5 ... ROM section, 6 ...
… Speaker drive circuit, 7 …… Speaker, 8 …… Display,
9 ... RS (readout switch and selection switch), 10 ...
MS (mode switch), 11 clock oscillator, 12 power switch, 401 program memory, 402 program counter, 403 control unit, 404 output port a, 405 input port b, 406 ... Output port c, 407 ... Input port d, 408 ... Data bus, 409 ... Data memory,
410 ... Accumulator, 411 ... ALU, 412
... Timer, 413 ... Oscillator.

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Masaaki Akahori 53-1331 Shiba, Minato-ku, Tokyo Inside NEC Corporation (72) Inventor Daisuke Ishii 5-33-1 Shiba, Minato-ku, Tokyo Japan Electric company (56) Reference JP 56-93440 (JP, A) JP 54-80627 (JP, A) JP 55-18084 (JP, B2)

Claims (1)

[Claims] 1. A selective call signal comprising a digital code,
In a radio selective call receiver for receiving a subsequent message signal, a first means for storing a plurality of received message signals following the selective call signal destined for its own receiver, and the first means are stored. Second means for protecting a particular message signal of the received message signal from being erased, and optionally erasing the particular message signal protected by the second means and the received message signal not erase-protected A radio selective calling receiver, comprising: a third means for performing the above and a fourth means for displaying the received message signal.