JPH06189263A - Digital high definition video signal recorder - Google Patents

Abstract

PURPOSE:To reproduce a recording medium in which a digital high definition signal is recorded by a VTR for a standard high definition video signal as well, and besides, to improve the quality of the reproduced picture of the high definition signal. CONSTITUTION:In the two-dimensional frequency spectrum of the HD signal, it is divided in both a horizontal direction and a vertical direction respectively, and a low frequency band signal LL and the other frequency band signals HL, LH, HH are formed. The low frequency band signal LL is compressed by DCT, variable length encoding and buffering by an encoding circuit 19, and the encoded output of the rate of 27 Mbps is formed. Besides, the differential signal of a local decoded signal and an original signal is formed. This differential signal and the signals of the other frequency bands are quantized respectively, and the encoded output of the total rate of 23 Mbps is generated by the buffering. These encoded outputs are made into the rate of 25 Mbps respectively, and are recorded as separate tracks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal recording apparatus applied to compression-encoding a high-definition video signal (HD signal) and recording the encoded output on a magnetic tape.

[0002]

2. Description of the Related Art A digital VTR for recording a digital video signal on a magnetic tape by a rotary head is known. Since the amount of information in a digital video signal is large,
High-efficiency coding for compressing the amount of transmitted data is often adopted. Among various high efficiency coding, DC
Practical application of T (Discrete Cosine Transform) is progressing.

In the DCT, one frame image is converted into, for example, (8
X8) is converted into a block structure, and this block is subjected to cosine transform processing which is a kind of orthogonal transform. As a result, (8 × 8) coefficient data is generated. Such coefficient data is transmitted after being subjected to variable-length coding processing such as run-length coding and Huffman coding. At the time of transmission, in order to facilitate data processing on the reproducing side, a code signal, which is an encoded output, is inserted into the data area of a sync block of a certain length, and a sync signal, I
The sync block to which the D signal is added is framed.

A digital VTR using a magnetic tape,
In a disc recording device or the like using a disc-shaped recording medium, it is usual that one field or one frame of video data is recorded on a plurality of tracks. However, when a variable length output is formed as in the DCT described above, the amount of data in these predetermined periods fluctuates. Therefore, equalization processing (referred to as buffering) is performed to reduce the amount of data in the predetermined period to the target value or less. The predetermined period may be one field and one frame, but it is preferable to control the data amount in a shorter period (referred to as a buffering unit) in order to reduce the required memory capacity.

Regarding a standard definition video signal (referred to as an SD signal) such as the 525/60 system, the transmission rate of recording / reproducing data is set to, for example, 25 Mbps.
The number of pixels of the HD signal in the horizontal direction is about 2 with respect to the SD signal.
Since the number of horizontal scanning lines is about twice, the original amount of information is about four times that of the SD signal. As a digital VTR capable of recording / reproducing such an HD signal, there is a digital VTR which uses a multi-track system for simultaneously forming two parallel tracks. 50Mbp by processing HD signal
If a transmission rate of s is achieved, HD signals can be recorded by a multi-track method in which the number of tracks formed in the same time can be twice that of SD signals.

[0006]

It is preferable that the magnetic tape on which the HD signal is recorded can be reproduced by the SD VTR. As one of the methods, it is considered that the HD signal is divided into a low frequency component and a high frequency component, each component is compression-encoded, and the encoded output is recorded on different tracks. HD VTR plays all tracks and SD
The VTR for reproduction reproduces only the track in which the encoded output of the low frequency component is recorded. To achieve such compatibility,
It is necessary that the data amount of the encoded output of the low frequency component is equal to that at the time of recording the SD signal, for example, 25 Mbps. Further, it is preferable that the encoded output data amount of the high frequency component is also 25 Mbps.

Accordingly, one object of the present invention is to provide a digital high-definition video signal recording apparatus capable of realizing compatibility in which a tape on which an HD signal is recorded can be reproduced by an SD VTR.

Another object of the present invention is to provide a digital high definition video signal recording apparatus capable of improving the quality of a restored image.

[0009]

The invention according to claim 1 is
What is claimed is: 1. A digital high-definition video signal recording apparatus, wherein a digital high-definition video signal is compression-encoded, and the definition-encoded output is recorded as a plurality of tracks on a recording medium. Circuit for forming first to fourth band signals by dividing each of the two-dimensional frequency spectrum in the horizontal direction and the vertical direction, and a device for recording a digital video signal whose encoded output data amount is standard definition The amount of data obtained by summing the first encoding circuit for encoding the first band signal and the encoded outputs of the second, third and fourth band signals so as to be substantially equal to For encoding the second, third and fourth band signals so that is approximately equal to that in a device for recording standard definition digital video signals. A second coding circuit, a digital high definition video signal recording apparatus comprising a circuit for recording on a recording medium the encoded outputs of the first and second coding circuit.

According to a second aspect of the present invention, the two-dimensional frequency spectrum of the digital high-definition video signal is divided into two in the horizontal direction and in the vertical direction.
~ Encoding and encoding the first band signal so that the circuit for forming the fourth band signal and the data amount of the encoded output are substantially equal to those in the apparatus for recording the standard definition digital video signal A first encoding circuit for locally decoding the output and forming a difference signal between the locally decoded output and the input data, and an encoded output for each of the difference signal, the second, third and fourth band signals A second encoding for encoding the differential signal, the second, third and fourth band signals so that the total amount of data is approximately equal to that in a device for recording a standard definition digital video signal. A digital high-definition video signal recording apparatus comprising a circuit and a circuit for recording the encoded outputs of the first and second encoding circuits on a recording medium.

[0011]

The HD signal has a horizontal frequency and a vertical frequency having a low frequency range LL, and the other signals HL, LH, and HH.
Will be divided. The low-frequency signal LL is processed as being equivalent to the SD signal, and the data amount of the encoded output is made substantially equal to that of the SD signal VTR. The signals in the other bands have the total amount of encoded output data made substantially equal to that of the SD signal VTR. These are recorded as separate tracks on the magnetic tape. The VTR for HD reproduces all tracks and
Play the signal. The SD VTR reproduces the track of the signal LL corresponding to the SD signal. Therefore, compatibility between HD and SD can be realized.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 and 2 show a digital VTR.
2 shows a configuration of a video data processing circuit provided on the recording side. FIG. 1 and FIG. 2 respectively show the configuration on the recording side divided in the middle due to the restriction of the drawing space.

In FIGS. 1 and 2, each component Y of the HD video signal is connected to the input terminal of the recording circuit.
P _R and P _B are supplied. The respective components are respectively supplied to the low pass filters 1Y, 1R, 1B for band limitation. The output signals of the low pass filters 1Y, 1R, 1B are supplied to the A / D converters 2Y, 2R, 2B, respectively. From the A / D converters 2Y, 2R, 2B, digitized HD component signals are obtained. A
The component signal at the output of the / D converter is referred to as a 16: 8: 8 signal due to the sampling frequency ratio.

As shown in FIG. 3, this embodiment uses 112
The target is a 5/60 system (also called a high-definition system) or a 1250/50 system (also called a HD-MAC system). The sampling frequency is 54 MHz, which is common to both systems. This is Y
As for the color signal, a sampling frequency (27 MHz) that is half that of the Y signal is selected. SD
In the case of signals, 13.5 MHz is the sampling frequency.

The color signals are A / D converters 2R, 2B.
A multiplexer 3 and a decimating filter 4 provided after ## EQU1 ## perform conversion to a line-sequential signal and 1/2 decimating processing. After such preprocessing, the portion excluding the blanking interval and the like is compression-coded as an effective area.

The (8 × 8) pixels in the frame are the minimum unit of transform coding (DCT block, but in the following description,
It is simply called a block). One macroblock is composed of a total of 6 blocks, that is, four Y signal blocks occupying the same position spatially and one P _R signal block and one P _B signal block.

Here, the preconditions for an encoding algorithm having SD / HD compatibility are: (1125/60) SD: 25 Mbps, 10 tracks / frame HD: 50 Mbps, 20 tracks / frame (1250/50) SD : 25 Mbps, 12 tracks / frame HD: 50 Mbps, 24 tracks / frame

For example, in the case of 1125/60, when the HD signal is compressed to 50 Mbps, the SD equivalent portion is 25 Mbps.
s, other parts are set to 25 Mbps, and each part is set to 10
Record alternately as tracks. FIG. 4 shows two examples of track patterns. In the case of FIG. 4A, the SD signal equivalent portion is recorded in one channel A of the two channels (A and B), and the other portion SUR is recorded in the other channel B. The HD VTR reproduces all tracks of channels A and B, and the SD VTR reproduces only channel A. In the case of FIG. 4B, FIG.
In this example, the signals SD and SUR are recorded for every one track, whereas these are alternately recorded for every two tracks.

Next, an example of the encoding algorithm according to the present invention will be described. As shown in FIG. 5A, the horizontal (H) direction and the vertical (V) direction of the two-dimensional frequency spectrum of the HD signal are divided into two. As a result, an LL signal having a low horizontal frequency and a vertical frequency, an HL signal having a high horizontal frequency and a low vertical frequency, an LH signal having a low horizontal frequency and a high vertical frequency, a horizontal frequency and a vertical frequency An HH signal whose frequency is both high is formed.

Next, the LL signal is used as an SD equivalent signal and
Compress to Mbps. A difference signal between the data obtained by locally decoding the encoded output and the original LL signal is formed. This differential signal and the HL signal, LH signal, and HH signal of other bands are combined and compressed to 25 Mbps. FIG. 5B shows the signals S0, S1, S2 and S3 that make up the signal SUR other than the LL signal. S0 corresponds to the differential signal, and S1, S2,
S3 corresponds to the HL signal, the LH signal, and the HH signal, respectively.

FIG. 6 and FIG. 7 show 1 for band division.
Denotes dimensional (ie, horizontal or vertical frequency axis) division. When the input signal x (n) having the spectrum shown in FIG. 7A is supplied, it is divided into low-pass components and high-pass components by the filters (low-pass filter 5 and high-pass filter 6) having the characteristics shown in FIG. 7B. A QMF (Quadrature mirror filter) is used as these filters.
Therefore, the spectrum of the output signal of the low pass filter 5 is shown in FIG. 7C, and the spectrum of the output signal of the high pass filter 6 is shown in FIG. 7D.

The output signals of the low-pass filter 5 and the high-pass filter 6 are recorded / reproduced through the 1/2 thinning circuits 7 and 8, respectively. On the reproducing side, the signals of the respective bands are supplied to the interpolation circuits 77 and 78, respectively, and are returned to the signals of the original sample number. Then, the signals are supplied to the low-pass filter 75 and the high-pass filter 76, the outputs of these filters are added, and the output signal x ^ (n) is obtained.

In the configuration of FIG. 6, assuming that the transfer functions of the low-pass filters 5 and 75 are H (ω) and the transfer functions of the high-pass filters 6 and 76 are H (-ω), the condition for perfect reconstruction (that is, restoration) The condition that the signal matches the input signal) is | H (ω) | ² + | H (ω + π) | ² = 1. The band division shown in FIG. 6 is applied to each of the horizontal direction and the vertical direction, and the HD signal is divided into four bands as shown in FIG. 5A.

Now, returning to FIG. 1, the structure of the recording process will be described. The digital Y signal from the A / D converter 2Y is supplied to the low pass filters 5Y and 6Y. These filters 5Y and 6Y perform band division in the horizontal direction. Half thinning circuits 7Y and 8Y are connected to the filters 5Y and 6Y, respectively. A low pass filter 9Y and a high pass filter 10Y are connected to the thinning circuit 7Y. Similarly, for the thinning circuit 8Y, the low-pass filter 11Y and the high-pass filter 1
2Y is connected.

These filters 9Y, 10Y, 11Y and 12Y perform band division in the vertical direction. For each filter, 1/2 thinning circuits 13Y, 14Y, 1
5Y and 16Y are connected. As a filter, F
IR digital filters can be used.

As for the color signal, a circuit for band division is provided, like the Y signal described above. Since this configuration is the same as that of the Y signal, the corresponding portions are given the same reference numerals with the suffix C and the description thereof is omitted.
The output signals of the thinning circuits 13Y and 13C are supplied to the multiplexer 17, and the output signals of the other thinning circuits are supplied to the multiplexer 18. At the output of the multiplexer 17, a signal LL in which the luminance signal and the color signal are combined as a macro block is obtained. At the output of the multiplexer 18, signals LH, HL, and HH in which the luminance signal and the chrominance signal are similarly combined are separately obtained.

As shown in FIG. 2, a coding circuit 19 for compressing and coding the signal LL is connected to the multiplexer 17, and signals LH and H are supplied to the multiplexer 18.
An encoding circuit 20 for compression encoding of L and HH is connected. Here, the number of effective pixels input to the encoding circuit 19 is 1/4 of the number of pixels shown in FIG. That is, 7
It is 20 × 520 (samples / frame). this is,
It is larger than the number of effective pixels of the SD signal (720 × 480 samples / frame). Therefore, the target of the data amount in the buffering process for controlling the data amount of the encoded output is set to 25 × (520/480) = 27.083 (Mbps). Of that, 25 Mbps equivalent is recorded on the SD track.

The remaining data is recorded on another track as a signal SUR other than SD. The total data amount of the band signal other than the signal LL and the differential signal is compressed to 25-2.083 = 22.917 (Mbps).

First, the encoding circuit 19 will be described.
In the block formation and shuffling circuit 21 provided in the first stage of the encoding circuit 19, a block formation process in which video data in the interlaced scanning order is converted into data having a block structure of (8 × 8), for example, Within one frame,
Processing for changing the spatial position from the original one, that is, shuffling is performed in units of macroblocks.

The output of the blocking and shuffling circuit 21 is supplied to a DCT (cosine transform) circuit 22.
From the DCT circuit 22, (8 × 8) coefficient data (that is, coefficient data of DC component AC and AC component AC) is generated. The macro block has (8 ×
8) is a collection of multiple blocks of coefficient data.
4 Y blocks and 1 P at the same position in the frame
6 blocks in total including _R block and 1 P _B block
Make up a macroblock.

The DC component DC of the (8 × 8) coefficient data generated in the DCT circuit 22 is transmitted to the circuit in the subsequent stage without being compressed, and 63 AC components thereof are quantized via the buffer 23. Is supplied to the digitization circuit 24. The coefficient data of the AC component is transmitted in the order of zigzag scanning from the AC component having a lower order to the AC component having a higher order. Further, the coefficient data for this alternating current is supplied to the data amount estimation device 25. The buffer 23 delays the coefficient data by the time required for the estimator 25 to determine the appropriate quantization step. The quantizing number QNo corresponding to the quantizing step from the estimator 25 is supplied to the quantizing circuit 24 and is transmitted to a subsequent stage (not shown).

In the quantizing circuit 24, the AC component in the coefficient data is quantized. That is, the coefficient data for the alternating current is divided by an appropriate quantization step, and the quotient is converted into an integer. This quantization step is determined by the quantization number QNo from the estimator 25. Since the amount of data generated by DCT and variable length encoding varies depending on the pattern to be encoded, the amount of generated data in a buffering unit (eg, 5 sync block length) shorter than one field or one frame period is less than or equal to a target value. The buffering process for The reason for shortening the buffering unit is to simplify the buffering circuit, such as reducing the memory capacity for buffering.

The output of the quantizing circuit 24 is supplied to the variable length coding circuit 26, and two-dimensional Huffman coding is performed. That is, the run length, which is the number of consecutive "0" s of the coefficient data, and the value of the coefficient data are given to the Huffman table stored in the ROM, and the variable length code (encoded output) is generated. The code signal from the variable length coding circuit 26 is supplied to the divider 27. The output signal of the divider 27 is supplied to the framing circuit 28, and data corresponding to the SD signal is generated at the output thereof.

In connection with the estimator 25, the same two-dimensional Huffman table referred to by the variable length coding circuit 26 is provided. This Huffman table generates bit number data of an output code when variable length coding is performed.
The estimator 25 determines the optimum quantization step, and the quantization circuit 24 quantizes the coefficient data at this quantization step.

FIG. 2 is a schematic configuration of the encoding circuit 19, and more specifically, a process of distinguishing a DCT transform between a still block and a motion block, a quantization step of coefficient data, and a block definition. A process of changing the quantization step depending on the (activity), a process of changing the quantization step according to the order of the coefficient data, and the like are performed. However, since these processes have little relation to the essence of the present invention, detailed description thereof will be omitted.

The data generated by the above-mentioned encoding is supplied to the framing circuit 28. Framing circuit 2
At 8, error correction coding processing, recording data conversion into a frame structure, and track shuffling are performed. The output of the divider 27 is 27, as described above.
Recorded data of Mbps occurs, of which 25 Mbps
The data for s is supplied to the framing circuit 28 and 2M
Data for bps is supplied to the framing circuit 64. Therefore, the data amount corresponding to the SD signal is 25 Mbps
Is.

Further, the quantization circuit 24 of the encoding circuit 19
A local decoding circuit including an inverse quantization circuit 29 and an inverse DCT circuit 30 is connected to the. The locally decoded data is supplied to the subtraction circuit 31. The subtraction circuit 31 is supplied with the original signal via the phase matching buffer 32.
Therefore, the subtraction circuit 31 produces a difference signal corresponding to the coding error. This difference signal is a signal L in another band
It is encoded in the encoding circuit 20 together with H, HL, and HH.

Blocking and shuffling circuits 41, 42, 4 are provided for each of the signals LH, HL, HH.
3 is provided. The output signals of these circuits are the buffer 4
4, 45, 46. Buffers 44, 45, 4
Reference numeral 6 is provided for phase matching between the differential signal generated at the output of the subtraction circuit 31 and the band signal. For these buffers, phase matching buffers 48, 49,
50 is connected. The difference signal from the subtraction circuit 31 is also supplied to the buffer 47. The output signals of the buffers 47 to 50 are supplied to the quantizing circuits 51, 52, 53 and 54, respectively.

The buffers 47 to 50 delay the data until the optimum quantizer step widths are determined by the estimators 55, 56, 57 and 58 provided in parallel with them. Quantization circuits 51-54 for buffers 47-50
Are connected respectively. A quantizer number is supplied from the estimator to the quantizer circuit. As shown in FIG. 8, when the quantization number q is supplied to the quantization circuit 51 which quantizes the difference signal, the quantization circuits 52 and 53 which quantize the signals HL and LH, respectively, are , The quantization number q + 1 is supplied, and the quantization number q + 3 is supplied to the quantization circuit 54 that quantizes the signal HH.

Like the estimator 25 in the encoding circuit 19 described above, the estimators 55 to 58 are provided to keep the data amount of the encoded output below the target value from the terminal 59. That is, the quantization step width is controlled so that the total data amount of the encoded output of the differential signal and the encoded output of the three band signals supplied to the framing circuit 64 is equal to or less than the target value (23 Mbps). It Although omitted for simplification, the quantization step width corresponding to the quantization number q is defined, and when the quantization number increases, the quantization step width tends to increase.

In this example, since the quantization number is shifted as described above, the quantization for the differential signal is fine and the quantization for the high frequency signal HH is coarse. This is because the difference signal and the low frequency signal have a larger influence on the image quality of the reproduced image.

The output signals of the quantizing circuits 51 to 54 are supplied to the variable length coding circuits 60, 61, 62 and 63, respectively. These variable length coding circuits perform run length coding and variable length coding. That is, the number of consecutive zeros in the quantized output is coded, and only the non-zero value of this code is variable length coded. As with the variable length coding circuit 26, the variable length coding is 2
Dimensional Huffman coding may be used.

Output data of the variable-length coding circuits 60 to 63 (total data amount is 23 Mbps) and output data of the divider 27 (2 Mbps) are supplied to the framing circuit 64. The framing circuit 64 is the framing circuit 2
As in the case of 8, the process of error correction coding, the process of converting the recording data into a frame structure, and the track shuffling are performed. The output of the framing circuit 64 is further channel coded to form recording data SUR.

S corresponding to the output of the framing circuit 28
The D-equivalent signal, the output of the framing circuit 64, and the corresponding signal SUR are recorded in the track pattern shown in FIG. 4A or 4B. As described above, when this recording pattern is reproduced by the HD VTR, not only an HD image can be obtained, but also by the SD VTR, the signal L
A reproduced image can be obtained by the component of L.

FIG. 9 shows the processing of another embodiment of the present invention. As shown in FIG. 5A, after dividing the HD signal into four bands, the low frequency signal LL is encoded by the intraframe processing. This is done by DCT and variable length coding as in the above-described embodiment. Other band signals HL, LH, HH
With respect to, each of the two is intra-frame encoded.

That is, four consecutive frames F
, Are divided into two frames, and the first frames F1, F3, ... Are intra-frame coded. In the next frames F2, F4, ..., Differences for each pixel from the previous frame are calculated, and the differences between the frames are encoded. That is, the differential signal is quantized, and the quantized output is variable length coded. The buffering controls the data amount for every two frames to be a predetermined amount. For example, 5x2
= 10 sync blocks are a buffering unit.

[0047]

According to the present invention, the low frequency component is coded so that the data amount is substantially equal to that of the SD signal, and the other band signals are also encoded to the data amount substantially equal to that of the SD signal. , These encoded outputs are recorded as separate tracks. Therefore, not only the HD signal can be reproduced by the VTR for HD, but also the reproduced image corresponding to the SD image can be obtained by reproducing the tape by the VTR for SD. Furthermore, by transmitting the difference signal between the locally decoded output and the original signal for the low frequency component, the quality of the reproduced HD image can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a part of a recording data processing circuit of a digital VTR according to the present invention.

FIG. 2 is a block diagram of the rest of the recording data processing circuit of the digital VTR according to the present invention.

FIG. 3 is a schematic diagram used to explain a digital HD signal to which the present invention can be applied.

FIG. 4 is a schematic diagram of an example of a track pattern recorded on a tape.

FIG. 5 is a schematic diagram showing band division of an HD signal.

FIG. 6 is a block diagram of an example of a circuit for band division.

FIG. 7 is a frequency spectrum diagram for explaining band division.

FIG. 8 is a schematic diagram for explaining a quantization operation.

FIG. 9 is a schematic diagram for explaining another embodiment of the present invention.

[Explanation of symbols]

 19, 20 Encoding circuit 21, 41, 43 Blocking and shuffling circuit 22 DCT circuit 29 Inverse quantization circuit 30 Inverse DCT circuit

Claims (5)

[Claims] 1. A digital high-definition video signal recording apparatus, wherein a digital high-definition video signal is compression-encoded and the encoded output is recorded as a plurality of tracks on a recording medium. Means for forming the first to fourth band signals by dividing each of the two-dimensional frequency spectrum of the two-dimensional frequency signal in the horizontal and vertical directions, and a digital video whose encoded output data amount is standard definition. First encoding means for encoding the first band signal so as to be substantially equal to that in the device for recording the signal, and a code for each of the second, third and fourth band signals. The second, third and third elements are arranged so that the total data amount of the digitized outputs is substantially equal to that in the apparatus for recording the standard definition digital video signal. And a second high-definition digital encoding means for encoding the fourth band signal, and means for recording the encoded outputs of the first and second encoding means on the recording medium. Video signal recorder. 2. A digital high-definition video signal recording apparatus for compressing and encoding a digital high-definition video signal and recording the encoded output as a plurality of tracks on a recording medium. Means for forming the first to fourth band signals by dividing each of the two-dimensional frequency spectrum of the two-dimensional frequency signal in the horizontal and vertical directions, and a digital video whose encoded output data amount is standard definition. A first for encoding the first band signal, locally decoding the encoded output, and forming a difference signal between the locally decoded output and the input data so as to be substantially equal to that in the device for recording the signal. The data amount obtained by summing the encoding means, the differential signal, and the encoded outputs of each of the second, third, and fourth band signals is the standard definition data. A second for encoding the differential signal and the second, third and fourth band signals so that they are substantially equal to those in a device for recording a digital video signal.
And a means for recording the encoded outputs of the first and second encoding means on the recording medium. 3. The digital video signal recording device according to claim 1, wherein the first encoding means encodes the first band signal within a frame, and the second encoding means comprises second, third and A digital high-definition video signal recording device, wherein the fourth band signal is processed every two frames, and one of the two frames and the difference between the two frames are encoded. 4. The digital video signal recording apparatus according to claim 1 or 2, wherein the first encoding means is a discrete cosine transform means, a quantizing means, a variable length encoding means, and an encoded output data amount. The second encoding means comprises a quantizing means, a variable length encoding means, and an estimating means for controlling the data amount of the encoded output to the target value. A digital high-definition video signal recording device characterized by the above. 5. The digital video signal recording apparatus according to claim 4, wherein the quantizing means of the second encoding means weights the quantizing step among the signals to be quantized. Video signal recorder.