JPH06188922A - Fsk demodulating circuit - Google Patents

Abstract

PURPOSE:To provide an FSK demodulation circuit which can exist together with a digital circuit. CONSTITUTION:A pulse signal E is generated in every half period of an analog signal A as the FSK demodulation object, and the number of master clock signals CK included in this half period is counted by counters 21a and 21b. When counted values reach an average of the number of master clock signals CK included in the half period in 64 half periods of the signal A, a ripple carry signal RCP3 is outputted, and the signal RCP3 is latched in a D flip flop 22 by the pulse signal E to obtain a binarized signal J subjected to FSK demodulation. Thus, the FSK demodulating circuit can be made of a simple digital circuit, and this circuit is hardly affected by the noise even if existing together with another digital circuit, and accurate demodulation is performed regardless of the variance in frequency of the signal A due to an external factor, and this circuit can be integrated together with another digital circuit, and an unnecessary space is eliminated to miniaturize the circuit.

Description

Detailed Description of the Invention

[0001]

The present invention relates to FSK (Frequency Shrink).
ift Keying: Frequency shift keying) The present invention relates to a demodulation circuit.

[0002]

2. Description of the Related Art A recordable optical disk 1 such as a write-once optical disk (CD-WO) or a magneto-optical disk (CD-MO).
As shown in FIG. 2, the track 2 is spirally formed in the recording area in advance with a slight amplitude. The swell of this track is ATIP (Absolute T
It represents absolute time information called ime In Pregroove) data, and has 22.05 KHz as a basic frequency, and the frequency is a length corresponding to 1 bit of ATIP data (frequency 4
± 1 KHz depending on the contents of the bit every 7 cycles of 4.1 KHz), that is, whether this bit is "1" or "0"
It is FSK modulated to change.

Further, one frame of ATIP data is
The frame is composed of a large number of consecutive frames each including a constant number (84 bits) of bits and having a fixed pattern frame synchronization signal at a predetermined position, and each frame is repeated at a frequency of 75 Hz.

On the other hand, when recording information such as audio and video on the above-mentioned recordable optical disc, the number of channels of the song, the presence / absence of pre-emphasis, the song number, the time from the beginning of the song, from the innermost circumference of the disc The control information indicating the absolute time of the subcode data, that is, the subcode data is also recorded at the same time. In this subcode data, one frame has a fixed number of bits (98 bits) (however, the unit length corresponding to one bit is A
(It is different from the case of TIP data) and is composed of a number of frames consisting of a bit string having a fixed pattern frame synchronization signal at a predetermined position, and each frame is recorded at a frequency of 75 Hz.

When the information is actually recorded on the optical disk, the standard defines that the ATIP data and the subcode data should be recorded in frame synchronization. Therefore, the ATIP data is reproduced. There is a need. Therefore, when the conventional ATIP data is reproduced, the above-mentioned undulation is detected and reproduced as an analog signal (wobble signal) having a undulation period as shown in FIG. 3, and FSK using an analog PLL circuit or the like is used. The demodulation circuit was used for demodulation.

[0006]

[Problems to be Solved by the Invention] However, FSK
When an analog PLL circuit is used as the demodulation circuit, the other circuits are configured by digital circuits, and therefore must be configured separately to avoid the influence of noise and the like generated from them, and an extra space is required. It was necessary and the device could not be downsized. Furthermore, since it is easily affected by noise, the ATIP data may not be reproduced accurately.

In view of the above problems, an object of the present invention is to provide an FSK demodulation circuit that can be mixed with a digital circuit.

[0008]

In order to achieve the above object, the present invention demodulates an FSK-modulated analog signal with a predetermined reference frequency as a center frequency by a binarized signal to obtain the binarized signal. In the output FSK demodulation circuit,
The level of the FSK-modulated analog signal is compared with a predetermined threshold level, and the output signal is changed to the first level or the first level for each half cycle of the analog signal in accordance with the magnitude relationship between them. A first comparison circuit for changing to a second level different from the above, an oscillation circuit for generating a master clock signal of a predetermined frequency that is an integral multiple of the reference frequency, and a signal output from the first comparison circuit. The first
Edge detection circuit that detects a level change point that changes from the second level to the second level and a level change point that changes from the second level to the first level, and the level change point is detected by the edge detection circuit. A first counting circuit counting from the time point based on the master clock signal, and counting the number of level change points at which the signal output from the first comparison circuit changes from the second level to the first level. However, the second counter circuit that outputs a pulse signal every predetermined number and the signal that is output from the first comparison circuit are the first counter circuit.
Within the period of the pulse signal output from the second counting circuit, which counts the number of level change points that change from the level of 2 to the second level and outputs a pulse signal at every predetermined number. And a pulse signal output from the third counting circuit and a fourth counting circuit that counts the number of the master clock signals included while the output signal of the first comparing circuit is at the first level. A fifth counting circuit that counts the number of the master clock signals included in the cycle of the output signal of the first comparing circuit while the output signal of the first comparing circuit is at the second level, and the counting result of the fourth counting circuit. Based on the above, every time a pulse signal is output from the second counting circuit, the average value of the number of the master clock signals included while the output signal of the first comparing circuit is at the first level. The first average value calculation to calculate Circuit and the counting result of the fifth counting circuit, while the pulse signal is output from the third counting circuit, the output signal of the first comparing circuit is at the second level. A second average value calculating circuit for calculating an average value of the number of the master clock signals included in the first average value calculating circuit, and a calculation result by the first average value calculating circuit or the second average value calculating circuit based on the output signal of the first comparing circuit. A selection circuit for selecting one of the calculation results by the second average value calculation circuit, and a second comparison circuit for comparing the average value selected by the selection circuit with the count value of the first counting circuit,
An FSK including a binarized signal output circuit that changes the value of the binarized signal to be output based on the comparison result of the second comparison circuit when the level change point is detected by the edge detection circuit. We propose a demodulation circuit.

[0009]

According to the present invention, the oscillator circuit generates a master clock signal having a predetermined frequency which is an integral multiple of the reference frequency in the FSK modulation to be demodulated, and the level of the FSK-modulated analog signal to be demodulated is: The first comparison circuit compares with a predetermined threshold level, and the first comparison circuit outputs a first level or a second level different from the first level corresponding to the magnitude relation of these levels. The level signal changes every half cycle of the analog signal and is output. Further, the edge detection circuit allows the first
The level change point at which the signal output from the comparator circuit changes from the first level to the second level and the level change point at which the signal changes from the second level to the first level are detected. The first counting circuit starts counting based on the master clock signal from the time when the edge is detected by the edge detecting circuit. Furthermore, the number of level change points at which the signal output from the first comparison circuit changes from the second level to the first level is counted by the second counting circuit, and a pulse signal is generated every predetermined number. Is output, and the number of level change points at which the signal output from the first comparison circuit changes from the first level to the second level is counted by the third counting circuit, and at the same time every predetermined number. A pulse signal is output. The number of the master clock signals included in the period of the pulse signal output from the second counting circuit and while the output signal of the first comparing circuit is at the first level is the fourth counting number. Within the period of the pulse signal counted by the circuit and output from the third counting circuit, and the output signal of the first comparing circuit is the second signal.
The number of the master clock signals included during the level of is counted by the fifth counting circuit. Also, every time a pulse signal is output from the second counting circuit, the first
The average value calculation circuit of the first counting circuit is within the period of the pulse signal output from the second counting circuit based on the counting result of the fourth counting circuit and the output signal of the first comparing circuit is An average value of the number of the master clock signals included in the level is calculated, and the second average value calculation circuit outputs the average value from the third counting circuit based on the counting result of the fifth counting circuit. The average value of the number of the master clock signals included in the period of the pulse signal and while the output signal of the first comparison circuit is at the second level is calculated. As a result, when the reference frequency of the FSK-modulated analog signal fluctuates due to some external factor, the comparison reference value in the second comparison circuit corresponds to the first reference frequency fluctuation.
Is corrected for each level of the output signal of the comparator circuit. Also,
The selection circuit selects one of the average values calculated by the first and second average value calculation circuits based on the output signal of the first comparison circuit, and the selected average value is the second average value. The comparison circuit sets the comparison reference value and the comparison reference value is compared with the count value of the first counting circuit. Thereby, the frequency shift direction in FSK modulation, that is, whether the frequency of the analog signal is increasing or decreasing with respect to the reference frequency is detected. Further, when an edge is detected by the edge detection circuit, the binarized signal output circuit outputs a binarized signal having a value based on the comparison result of the second comparison circuit, and F
SK demodulation is completed.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an FSK demodulation circuit according to an embodiment. In the figure, 10 is an oscillating circuit for generating a square-wave master clock signal CK, 11 is a comparator composed of an operational amplifier, 12a and 12b are D flip-flops, and 13
a to 13e are NOT circuits, 14 is an exclusive OR circuit (hereinafter referred to as EXOR circuit), 15 is a 2-input AND circuit, 16 is a 2-input NOR circuit, and 17a and 17b are counters such as 74HC163. Every time the count value is 64 in the serially connected counting circuit, a ripple carry signal of one clock width is output and reset. 18a and 18b are 16-bit counting circuits made up of 74HC163, 19a and 19b are 8-bit input / output D flip-flops with chip enable terminals, 20 is an 8-bit selector, 21a and 21b are counters such as 74HC163, and 22 is It is a D flip-flop with a chip enable terminal.

An FSK-modulated analog signal (hereinafter referred to as a wobble signal) A to be demodulated is input to the non-inverting input terminal of the comparator 11, and the maximum value of the level of the wobble signal A is input to the inverting input terminal. The threshold voltage Vth at the level of the minimum value is applied. In addition, the comparator 11
Is connected to the input terminal of the D flip-flop 12a, and the output terminal of the D flip-flop 12a is connected to one of the input terminals of the EXOR circuit 14, the AND circuit 15, and the NOR circuit 16 and the input terminal of the D flip-flop 12b. Has been done. The output terminal of the D flip-flop 12b is connected to the other input terminal of each of the EXOR circuit, the AND circuit 15 and the NOR circuit 16 via the NOT circuit 13a, and the master terminal is connected to the clock signal input terminal CLK of the D flip-flops 12a and 12b. The clock signal CK is input.

The count circuit 17a is, for example, a well-known 74.
Two HC 163 are connected in series to form eight, and the number of pulse signals F output from the AND circuit 15 is counted based on the master clock signal CK, and the count value of the pulse signals F is a ripple of one clock width for every 64 bits. The carry signal RCP1 is output. That is, the value "192" is set to the data input terminal of the count circuit 17a, and the master clock signal C is input to the clock signal input terminal CLK.
K is input, and the enable terminal ET is connected to the output terminal of the AND circuit 15. As a result, the counting circuit 17a counts the number of pulse signals F output from the AND circuit 15 in synchronization with the master clock signal CK, and outputs a ripple carry signal RCP1 consisting of a positive pulse having a one-clock width every 64 counts. .

Similarly, the count circuit 17b is composed of, for example, two well-known 74HC163s connected in series to form eight, and the NOR circuit 1 is based on the master clock signal CK.
The number of pulse signals G output from 6 is counted, and a ripple carry signal RCP2 having a count value of the pulse signal G of 1 clock width is output every 64 bits. That is, the value “192” is set to the data input terminal of the count circuit 17b, the master clock signal CK is input to the clock signal input terminal CLK, and the enable terminal ET is NO.
It is connected to the output terminal of the R circuit 16. This allows
The counting circuit 17b counts the number of pulse signals G output from the NOR circuit 16 in synchronization with the master clock signal CK, and outputs a ripple carry signal RCP2 consisting of a positive pulse having a one-clock width every 64 counts.

The counting circuit 18a includes, for example, four 74
The HC 163 is configured by being connected in series, and from the time when the ripple carry signal RCP1 of the count circuit 17a is input based on the master clock signal CK to the time when the next ripple carry signal RCP1 is input, and the output signal of the D flip-flop 12a. Count the number of master clock signals CK while C is high. That is, the ripple carry signal RCP1 is input to the clear terminal CLR of the count circuit 18a via the NOT circuit 13b, the master clock signal CK is input to the clock signal input terminal CLK, and the enable terminal EP of the D flip-flop 12a. The output signal C is input.

The counting circuit 18b is a counting circuit 18
As in the case of a, for example, four 74HC163 are connected in series, and between the time when the ripple carry signal RCP2 of the count circuit 17b is input based on the master clock signal CK and the time when the next ripple carry signal RCP2 is input. Moreover, the number of master clock signals CK while the output signal C of the D flip-flop 12a is low level is counted. That is, the clear terminal C of the counting circuit 18b
The ripple carry signal RCP2 is input to the LR via the NOT circuit 13c, the master clock signal CK is input to the clock signal input terminal CLK, and the output signal of the D flip-flop 12a is input to the enable terminal EP via the NOT circuit 13d. C has been entered.

8-bit input / output D flip-flop 19a
Is the ripple carry signal RC from the counting circuit 17a.
When P1 is output, the count value of the count circuit 18a is divided by 64 and the complement of this value is output. That is, each of the data input terminals D1 to D8 of the D flip-flop 19a is the seventh bit Qg counted from the LSB of the 16-bit data output terminals Qa to Qp of the counting circuit 18a.
To the 14th bit Qn, the input data is inverted and output. The master clock signal CK is input to the clock signal input terminal CLK of the D flip-flop 19a, the chip enable terminal CE is connected to the output terminal of the NOT circuit 13b, and the ripple carry signal RCP1 is inverted to the chip enable terminal CE. A signal is being input.

8-bit input / output D flip-flop 19b
Is the ripple carry signal RC from the counting circuit 17b.
When P2 is output, the count value of the count circuit 18b is divided by 64, and the complement of this value is output. That is, each of the data input terminals D1 to D8 of the D flip-flop 19b is the seventh bit Qg counted from the LSB of the 16-bit data output terminals Qa to Qp of the count circuit 18b.
To the 14th bit Qn, the input data is inverted and output. The master clock signal CK is input to the clock signal input terminal CLK of the D flip-flop 19b, the chip enable terminal CE is connected to the output terminal of the NOT circuit 13c, and the ripple carry signal RCP2 is inverted to the chip enable terminal CE. A signal is being input.

The selector 20 includes a D flip-flop 19
8-bit data D output from each of a and 19b
A1 and DA2 are input and either one of these data DA1 and DA2 is output based on the output signal C of the D flip-flop 12a. That is, the D flip-flop 1 is connected to one 8-bit data input terminal IA of the selector 18.
The output data DA1 of 9a is input, the output data DA2 of the D flip-flop 19b is input to the other 8-bit data input terminal IB, and the output signal C of the D flip-flop 12a is input to the select signal input terminal SE. The data DA2 is output to the 8-bit data output terminal Y when the signal C is at low level, and the data DA1 is output when the signal C is at high level.

The data input terminals Da to Dd of the counters 21a and 21b are connected to the output terminals Y1 to Y8 of the corresponding selector 18, respectively. In addition, the counter 21
a and 21b are connected in series to form a master clock signal CK
Counting is performed and the data of the input terminals Da to Dd is loaded when the output signal E of the EXOR circuit 14 is at a low level. That is, the counter 21a,
The clock input terminal of 21b has a master clock signal C
K is the EXOR circuit 1 at the load signal input terminal LD.
4 output signals E are input, and the ripple carry output terminal RC of the counter 21a is connected to one enable terminal ET of the counter 21b. Further, the counter 21b ripple carry output terminal RC is connected to the other enable terminal EP of the counters 21a and 21b via the NOT circuit 13e, and the other enable terminal ET of the counter 21a is pulled up to a high level and is always set to the operating state. Has been done.

The data input terminal of the D flip-flop 22 is connected to the ripple carry output terminal RC of the counter 21b, and the chip enable terminal CE has EXO.
The output signal E of the R circuit 14 and the master clock signal CK are input to the clock signal input terminal CLK, respectively.

Next, the operation of this embodiment having the above-mentioned structure will be described with reference to the timing chart shown in FIG. Here, the FSK demodulation in the process of reproducing the ATIP data from the track formed on the optical disk as described in the conventional example will be described. In this case, oscillator 1
The frequency of the master clock signal CK output from 0 is a frequency of the undulation of the track at the time of normal information reproduction from the optical disk, that is, a frequency sufficient to detect the frequency change of the undulation at an integral multiple of 22.05 KHz, For example, it is set to 8.4672MHz.

The wobble signal A input to the comparator 11
Is obtained from a track formed on the optical disc through an optical pickup (not shown), has the frequency of the swell of the track, and is FSK-modulated. The voltage Va of the wobble signal A is compared with the threshold voltage Vth by the comparator 11, and the output signal B of the comparator 11 becomes high level when the value of the voltage Va is larger than the value of the voltage Vth, and when it is small. Goes low and comparator 11
Of the wobble signal A is inverted every half cycle of the wobble signal A.

The signal B output from the comparator 11 is supplied to the master clock signal C by the D flip-flop 12a.
After being changed to the signal C synchronized with K, the signal C is changed to the signal D delayed by one clock by the D flip-flop 12b. The signal D is inverted by the NOT circuit 13a, converted into a signal D ′, and input to the EXOR circuit 14. The EXOR circuit 14 exclusive-ORs the signal C and the signal D ′ and outputs the signal E. As a result, both the edge point of the signal B, that is, the change point from the high level to the low level and the change point from the low level to the high level are detected, and when they are detected, the one clock width synchronized with the master clock signal CK is detected. The negative pulse signal E is output.
The signal C and the signal D ′ are input to the AND circuit 15 and the NOR circuit 16, respectively. As a result, the AND circuit 15 detects a transition point at which the signal B changes from the low level to the high level, and when detected, outputs a positive pulse signal F having a one-clock width in synchronization with the master clock signal CK. Further, the NOR circuit 16 detects a transition point where the signal B changes from high level to low level, and when detected, outputs a positive pulse signal G having a one-clock width in synchronization with the master clock signal CK.

In the counting circuit 17a, as described above, the number of pulse signals F is counted, and every time the number of input pulse signals F becomes 64, a ripple composed of a positive pulse signal of one clock width. Carry signal RCP1
Is output, and the counting circuit 17b counts the number of pulse signals G as described above, and each time the number of input pulse signals G becomes 64, a positive pulse signal of one clock width is formed. Ripple carry signal RCP2
Is output.

In the count circuit 18a, the master clock signal is input from the time when the ripple carry signal RCP1 is input to the time when the next ripple carry signal RCP1 is input and the output signal C of the D flip-flop 12a is at the high level. The number of signals CK is counted. Further, in the count circuit 18b, the master clock signal CK of the D flip-flop 12a during the period from the input of the ripple carry signal RCP2 to the input of the next ripple carry signal RCP2 and the output signal C of the D flip-flop 12a is at the low level. The number is counted.

On the other hand, the data input to the 8-bit input / output D flip-flop 19a is 1 of the count circuit 18a.
Of the 6-bit output, it is 8 bits that are shifted 6 bits higher from the LSB, so the value is the count circuit 18a.
The value of the 16-bit output data is 1/64, and the master clock signal C is included in the 128 half cycles of the wobble signal A and in the 64 half cycles where the signal C is at the high level.
The average value of the number of K will be input. Similarly, since the data input to the 8-bit input / output D flip-flop 19b is 8 bits which are shifted 6 bits higher from the LSB in the 16-bit output of the counting circuit 18b, the value thereof is stored in the counting circuit 18b. The value becomes 1/64 of the value of 12-bit output data, and the value of 12 of wobble signal A
The average value of the number of master clock signals CK included in the 64 half cycles in which the signal C is at the low level within the 8 half cycles is input. Further, when the ripple carry signal RCP1 is output from the count circuit 17a, the input data is latched to the D flip-flop 19a, and when the ripple carry signal RCP2 is output from the count circuit 17b, the input data is latched to the D flip-flop 19b. To be done.

Further, the EXOR circuit 14 outputs a pulse signal E.
Is output, the counter 2 is generated by the pulse signal E.
The output data of the selector 20 is loaded into each of 1a and 21b. Here, the output data of the selector 20 is the output data DA of the D flip-flop 19b when the output signal C of the D flip-flop 12a is at the low level.
2, and when the output signal C of the D flip-flop 12a is at high level, it is the output data DA1 of the D flip-flop 19a. Further, the output data of the selector 20 is a complement of the number of the master clock signal CK included in the half cycle of the reference frequency in the waviness of the track when the rotation of the optical disc is normal. That is, since the swell reference frequency is 22.05 KHz and the frequency of the master clock signal CK is 8.4672 MHz, the number of master clock signals CK included in a half cycle of the reference frequency is 192 as shown in the following equation.

(8.4672 × 10 ⁶ ) ÷ (22.05 × 10 ³ ) ÷ 2 = 192 Further, when the count number of the counters 21a and 21b becomes 192 or more, a high level pulse is output from the ripple carry output terminal RC of the counter 21b. In order to output the signal, the output data of each of the D flip-flops 19a and 19b is the inversion of the input data.

Counters 21a, 2 are generated by the pulse signal E.
After the output data of the selector 20 is set as an initial value for each of the 1b, the counts of the counters 21a and 21b are advanced, and when the count value is equal to or more than a half cycle of the swelling reference frequency, a ripple carry composed of a positive pulse signal. When the signal RCP3 is output, the EXOR circuit 14 outputs the next pulse signal E, and the low-level signal is input to the chip enable terminal CE of the D flip-flop 22, the value of the ripple carry signal RCP3, that is, the high level. The level or low level is latched in the D flip-flop 22 and the binarized signal J having this value is output.
Therefore, when the length of the half cycle of the wobble signal A is more than the half cycle of the reference frequency of 22.05 KHz, the high level signal J is output from the D flip-flop 22 with a delay of half cycle, and the half cycle of the wobble signal A is long. The reference frequency is 22.05KHz
When it is shorter than the half cycle of, the D flip-flop 22 outputs the low-level signal J with a delay of half cycle. As a result, FSK demodulation is performed.

Here, the ripple carry signal RCP3
Keeps the high level until the next pulse signal E is output. Therefore, the fluctuation of the output time of the pulse signal E due to the frequency change of the FSK modulation, that is, the ripple carry signal RCP.
It is possible to sufficiently deal with the fluctuation of time from the time when 3 becomes high level to the time when the pulse signal E is output.

Further, even if the frequency of the wobble signal A fluctuates greatly due to uneven rotation or speed deviation of the optical disk due to some external factor, a reference value for outputting the ripple carry signal RCP3 as shown in FIG. That is, since the average value data DA1 and DA2 obtained by the count circuits 18a and 18b and the D flip-flops 19a and 19b are corrected every 128 half cycles of the wobble signal A, accurate FSK demodulation can always be performed.

Further, by the counting circuit 18a and the D flip-flop 19a, within the 128 half cycles and D
When the output signal C of the flip-flop 12a is at a high level, an average value is calculated, and when the output signal C of the D flip-flop 12a is at a low level within the 128 half cycle by the count circuit 18b and the D flip-flop 19b. When the duty ratio of the signal B does not reach 50% due to the level fluctuation of the wobble signal A or the like, the average values of the wobble signal A are selectively loaded into the counters 21a and 21b and used as comparison reference values. However, corresponding to this, the above-mentioned comparison reference value is set and accurate FSK
Demodulation can be performed.

As described above, according to this embodiment, the FSK
Since the demodulation circuit is composed of a digital circuit, it is not easily affected by noise even when mixed with other digital circuits, and the cycle length is compared with a reference value every half cycle of the FSK-modulated wobble signal A. Therefore, accurate demodulation can be performed. Further, even when the frequency of the wobble signal A fluctuates greatly due to external factors, accurate demodulation can always be performed. Furthermore, since it can be integrated with other digital circuits and does not require an extra space, the device can be made compact.

When information processing is performed by changing the number of revolutions of the optical disk, the frequency of the master clock signal CK is corresponding to the number of revolutions, that is, the change in the frequency of the waviness due to the change in the number of revolutions. Should be changed. For example, when the information processing is performed by doubling the rotation speed of the optical disk, the frequency of the master clock signal CK may be doubled. Such frequency switching of the master clock signal CK can be easily performed by using a higher-frequency oscillator and a frequency divider.

The circuit configuration of this embodiment is an example, and the present invention is not limited to this. For example, in the present embodiment, the master clock signal C included in the half cycle of the wobble signal A
The counters 21a and 21b are provided with the function of counting the number of K and the function of comparing the count value with the reference value.
A comparison circuit may be provided separately from a and 21b, and the count value of the counters 21a and 21b and the reference value may be compared by this comparison circuit. Furthermore, a divider may be separately provided as a circuit for obtaining the average value.

[0036]

As described above, according to the present invention, F
The counter circuit counts the number of master clock signals included in the half cycle of the analog signal to be SK demodulated, and the count value and the number of the master clock signals included in the half cycle of the FSK modulation reference frequency Since the digital comparison is performed by the second comparison circuit and the increase / decrease in the frequency of the analog signal is identified based on the comparison result and the FSK demodulation is performed, it can be configured by a simple digital circuit and mixed with other digital circuits. Even if it is done, it is hardly affected by noise, and accurate demodulation can be performed. Furthermore, since it can be integrated with other digital circuits and does not require an extra space, the device can be made compact. Furthermore, the average value of the number of the master clocks in the half cycle of the analog signal by the second to fifth counting circuits and the first and second average value calculation circuits within a predetermined multiple of the half cycle of the analog signal. Is calculated for each level of the output signal of the first comparison circuit and the increase / decrease of the frequency of the analog signal is discriminated based on the average value. Therefore, the reference of the analog signal modulated by the FSK by some external factor. It is possible to perform accurate FSK demodulation even when the frequency fluctuates, and the first
This has an extremely excellent effect that accurate FSK demodulation can be performed even when the duty ratio of the output signal of the comparator circuit is not 50%.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating tracks formed on an optical disc.

FIG. 3 is a waveform diagram showing an FSK-modulated analog signal.

FIG. 4 is a timing chart illustrating the operation of the embodiment of the present invention.

FIG. 5 is a diagram illustrating the relationship between the frequency of a wobble signal and average value data in one embodiment.

[Explanation of symbols]

10 ... Oscillator, 11 ... Comparator, 12a, 12b ... D flip-flop, 13a-13e ... NOT circuit, 14 ... Exclusive OR circuit, 15 ... AND circuit, 16 ... NOR circuit, 17a, 17b ... Count circuit, 18a , 18b ...
Counting circuits, 19a, 19b ... D flip-flops,
20 ... Selector, 21a, 21b ... Counter, 22 ... D
flip flop.

Claims (1)

[Claims] 1. A level of the FSK-modulated analog signal in an FSK demodulation circuit that demodulates an FSK-modulated analog signal with a predetermined reference frequency as a center frequency by a binarized signal and outputs the binarized signal. And a predetermined threshold level are compared with each other, and the output signal is changed to a first level or a second level different from the first level for each half cycle of the analog signal in accordance with the magnitude relationship. A first comparison circuit for generating a master clock signal having a predetermined frequency that is an integral multiple of the reference frequency; and a signal output from the first comparison circuit from the first level to the second level. An edge detection circuit that detects a level change point that changes to a level and a level change point that changes from a second level to a first level; and a level change by the edge detection circuit. And a level change point at which the signal output from the first comparison circuit changes from the second level to the first level from the time when the signal is detected, based on the master clock signal. Second counting circuit that counts the number of pulses and outputs a pulse signal every predetermined number, and a level change point at which the signal output from the first comparison circuit changes from the first level to the second level. Of the pulse signal output from the second counting circuit and the output signal of the first comparing circuit within the period of the pulse signal output from the second counting circuit. A fourth counting circuit for counting the number of the master clock signals included while being at a level of 1, and an output of the first comparing circuit within the period of the pulse signal output from the third counting circuit The signal is at the second level A fifth counting circuit that counts the number of the master clock signals included in between, and each time a pulse signal is output from the second counting circuit based on the counting result of the fourth counting circuit, A first average value calculating circuit for calculating an average value of the number of the master clock signals included while the output signal of the first comparing circuit is at the first level; and a counting result of the fifth counting circuit. Based on the above, every time a pulse signal is output from the third counting circuit, the average value of the number of the master clock signals included while the output signal of the first comparing circuit is at the second level. A calculation result by the first average value calculation circuit or a calculation result by the second average value calculation circuit, based on the output signal of the second average value calculation circuit Selection times to select or A second comparison circuit for comparing the average value selected by the selection circuit with the count value of the first counting circuit; and a second comparison circuit for detecting a level change point by the edge detection circuit. An FSK demodulation circuit, comprising: a binarized signal output circuit that changes the value of the binarized signal to be output based on the comparison result of the second comparison circuit.