JPH06188862A - Information bit series transmission system - Google Patents

Abstract

PURPOSE:To provide an information bit series transmission system for realizing more efficient error correction decoding while suppressing the increase of the probability of error correction at the time of transmitting an information bit series. CONSTITUTION:In coding and decoding techniques in this information bit series transmission system, a CRC error detection code processing 41 is performed to the information bit series A and its processing result is BCH code processed 43 and transmitted to a transmission part 45. The random error correction decoding processing 47 of cyclic codes and a burst error correction decoding processing 48 are performed to a code series received by the transmission part 45. The processing result is CRC error detection decoding processed 50.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information bit sequence transmission system, typically a mobile radio system such as a digital car telephone system or a mobile telephone system.

[0002]

2. Description of the Related Art One of the information systems in which random errors and burst errors frequently occur is a mobile radio system such as a digital car telephone system or a mobile telephone system. In such a transmission system, random errors and burst errors coexist frequently on the transmission path. In such a transmission system, it is difficult to realize efficient error correction only by random error correction decoding. For this reason, in this type of transmission system, a technique of using bit interleaving and a random error correction code together may be applied in order to realize efficient error correction.

On the other hand, the cyclic code has a property that a sequence obtained by cyclically replacing a certain code word is also a code word. Mabey proposes an attempt to apply burst error correction decoding to this type of transmission system by utilizing the property of this cyclic code ("Mobile Digital Transmission with
Soft Decision Decoding ", IEEE Veh.Tech.Conf., 198
5, pp197-199). The Mabey burst error correction decoding technique uses reliability information obtained from the receiver. That is, using the reliability information obtained from this receiver, the cyclically continuous k bits having the highest reliability are extracted from the received word. The transmission sequence is reproduced by encoding the extracted k bits. However, the burst error correction decoding technique proposed by Mabey is based on the assumption that there is no error in cyclically continuous k bits with the highest reliability.

Further, in the above-described technique of using the bit interleave and the random error correction code together, the burst error is randomized by making the bit interleave length sufficiently long. Therefore, it is possible to achieve the effective random error correction code by applying the technique of using the bit interleave and the random error correction code together to this type of transmission system.

[0005]

However, the above-described technique of using the bit interleave and the random error correction code together cannot satisfy both the error correction capability and the reduction of the delay time at the same time. This is because it is necessary to make the bit interleave length sufficiently long in order to exert a high error correction capability, which makes it impossible to expect a reduction in delay time. Therefore, applying this technique to a mobile radio system such as a digital car telephone system or a mobile telephone system has the following drawbacks. That is, in this type of mobile radio system,
The signals transmitted and received are composed of control signals and audio signals.
Among the control signal and the non-control signal (voice signal), particularly for the control signal for controlling various controls such as line connection, the transmission / reception delay time between the transmitting side and the receiving side should be shortened as much as possible. In the two-way communication, if the transmission / reception delay time of the non-control signal (voice signal) increases, the conversation becomes delayed and the tempo becomes slow. Therefore,
The transmission / reception delay time of the control signal and / or the non-control signal (audio signal) is required to be shortened as much as possible. Therefore, even if the technique is capable of exhibiting a high error correction capability, the above technique, which cannot reduce the delay time, is not preferable for this type of mobile radio system. On the contrary, if the bit interleave length is suppressed to about several tens of ms in order to shorten the delay time, the burst error cannot be sufficiently randomized,
Therefore, the random error correction code capability of the above technique cannot be utilized efficiently, which is not preferable for this type of mobile radio system. .

Further, the above-mentioned burst error correction decoding technique proposed by Mabey is based on the premise that there is no error in cyclically continuous k bits having the highest reliability, and therefore, there is no code error in these k bits. If it exists, it will be erroneously corrected (erroneous correction). That is, the above-mentioned technique proposed by Mabey has a drawback that the probability of error correction increases because burst error correction is performed using only reliability information. Further, the above-described burst error correction decoding technique proposed by Mabey can correct an error when the code includes only one burst error. However, when a plurality of burst errors and / or random errors are mixed in the code, it is difficult to correct the errors. In particular, in a transmission path of a mobile radio system, random errors and burst errors coexist, and a plurality of errors exist in the same code, so it is difficult to correct the errors only by burst error correction decoding. .

Therefore, an object of the present invention is to provide an information bit sequence transmission system transmission which realizes more efficient error correction decoding while suppressing an increase in the probability of error correction when transmitting an information bit sequence. .

[0008]

In order to achieve the above object, an information bit series transmission system according to the present invention comprises an information bit and a redundant bit for error detection coding.
An error detection coding unit that performs error detection coding on the information bit sequence given as the A sequence in order to generate the sequence _;
To generate a sequence (i = 1 to k, bit length n _{i of} each sequence), a division unit that divides the B sequence into k pieces, and a cyclic code for each of the B _i sequences to generate a C _i sequence. In order to generate the D series and the error correction code part for error correction coding of
An interleaving unit that interleaves the C _i sequence, a transmission unit that transmits the D sequence to a predetermined transmission line, and an E sequence corresponding to the D sequence received from the transmission line to generate an E _i sequence. De-interleaving section and dividing section for de-interleaving and dividing the de-interleaved series into k pieces corresponding to the cyclic code, F _{i, 1} series (bit length n _{i of} each series ₎ )
To generate a random error correction code unit for cyclic error code encoding of the cyclic code for each E _i sequence, and H
_In order to generate an _{i, J (i)} sequence (bit length n _{i of} each sequence),
A burst error correction decoding unit for decoding each of the E _i sequences for burst error correction of a cyclic code, the F _{i, 1} sequence and H
The first decoding candidate J corresponding to the B _i sequence is selected by selecting one from the total (1 + j (i)) of _{i, 1} , H _{i, 2 to} H _{i, j (i)} sequences. _i is generated, and the first decoding candidate J _i is combined to generate the second decoding candidate I _l (l = 1 to k, the maximum of k is Π _{i, (1 + j (i)).} (i = 1 to k)), and the second decoding candidate I _l is _subjected to error detection decoding to generate a decoding result of the information bit sequence corresponding to the A sequence, and a final decoding means.

In order to achieve the above object, in the information bit sequence transmission system according to the present invention, the random error correction decoding unit in the system uses soft decision decoding using reliability information obtained at the receiving side. Accordingly, F _{i, 1} and F _{i, 2 are set} as decoding candidates for the respective E _i series.
Comprises means for generating a ~F _{i, f (i)} sequences, the burst error correction decoding unit in the system, and n _i consecutive bits cyclically in the E _i series, the reliability of the E _i series H _{i, 1} , H _{i, 2 to} F _{i, j2 (i)} sequences are generated by using the cyclic polynomial generating polynomial with the newly obtained n _i bit sequence by inverting relatively low bits. The combining unit in the system generates (f (i) + j2 (i)) decoding candidates corresponding to the E _i sequence, and (f (i) + j2 (i)) ) Decoding candidates I j _(i) are selected, the decoding candidate I _l corresponding to the B sequence is selected.
(L = 1 to k, the maximum of k is Π _{i, j3 (i )} (i = 1 to k)), and the CRC code error detection decoding unit and maximum likelihood decoding selection unit are As a result of error detection and decoding of the candidate I _l , when there is only one decoding candidate determined to be error-free, the decoding candidate is selected as the decoding result of the information bit sequence, and the decoding candidate determined to be error-free is selected. In the case where there are a plurality of items, there is included means for comparing the reliability of the decoding candidates and selecting the highest decoding candidate as the decoding result of the information bit sequence of the A sequence.

Further, in order to achieve the above object, the information bit sequence transmission system according to the present invention is provided as an A sequence in order to generate a B sequence consisting of information bits and redundant bits for error detection coding. An error detection coding unit that performs error detection coding on the information bit sequence, and a B _i sequence (i = 1
~ K, to generate the bit length n _i ) of each sequence
A dividing unit for dividing the sequence into k, to generate a C _i sequence, an error correction code unit for error correction coding of the cyclic code to people the B _i line respectively, to generate a D sequence, the C _i line An interleaving section for interleaving
A transmission unit for transmitting the D sequence to a predetermined transmission path and an E sequence corresponding to the D sequence received from the transmission path are de-interleaved to generate an E _i sequence, and the de-interleaved A de-interleaving unit and a dividing unit that divide a sequence into k pieces corresponding to the cyclic code, and a F _{i, f4 (i)} sequence that is a random error correction decoding candidate corresponding to the B _i sequence (i = 1 ~ K, bit length n of each sequence
a random error correction decoding unit that performs random error correction decoding of a cyclic code on each of the E _i sequences to generate _i );
Burst error correction decoding candidates corresponding to the B _i sequence, H _{i, j4 (i)} sequence (i = 1 to k, bit length n _{i of} each sequence)
To generate each of the E _i sequences, a burst error correction decoding unit that performs burst error correction decoding of a cyclic code on each E _i sequence, and the number of random error correction decoding candidates in the F _i sequence generated by the random error correction decoding unit is f _{4 ( i)} (i = 1 to k), and the number of candidates for burst error correction decoding in the H _i sequence generated by the burst error correction decoding unit is j _{4 (i)} (i =
1 to k), an I _Ko sequence is constructed using the F _i (i = 1 to k), CRC error correction decoding is performed on this I _Ko sequence, and redundant bits of this decoded sequence A first processing unit that stores R _o , all the information bits other than the i-th information bit in the CRC error correction decoded sequence is set to zero, and the i-th information bit in the CRC error correction decoded sequence is C _i.
Configure I _K sequence by performing an exclusive OR processing for each bit of the decoded candidates and the F _i sequence corresponding to sequence, the I _K
CRC error correction decoding is performed on the sequence, and the decoded redundant bits R _{i, j (i)} (i = 1 to k, j (i) = 1 to (f4 (i) + j4 (i) -1)).
), A third processing unit that applies the following logical processing to all combinations of the decoding candidates and determines that the result of this logical processing becomes zero, and R _o ^ER R
_{1, J (i)} ^ER R _{2, J (i)} ^ER R _{3, J (i)} to ^ER R _{k, J (i)} (where ^ER represents an exclusive OR for each bit) R _o Alternatively, when the result of the logical processing is zero, the result of the exclusive-OR processing of the I _ko and the I _k is a fourth decoding unit that determines that the final decoding result does not include an error. It is equipped with.

[0011]

According to the present invention, the information bit sequence is subjected to error detection coding processing by the CRC code or the like on the transmitting side, and then error correction coding is performed by the cyclic code and transmitted to the transmission line. A random error correction decoding process for a cyclic code and a burst error correction decoding process are applied at the same time, and a CRC is applied to the decoding result obtained as a result.
A final decoding result is obtained by performing error detection check using a code or the like. According to the series of processes, basically, the random error correction decoding process and the burst error correction decoding process of the cyclic code are performed as much as possible, and the powerful CR is used for the purpose of reducing the error miss which increases at this time.
Since error detection and decoding such as C coding is also used, when applied to a transmission line in which random errors and burst errors are mixed such as a mobile radio system, efficient error correction is realized and the error miss rate is Can be kept small.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A mobile radio system to which the present invention is applied can be roughly understood by referring to FIG. Figure 1
As shown in FIG. 1, the mobile network 10 includes a control station 11 and a base station 1.
It is defined by the base station side equipment consisting of two, the transmission line, and the mobile station side equipment (the mobile station 13 such as a mobile phone). Mobile network 10 is typically connected to a fixed network 14, such as a general subscriber telephone network. Mutual communication is performed between the base station 11 and the mobile station 13 via a wireless transmission line which is an antenna. Communication between one mobile station and another mobile station, or between one mobile station and a fixed-line general subscriber telephone, is performed between the mobile station and communication of ground equipment consisting of a control station and a base station. It is done by sending and receiving signals. In a mobile radio system typified by such a mobile telephone system, low delay transmission (shortening of delay time) and high precision transmission of an information bit sequence are required. The present invention is
A low delay transmission (shortening of delay time) and a high precision transmission of an information bit sequence signal are achieved by using a coding / decoding technique.

As shown in FIG. 2, in the mobile radio system to which the present invention is applied, the base station side equipment and the transmission line 2 are used.
3 and equipment on the mobile station side are defined. The base station equipment is
Encoder 20, transmitter 21, antenna 22, receiver 29,
A decoder 30 is included. The mobile station side equipment includes an antenna 24, a receiver 25, a decoder 26, an encoder 27, and a transmitter 28. Then, the signal transmission from the base station side to the mobile station side is achieved by the path 31, and the signal transmission from the mobile station side to the base station side is achieved by the path 32. And the route 31
Regardless of which path or path 32 is formed, in this system, encoding / decoding of an information bit sequence, wireless transmission, and encoding / decoding are performed reversibly.

The system of the first embodiment of the present invention shown in FIG. 3 is a system for transmitting an information bit sequence (52 bits) as an A sequence using a coding / decoding technique.
0 (or 27), a wireless transmission unit 45 (transmitter 21, antenna 22, transmission path 23, antenna 24, receiver 25, transmitter 28, receiver 29) and a decoder 26 (or 30). .

Encoder 20 in the system of the first embodiment
(Or 27) is a CRC encoding unit 41, a dividing unit 42,
The BCH coding unit 43 and the interleaving unit 44 are included. Also, the decoder 26 (or 37) includes a de-interleaving unit and division unit 26, a random error correction decoding unit 47, a burst error correction decoding unit 48, and a combining unit 49.
And a CRC error detection decoding unit 50 and a selection unit 51.

Each part of the system of the first embodiment will be described in detail below. First, the encoder 20 (or 27) will be described. That is, the error detection coding unit 41 CRC-codes the information bit sequence given as the A sequence in order to generate a B sequence consisting of information bits and redundant bits for error detection coding. The dividing unit 42 divides the B _i sequence (i = 1 to k
, The B-sequence is divided into k in order to generate the bit length n _i ) of each sequence. The BCH encoding section BCH-encodes each B _i sequence in order to generate a C _i sequence. The interleaving unit 44 interleaves the C _i sequence to generate the D sequence.

The transmission unit 45 is a radio transmission unit for a mobile radio system.

Next, the decoder 26 (or 37) will be described. That is, the de-interleaving unit 46 is
The D received from the transmission line to generate an E _i sequence
The E sequence corresponding to the sequence is de-interleaved, and the sequence obtained by this is divided into k corresponding to the cyclic code. The random error correction coding unit 47 performs random error correction coding of a cyclic code on each of the E _i series in order to generate the F _{i, 1} series (bit length n _{i of} each series).

The burst error correction decoding unit 48 uses H _{i, j (i)}
To generate a sequence (bit length n _{i of} each sequence), the E
_{Each i-} sequence is subjected to burst error correction decoding of a cyclic code.
Here, the burst error correction decoding unit 48 applies a process of selecting n _i bits which are cyclically continuous from each of the E _i sequences and applies the cyclic code generation polynomial to the selected bits. To generate an E1 _i sequence and
The 1 _i sequence is cyclically shifted and n _i corresponding to the B _i sequence is _generated.
The process of generating the E2 _i series of bits is repeated by sequentially changing the bit positions to generate the H _{i, j (i)} (i = 1 to k) series corresponding to the series E _i .

Here, H _i is defined as a set of the following series.

H ₁ = {H _1,1 , H _{1,2 to} H _{1, j (1)} } H ₂ = {H _2,1 , H _{2,2 to} H _{2, j (2)} } H ₃ = {H _3,1 , H _{3,2 to} H _{3, j (3)} } …………………… H _k = {H _{k, 1} , H _{k, 2 to} H _{k, j (k)} } final The decoding unit includes a combining unit 49, a CRC code error detection decoding unit 50, and a maximum likelihood decoding selection unit 51. By the combining unit 49 and the maximum likelihood decoding selecting unit 51, the F
The sum of the _{i, 1} sequence and the H _{i, 1} , H _{i, 2 to} H _{i, j (i)} sequence (1 + j
(i)) number of selects one sequence from generating a first decoded candidates J _i corresponding to the B _i line, the B the first decoded candidates J _i in combination as shown in FIG. 15 The second decoding candidate I _l corresponding to the sequence (l = 1 to k, the maximum of k is Π _{i, (1 + j (i))}
(i = 1 ~ k)) is generated. The CRC code error detection decoding section, CRC said second decoded candidates I _l and error detection decoding, from the no error is detected the second decoding candidates I _l
The sequence excluding the redundant bits of is adopted as the decoding result of the information bit sequence corresponding to the A sequence.

The random error correction decoding unit 47 uses the soft decision decoding using the reliability information obtained at the receiving side to determine the F _i sequence as f (i) as a decoding candidate for each E _i sequence. A means for generating (F _{i, 1} , F _{i, 2 to} F _{i, f (i)} ) pieces is included.

Here, F _i is defined as a set of the following series.

F ₁ = {F _1,1 , F _{1,2 to} F _{1, f (1)} } F ₂ = {F _2,1 , F _{2,2 to} F _{2, f (2)} } F ₃ = {F _3,1 , F _{3,2 to} F _{3, j (3)} } …………………… F _k = {F _{k, 1} , F _{k, 2 to} F _{k, f (k)} } The burst error correction decoding unit 48, in addition to the process of selecting cyclically consecutive n _i bits in the E _i sequence, selects a bit of relatively low reliability among the selected bits, A process of inverting only that bit to generate new n _i bits is added, and the H _{i, j (i)} sequence is converted to j2 ( ₎ by error correction code processing and cyclic shift processing using the generator polynomial. i) Includes means for generating a number.

The combining unit 49, the E _i is generated corresponding to the sequence (f (i) + j2 (i)) number j3 from the decoding candidates in reliable order (i) number of the E _i series It is selected as the corresponding first candidate J _i , and the first candidate J _i is combined as shown in FIG. 15, and the decoding candidates I _l (l =
The maximum of 1 to k and k includes means for generating Π _{j3 (i)} (i = 1 to k). Although j3 (i) generally takes a value smaller than (f (i) + j2 (i)), it may be equal to (f (i) + j2 (i)).

When the CRC code error detection decoding unit 50 and the maximum likelihood decoding selection unit 51 perform error detection decoding on the decoding candidate I _l and there is only one decoding candidate determined to have no error, the decoding is performed. When a candidate is selected as the decoding result of the information bit sequence of the A sequence and there are a plurality of decoding candidates determined to be error-free, the reliability of these decoding candidates is compared to determine the highest decoding candidate as the A sequence. Means for selecting as the decoding result of the information bit sequence of.

The operation of the system of the present embodiment configured as above will be described focusing on the error correction / detection coding / decoding technique. In this system. An information bit sequence (A sequence) having a 53-bit length is encoded and transmitted.

First, on the transmitting side, a CRC code of 10 bits is applied to the 53-bit information bit sequence as an error detection coding process to perform CRC coding to generate a 63-bit B series (CRC code). Part 41).

Next, this B sequence is divided into k = 3,
B _i (i = 1 to 3) in which the number of bits of each series is 21 bits
A sequence is generated (dividing unit 42).

Next, the B _i sequence is used as a cyclic code to perform an encoding process using three BCH (41, 21) codes to generate a C _i sequence (BCH encoding section 43). This BCH code has 21 information bits and 41 code lengths, respectively.
Each C _i sequence has 41 bits.

Next, the C _i sequence is further subjected to bit interleaving processing and combined to form a D sequence, which is transmitted via the transmission path (interleaving section 44, wireless transmission section 45). Here, the bit interleaving process is
For example, as shown in FIG. 4, two C _i sequences, that is, the i-th
With a structure that extends over the frame and the (i + 1) th frame,
The information bit portion and the redundant bit portion are transmitted together. The interleaving unit 44 waves, as shown in FIG. 4, transmits information bits between a plurality of (two) frames.
It is not limited to the interleaving technique. The interleaving unit 44 can employ various bit interleaving techniques such as a technique of bit interleaving information bits in one frame.

On the other hand, the receiving side performs de-interleaving processing, which is the reverse processing of the bit interleaving processing on the transmitting side, on the reception sequence received from the transmission line, and further, three pieces corresponding to the BCH code. To generate an E _i sequence (each sequence is 41 bits long) corresponding to the C _i sequence on the transmission side (de-interleaving unit / dividing unit 4).
6). Here, if there is no error on the transmission path, the C _i sequence and the E _i sequence completely match.

Next, both the random error correction decoding process and the burst error correction decoding process are performed on the E _i sequence to generate the sequence sets F _i and H _i (random error correction decoding unit 47 and burst error correction). Decoding section 48).

The burst error correction decoding process here is performed as follows. That is, n _i bits that are cyclically continuous are selected from each of the E _i series,
The BCH encoder 43 uses the n _i bits as information bits.
Cyclic encoding is performed using the same generator polynomial as the encoding _{in 1.} to generate a G _{i, 1} sequence, and this G _{i, 1} sequence is cyclically shifted to generate n _i bits of the portion corresponding to the B _i sequence. Consisting of H
Generate an _{i, 1} sequence. Then, to generate the G _{i, 2} sequence by performing the same processing by selecting the different n _i bits which continuously cyclically from each of the E _i series, the G _{i, 2}
A H _{i, 2} sequence is generated based on Hereinafter, similarly, the above n _i
The positions of these bits are sequentially changed and repeated, and finally, a series set H _i of the following equation is generated for the E _i series.

H ₁ = {H _1,1 , H _{1,2 to} H _{1, j (1)} } H ₂ = {H _2,1 , H _{2,2 to} H _{2, j (2)} } H ₃ = {H _3,1 , H _{3,2 to} H _{3, j (3)} } The above is the burst error correction decoding process.

Next, the elements of the set F _i and the set H _i obtained by the random error correction decoding unit 47 and the burst error correction decoding unit 48 are combined (combining unit 49). This synthesizer 4
In _No. 9, F _{i, 1} as a decoding candidate for the B _i sequence
And H _{i, 1} , H _{i, 2 to} H _{i, j ( i)} (1 + j (i)) are selected, and these decoding candidates are combined to obtain I _l sequence (however, , L = 1 to k, the maximum of k produces Π i (1 + j (i))).

Next, the I ₁ sequence obtained by the combining unit 49 is subjected to error detection decoding with a CRC code (CRC error detection decoding unit 50). Here, as a result of this error detection decoding, if there is only one decoding candidate that is determined to have no error,
When the decoding candidate is selected as the decoding result of the information bit sequence, and there are a plurality of decoding candidates determined to have no error,
The reliability of these decoding candidates is compared, and the highest decoding candidate is selected as the decoding result of the information bit sequence to obtain the final decoding result (selection unit 51).

Block 4 which is the main configuration in this embodiment
7 to 51 will be described in more detail. As shown in FIG. 5, the decoder includes a deinterleaving unit 46A, a codeword dividing unit 46B, a random error correction decoding unit 47, a burst error correction decoding unit 48, a combining unit 49, a CRC decoding check unit 51, and maximum likelihood decoding. It comprises a word selection unit 51.

The random error correction decoding unit 47 performs error correction decoding using random cyclic codes. This random error correction decoding technique is not particularly limited, but here, for example, the technique proposed by Bulk is used (“A Decoding Procedur
e for Multiple-Error-Correcting Cyclic Codes ”IEE
E TRANSACTIONS ON INFORMATION THEORY IT10, pp134-1
39, April, 1964). Since this decoding method is based on the hard decision of the receiver, it is necessary to devise it when using the reliability information obtained from the soft decision receiver. The method proposed by Chase is used as a method of using reliability information (“A Class of Algorithms for Decoding Block Cod
es With Channel Measurement Information ”IEEE TRA
NSACTIONS ON INFORMATION THEORY, VOL. IT-18, NO. 1,
JANUARY 1972).

FIG. 6 is a detailed block diagram of the random error correction decoding unit 47 utilizing the concept of the Chase technique. As shown in FIG. 6, a bit inversion circuit 47A, a plurality of random error correction decoding circuits 47B, an ordering circuit 4
7C and a selection circuit 47D. First, the received word r
Random error correction decoding circuit 47 (E _i series in this case)
Burst error correction decoding is performed by B as it is. on the other hand,
A bit inversion circuit 4 determines the bit with low reliability in the received word r.
Invert by 7A. As a result, inverted code words r ₁ and r ₂ ~ are generated. This inverted codeword r ₁ ,
The random error correction decoding circuit 47B performs random error correction decoding on r ₂ to. Random error correction decoding circuit 4
7B uses, for example, the technique described above for the bulk proposal.
By the above, I decoding candidates are generated. Next, the ordering circuit 47C orders the f (i) decoding candidates by reliability. Then, the selection circuit 47D selects f (i) decoding candidates selected by the ordering circuit 47C from the highest reliability. Since this Chase technique is premised on the use of CRC, it differs from the present invention in that one candidate with the highest reliability is adopted as the decoding result.

FIG. 7 is a detailed block diagram of the burst error correction decoding unit 48 using the reliability information. The burst error correction decoding unit 48 includes a selection circuit 48A, a plurality of bit inversion circuits 48B, and a plurality of burst error correction decoding circuits 4
8C, an ordering circuit 48D, and a selection circuit 48E. First, the selection circuit 48 causes the A received word r to be 4
21 bits that are cyclically continuous with high reliability from 1 bit
Select multiple bits. The selected 21 bits will be referred to as a seed bit string. Next, with respect to these 21-bit seed bit strings, the bits having relatively low reliability are inverted by the bit inversion circuit 48B. As a result, an inverted seed bit string is generated. By using the seed bit and the inverted seed bit thus obtained, the burst error correction decoding circuit 48C
By performing burst error correction decoding by Jo (i)
Generate decoding candidates.

The burst error correction decoding circuit 48C includes, for example, "Miyakawa, Iwadare, Imai" Error Correction Code ", Shokoido, 19
The cyclic error burst error correction technique described in "73" is used therein. That is, 21 bits that are cyclically continuous are selected from the 41 bits, which are encoded as information bits to generate redundant bits.

Next, the ordering circuit 48D orders the Jo (i) decoding candidates by reliability. Then, the selection circuit 48E selects Jo (i) pieces from the ordered decoding candidates in descending order of reliability.

By the burst error correction decoding process and the random error correction decoding process shown in FIGS. 6 and 7 described above, there are f (i) + j2 (i) decoding candidates corresponding to each B _i sequence. Is generated. As a result, there are Π (i) + j2 (i) (i + j) (i = 1 to 3) decoding candidates for the B sequence. In the CRC error detection decoding unit 50 of FIG. 3 or FIG.
(i) + j2 (i) (i + j) (i = 1 to 3) All the decoding candidates are subjected to error detection check by the CRC code.
If more than one candidate remains as a result of this check, the candidate with the highest reliability among these is selected as the final decoding result (decoded word) by the maximum likelihood decoding selection unit 51.

As described above, according to the first embodiment of the present invention, both burst error correction and random error correction are applied to the received sequence, and C is applied to the correction result.
By applying the error detection coding process using the RC code, it is possible to realize efficient error correction even in a transmission line where a random error and a burst error occur in a mixed manner such as in a mobile radio system, and the error miss rate is also achieved. Can be kept small.

Next, the system of the second embodiment is shown in FIG.
This will be described with reference to FIGS. 9 to 11. The system of the second embodiment shown in FIG. 8 has information bits (144 bits) as the A series. In addition, the system of the second embodiment has substantially the same blocks as the system of the first embodiment shown in FIG. CRC encoder 41 in FIG.
And the CRC encoding unit 141 in FIG. 8 are substantially the same. The dividing unit 42 in FIG. 3 and the dividing unit 1 in FIG.
42 is substantially the same. The BCH encoder 43 in FIG. 3 and the BCH encoder 143 in FIG. 8 are substantially the same. The interleaving unit 44 in FIG. 3 is substantially the same as the interleaving unit 144 in FIG. 8 except that block interleaving in one frame is used. The wireless transmission unit 45 in FIG. 3 and the wireless transmission unit 145 in FIG. 8 are substantially the same. De-interleaving unit / dividing unit 4 in FIG.
6 is substantially the same as the de-interleaving unit / dividing unit 146 in FIG. 8 except that block interleaving in one frame is used. The random error correction decoding unit 47 in FIG. 3 and the random error correction decoding unit 147 in FIG. 8 are substantially the same. The burst error correction decoding unit 48 in FIG. 3 and the burst error correction decoding unit 148 in FIG. 8 are substantially the same. Also, the encoder 20 in FIG. 3 and the encoder 2 in FIG.
It is substantially the same as 0 '.

However, the decoder 26 in FIG. 3 is different from the decoder 26 'in FIG. The decoder 26 ′ inserts the narrowing unit 149 between the random error correction decoding unit 147, the burst error correction decoding unit 148, and the combining unit 150.

The narrowing unit 149 operates according to the condition 1. That is, as shown in FIG. 9, before selecting j3 (i) from (f (i) + j2 (i)) decoding candidates in the combining unit 149, f (i) corresponding to the B sequence are selected. Of the F _{i, f (i)} sequences are narrowed down to f3 (i) (f (i) ≧ f3 (i)), and j2 (i) H _{i, j2 (i)} sequences are j3 (i). Pieces (j2 (i)
Narrow down to ≧ j3 (i)).

Further, the narrow-down unit 149 operates according to the condition 2. That is, as shown in FIG. 10, (f (i) +
j2 (i)) means for obtaining the reliability of the decoding candidates;
The number of candidates corresponding to the B series is set to f (i) according to the degree of reliability and the relative magnitude acquired by the means.
The set F _i having a number of elements f3 (i) number (f (i) ≧ f3 ( i)
), The j2 (i) H _i sequences are j3 (i) (j2 (i)).
(i) ≧ j3 (i)).

Further, the narrow-down unit 149 operates according to the condition 3. That is, as shown in FIG. 11, the narrowing-down unit 149 appropriately suppresses the number of candidates corresponding to the B sequence to be equal to or less than the planned number below Π i (f3 (i) + j3 (i)). The f (i) F _i sequences are f3 (i) (f (i) ≧ f3
(i)), and the j2 (i) H _i sequences are narrowed down to j3 (i) (j2 (i) ≧ j3 (i)).

The random error correction decoding unit 147 in this embodiment generates a maximum of two decoding candidates for Bi by the processing of (1) and (2) below.

(1) The received word r (here, E _i ) is directly decoded.

(2) Invert the least reliable bit in the received word r to generate the inverted bit r ₁ of the received word r,
This is decrypted. Here, when the decoding results by the above processes (1) and (2) are different, the number of decoding candidates for B _i is 2
If they match, the number of decoding candidates is 1.

The burst error correction decoding unit 148 in the present embodiment uses the burst error correction method of the cyclic code described above to generate two decoding candidates. That is, 10 bits that are cyclically continuous are selected from 14 bits, and these are encoded as information bits to generate 4 redundant bits.
This is a decoding method that adopts these 4 bits as a decoding candidate.
In the present embodiment, burst error correction decoding is performed by the following processes (1), (2) and (3) using the reliability information obtained from the receiver.

(1) There are 14 cyclically continuous 10 bits in the 14 bits of the received word. From these, one cyclically continuous 10-bit with the highest reliability is selected. The selected 10 bits are called seed bits.

(2) Regarding the seed bit, one bit having the lowest reliability is inverted to generate an inverted seed bit.

(3) Burst error correction decoding is performed using the above seed bits and inverted seed bits to generate two decoding candidates.

Next, the processing contents of the narrowing unit 149 in this embodiment will be described. That is, by the processing of the random error correction decoding unit 147 and the burst error correction decoding unit 148, the maximum of two candidates for B _i , respectively, and the maximum of (2
+2) decoding candidates can be generated. The maximum number of decoding candidates for the sequence B is (2 + 2) ¹⁶ .

From the candidates for the sequence B, the following (1)-
By the procedure of (7), the number of candidates is narrowed down to a predetermined number (CA) or less.

(1) The 16 received words are sorted in the order of reliability.

(2) For the received word with the lowest reliability,
A candidate to be left is determined according to a predetermined condition.

(3) The above number of candidates is set in the candidate number buffer.

(4) Next, regarding the received word with the low reliability,
The candidates to be left are determined according to the above-mentioned predetermined conditions.

(5) The product of the value of the number of candidates buffer and the number of candidates is calculated, and the obtained value is set in the number of candidates buffer.

(6) The value of the candidate number buffer is compared with the number of CAs, and if the value of the candidate number buffer becomes large, the above (4)
Only one candidate with the highest reliability is left.

(7) The above processes (4) to (6) are repeated to determine candidates for all 16 received words.

The number of candidates for each received word is CW _i (i = 1,
2,3, ..., 16), the candidates for sequence B are Π (i = 1
~ 16) x CW _i pieces.

With respect to the candidates for the sequence B narrowed down by the above processing, the CRC error detection decoding unit 152
Check the error detection by code. Then, the result of the CRC error detection / decoding unit 152 is passed through the selection unit 152 to obtain the final decoding result. Next, the third aspect of the present invention
The system of the embodiment will be described with reference to FIGS. 12 and 13. 12 and 13, the same parts as those in FIG. 8 are designated by the same reference numerals and the description thereof will be omitted. That is, the system of the third embodiment realizes reduction of the processing amount required for CRC decoding. In the above example, the number of candidates is Π (i = 1 to 16) × CW _i , so CRC decoding is also π (i = 1 to 1) unless special measures are taken.
6) × CW _i times are required, but the number of CRC decoding times can be reduced and the processing amount can be reduced by applying the processing described below. As shown in FIGS. 12 and 13, the decoder 2 includes the first processing unit 153, the second processing unit 154, the third processing unit 155, and the fourth processing unit 156.
6 "is configured.

The first processing unit 153 determines that the number of random error correction decoding candidates in the F _i sequence generated by the random error correction decoding unit 147 is f4 (i) (i = 1 to k), and the burst error correction decoding is performed. The number of candidates for burst error correction decoding in the H _i sequence generated by the unit 148 is j4 (i) (i = 1
.About.k), an I _ko sequence is constructed using the F _i (i = 1 to 16), CRC error correction decoding is performed on this I _ko sequence, and redundant bits R of this decoded sequence are used. Remember _o .

The second processing unit 154 sets all the information bits other than the ith information bit in the CRC error correction decoded sequence to zero, and the ith information bit in the CRC error correction decoded sequence corresponds to the C _i sequence. configure I _k sequence by performing an exclusive OR processing for each bit of the decoded candidates and the F _i sequence, the I _k sequence performs CRC error correction decoding, the decoded redundant bits R _{i, j ( i)} (i = 1 to k, j (i) = 1
~ (F4 (i) + j4 (i) -1)) is stored.

The third processing unit 155 applies the following logical processing to all combinations of the decoding candidates, and determines that the result of this logical processing becomes zero.

[0072] ^{_{R o ER R 1, J (}} i) ER R 2, J (i) ER R 3, J (i) ER ~ ER R k, J (i) where, ^ER is bitwise exclusive Indicates.

When the R _o or the result of the logical processing is zero, the fourth processing unit 156 determines that the result of the exclusive OR processing of the I _ko and the I _k is the final result that does not include an error. It is determined that it is a decryption result.

Further, the first processing section 153 and the second processing section 1
54, the 3rd processing part 155, and the 4th processing part 156 are explained in detail.

The first processing unit 153 determines that the number of random error correction decoding candidates in the F _i sequence generated by the random error correction decoding unit 147 is f4 (i) (i = 1 to k), and the burst error correction decoding is performed. The number of candidates for burst error correction decoding in the H _i sequence generated by the unit 148 is j4 (i) (i = 1
˜k), the first candidates J _i (J _i = F _{i, 1} ) corresponding to the B _i series (i = 1 to k) are combined as shown in FIG. 15 to correspond to the B series. The second candidate I _o is obtained and this second
Obtain the syndrome S _o candidate I _o to an error detection decoding, and stores the syndrome S _o.

The second processing section 154 operates as follows. That is, first, the sequence L _{i, m} (i = 1 to k, m = 1 to (f4
(i) + j (4 (i)) is generated as follows.

L _{i, m} = F _{i, 1} ^ER F _{i, m} (m = 1 to f4 (i)) L _{i, m} = F _{i, 1} ^ER F _{i, (m-f4 (i))} (m = F4 (i) +1 to f4 (i) + j4 (i)) However, ^ER indicates an exclusive OR for each bit.

Then, for a certain j (1 ≦ j ≦ k), J _i = L _{i, m} (i = j) J _i = All bits are zero (i ≠ j) J _i (i = 1 to k) is generated. This J _i
As shown in FIG. 15, they are combined to generate an I ′ sequence.
The same process as the error detection decoding for the second candidate I _o is applied to this I ′ sequence to obtain the syndrome S _{j, m} . In this case, the syndrome S _{j, m} is J (J = 1 to k) and each
It is generated for all of m = 1 to (f4 (i) + j (4 (i)), and these syndromes S _{j, m} are stored.

The third processing section 155 operates as follows.
That is, m ₁ , m _{2 to} m _k are defined as follows.

1 ≦ m ₁ ≦ (f4 (i) + j (4 (1)) 1 ≦ m ₂ ≦ (f4 (i) + j (4 (2)) ... 1 ≦ m _k ≦ (f4 (i) + j (4 (k)) All combinations of m ₁ , m _{2 to} m _k (Π (f4 (i) + j (4
(k)), the following logical processing is applied. As a result, it is determined that the obtained sequence has all bits of zero.

The S _o ^ER S _{1, m1} ^ER S _{2, m2} ^ER S _{3, m3} ^ER to ^ER S _{k, mk} fourth processing unit 156 operates as follows. That is,
A sequence in which all bits are zero when m ₁ and m _{2 to} m _k is
When obtained by the third processing unit 155, J _i (i = 1 to k) is generated by the following processing.

J ₁ = F _1,1 ^ER L _{1, m1} J ₂ = F _2,1 ^ER L _{2, m2} ………… J _k = F _{k, 1} ^ER L _{k, mk} These J _i are shown in FIG. The I "sequence is generated by combining as shown. The I" sequence is determined to be the final decoding result that does not include an error for B.

The effects of the present invention described above can be confirmed with reference to FIG. In FIG. 14, the horizontal axis shows the bit error rate and the vertical axis shows the frame error rate. As shown in FIG.
According to the present invention, the frame error rate can be reduced to about 1/2 as compared with the conventional technique (soft decision, hard decision).

The present invention is not limited to the above embodiments, but can be implemented with various modifications without departing from the gist of the present invention.

[0085]

As described above, according to the present invention, on the transmitting side, the information bit sequence is subjected to error detection coding processing such as CRC coding, and then error correction coding is carried out using the cyclic code and transmitted to the transmission line. On the receiving side, the random error correction decoding process of the cyclic code and the burst error correction decoding process are applied to the code sequence at the same time, and the error detection check is performed on the decoding result obtained by using the CRC code or the like. Then, the final decoding result is obtained.

According to the series of processes, basically, the random error correction decoding process of the cyclic code and the burst error correction decoding process are performed as much as possible to perform decoding, and for the purpose of reducing the error oversight that increases at this time, it is powerful. Since error detection decoding such as CRC coding is also used, when applied to a transmission line in which random errors and burst errors coexist, such as mobile radio systems, efficient error correction is realized and errors are overlooked. The rate can be kept small.

Further, the error correction capability is further increased, and the decoding efficiency is improved because only the highly reliable decoding candidates are intensively checked by the CRC code or the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a wireless transmission system to which the present invention is applied.

FIG. 2 is a block diagram showing a main part of the wireless transmission system of FIG.

FIG. 3 is a block diagram showing a main part of a first embodiment of a system according to the present invention.

FIG. 4 is a detailed block diagram of an interleaving unit in FIG.

5 is a detailed block diagram of the decoder in FIG.

FIG. 6 is a detailed block diagram of a random error correction decoding unit in FIGS. 3 and 5.

FIG. 7 is a detailed block diagram of a burst error correction decoding unit in FIGS. 3 and 5.

FIG. 8 is a block diagram showing the main parts of a second embodiment of the system according to the present invention.

9 is a detailed block diagram of a first example of the decoder in FIG.

10 is a detailed block diagram of a second example of the decoder in FIG.

FIG. 11 is a detailed block diagram of a third example of the decoder in FIG.

FIG. 12 is a block diagram showing the main parts of a third embodiment of the system according to the present invention.

13 is a detailed block diagram of the decoder in FIG.

FIG. 14 is a comparative characteristic diagram of the present invention and a conventional technique (soft decision, hard decision).

FIG. 15 is a diagram showing the relationship between Ji and Il.

[Explanation of symbols]

10 ... Mobile network, 11 ... Control station, 12 ... Base station, 13 ... Mobile station, 14 ... Fixed network, 20, 27 ... Encoder, 21, 28
... transmitter, 22, 24 ... antenna, 23 ... transmission path, 2
5, 29 ... Transmitter, 26, 30 ... Decoder, 41, 141
... CRC code part, 42, 142 ... Dividing part, 43, 143
... BCH code part, 41, 141 ... interleaving,
45 ... Radio transmission section, 46, 146 ... De-interleaving section / dividing section, 47, 147 ... Random error correction code section, 48, 148 ... Burst error correction code section, 49, 1
50 ... synthesizing unit, 50, 151 ... CRC error detecting / decoding unit,
51, 152 ... Selection unit, 149 ... Narrowing unit, 153 ... First processing unit, 154 ... Second processing unit, 155 ... Third processing unit,
156 ... Fourth processing unit.

Claims (3)

[Claims] 1. An error detection code section for error-detecting and coding an information bit sequence given as an A-sequence to generate a B-sequence consisting of information bits and redundant bits for error-detection coding, and a B _i sequence. (I = 1 to k, bit length n _{i of} each sequence), a division unit that divides the B sequence into k pieces, and a cyclic code of each of the B _i sequences to generate a C _i sequence. An error correction coding unit that performs error correction coding, an interleaving unit that interleaves the C _i sequence to generate a D sequence, a transmission unit that transmits the D sequence to a predetermined transmission path, and an E _i sequence In order to do so, the D received from the transmission line
A de-interleaving unit and a dividing unit that de-interleaves the E sequence corresponding to the sequence and divides the de-interleaved sequence into k corresponding to the cyclic code, and F _{i, 1} sequence ( to generate a bit length n _i) of each series,
A random error correction code section for random error correction coding of cyclic codes in people the E _i sequence husband, H _i, to generate a _{J (i)} sequence (bit length n _i of each series), a s the E _i sequence husband A burst error correction decoding unit for performing a burst error correction decoding of a cyclic code, and a total (1 + j (i _{) of the} Fi _{, 1} series and the _{Hi, 1} , Hi _{, 2 to} Hi _{, j (i)} series. )) One is selected to generate a first decoding candidate J _i corresponding to the B _i sequence, and the first decoding candidate J _i is generated.
The second decoding candidate I _l corresponding to the B sequence by combining _i
(L = 1 to k, the maximum of k is Π _{i, (1 + j (i))} (i = 1 to k)), and the second decoding candidate I _l is subjected to error detection decoding to perform the A sequence. An information bit sequence transmission system comprising: final decoding means for generating a decoding result of an information bit sequence corresponding to. 2. The random error correction decoding unit uses soft-decision decoding using reliability information obtained on the receiving side to obtain F _{i, 1} and F _{i, 2} as decoding candidates for each E _i sequence. comprises means for generating a ~F _{i, f (i)} sequences, the burst error correction decoding unit, and n _i consecutive bits cyclically in the E _i series, relatively confidence in the E _i series A means for generating the H _{i, 1} , H _{i, 2 to} F _{i, j2 (i)} sequences by using the cyclic polynomial generating polynomial with the newly obtained _ni bit sequence obtained by inverting the low bits. wherein said combining unit, the decoded candidates corresponding to the E _i sequence (f
(i) + j2 (i)) decoding candidates, and by selecting j _{3 (i)} decoding candidates from the (f (i) + j2 (i)) decoding candidates, the decoding candidates corresponding to the B sequence are generated. I _l (l = 1 to k, the maximum of k is Π _{i, j3 (i)} (i
= 1 to k)), the CRC code error detection decoding unit and the maximum likelihood decoding selection unit,
As a result of error detection decoding of the decoding candidate I _l , when there is only one decoding candidate determined to be error-free, the decoding candidate is selected as the decoding result of the information bit sequence, and it is determined that there is no error. The information bit according to claim 1, further comprising means for comparing the reliability of the decoding candidates and selecting the highest decoding candidate as a decoding result of the information bit sequence of the A sequence when there are a plurality of decoding candidates. Series transmission system. 3. An error detection code section for error-detecting and coding an information bit sequence given as an A-sequence to generate a B-sequence consisting of information bits and redundant bits for error-detection coding, and a B _i sequence. (I = 1 to k, bit length n _{i of} each sequence), a division unit that divides the B sequence into k pieces, and a cyclic code of each of the B _i sequences to generate a C _i sequence. An error correction coding unit that performs error correction coding, an interleaving unit that interleaves the C _i sequence to generate a D sequence, a transmission unit that transmits the D sequence to a predetermined transmission path, and an E _i sequence In order to do so, the D received from the transmission line
A de-interleaving unit and a dividing unit that de-interleaves the E sequence corresponding to the sequence and divides the de-interleaved sequence into k corresponding to the cyclic code, and corresponds to the B _i sequence. F _{i, f4 (i)} sequences that are random error correction decoding candidates (i = 1 to k, bit length n _{i of} each sequence)
To generate a random error correction decoding unit that performs random error correction decoding of a cyclic code on each of the E _i sequences, and a H _{i, j4 (i)} sequence that is a burst error correction decoding candidate corresponding to the B _i sequence. i = 1 to k, bit length n _{i of} each sequence)
To generate the burst error correction decoding unit for cyclic error burst decoding of each E _i sequence, and the number of random error correction decoding candidates in the F _i sequence generated by the random error correction decoding unit is f _{4 ( i)} (i = 1 ~ k)
H generated by the burst error correction decoding unit.
The number of candidates for burst error correction decoding in the i series is j _{4 (i)}
If (i = 1 ~k) a number, constitutes the I _Ko sequence using the Fi (i = 1 ~k), the I _Ko sequence performs CRC error correction decoding, the decoded sequence Redundant bit R
a first processing unit for storing _o , all the information bits other than the i-th information bit in the CRC error-correction decoded sequence being zero, and the i-th information bit in the CRC error-correction decoded sequence corresponds to the C _i sequence. configure I _K sequence by performing an exclusive OR processing for each bit of the decoded candidates and the F _i sequence, the I _K series performs CRC error correction decoding, the decoded redundant bits R _{i, j ( i)} (i =
A second processing unit for storing 1 to k, j (i) = 1 to (f4 (i) + j4 (i) -1)), and the following logical process applied to all combinations of the decoding candidates Then, a third processing unit that determines that the result of this logical processing becomes zero, and _Ro ^ER R _{1, J (i)} ^ER R _{2, J (i)} ^ER R _{3, J (i)} to ^ER R _{k, J (i)} (However, ^ER indicates an exclusive OR for each bit.) When R _o or the result of the logical processing is zero, the exclusive logic of I _ko and I _k An information bit sequence transmission system, comprising: a fourth processing unit that determines that the result of the sum processing is a final decoding result that does not include an error.