JPH06188694A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To obtain a general-purpose flip-flop circuit(FF) by devising the circuit so as to be operated by either rising and falling edge of a clock signal. CONSTITUTION:When an enable signal E is made to 1, an in phase signal P and an inverting signal inverse of P are made to an opposite value to that of the time when the enable signal E is made to 0, and a synchronizing signal generating circuit corresponds a rising change of a clock signal CK from 0 to 1 to a falling change of an in phase signal P from 1 to 0. That is, a DFF fetches data inputted to a terminal D at the trailing edge of the clock signal CK and outputs inverted input data to a terminal QN. The synchronizing signal generating circuit converts the clock signal CK by the control of the enable signal E into a negative lock signal CN and the general-purpose performance is improved by inputting data at the rising edge and outputting the data at the falling edge.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit (FF) which takes in input information at a change point of a clock signal.

[0002]

2. Description of the Related Art Conventionally, as this type of FF, for example, a DFF shown in FIG. 3 for capturing a rising edge of a clock signal and inputting information, and a DFF shown in FIG. 4 for capturing a falling edge of a clock signal and inputting information. There is a DFF shown.

The diagram (a) in each of these figures is a circuit showing the logic of the DFF. Clocked inverter 1, 21
Inputs data from the D terminal when the in-phase signal P is 0,
When the in-phase signal P is 1, a high impedance state is set and data is not captured. The NOT circuits 2 and 3 and the transfer gate 4, and the NOT circuits 22 and 23 and the transfer gate 24 form a sequential circuit when the in-phase signal P is 1, and hold the input data from the clocked inverters 1 and 21. When the synchronizing signal P is 0, the transfer gates 4 and 24 are turned off, so that the input data is inverted and output. The transfer gates 5 and 25 take in data from the NOT circuits 2 and 22 when the in-phase signal P is 1, and output the data to the NOT circuits 6 and 26. The NOT circuits 6 and 7 and the transfer gate 8 and the NOT circuits 26 and 27 and the transfer gate 28 form a sequential circuit when the in-phase signal P is 0 and hold the input data. Further, when the in-phase signal P is 1, the NOT circuits 6 and 26 are
The data from the NOT circuits 9 and 29 are output to the Q terminal, and the data from the NOT circuits 7 and 27 are NOT-outputted.
Output to the QN terminal via the circuits 10 and 30.

Each of FIGS. 3 (b) and 3 (b) shows a circuit for generating a synchronization signal applied to each of the logic circuits.
The synchronization signal includes an in-phase signal P that changes the same state as the clock signal and a negative-phase signal bar P that changes the state opposite to the clock signal. DF operating on the rising edge shown in FIG.
A signal obtained by inverting the clock signal CK by the NOT circuit 11 is output to F as the anti-phase signal bar P, and NOT
The signal inverted by the circuit 12 is output as the in-phase signal P. In addition, the DFF operating at the falling edge shown in FIG.
, The negative clock signal CN obtained by inverting the clock signal CK is output as the in-phase signal P by the NOT circuit 31, and the signal inverted by the NOT circuit 32 is output as the anti-phase signal bar P. . Therefore, FIG.
The data input to the D terminal is output to the Q terminal at the timing when the clock signal CK rises from 0 to 1 in the DFF shown in FIG. 4 and the timing when the negative clock signal CN falls from 1 to 0 in the DFF shown in FIG. Then, the inverted data is output to the QN terminal.

[0005]

However, in the above-mentioned conventional flip-flop circuit, the timing at which the input data is taken in is limited to either the rising or falling transition point of the clock signal. For this reason, the circuit is not versatile and may cause various inconveniences.

For example, in a gate array in which two types of DFFs operating at different edges are arranged in an array, it takes a lot of time to test each DFF by the scan path method, and it is difficult to test. That is,
When two types of DFFs, a DFF that operates on the rising edge of a clock signal and a DFF that operates on the falling edge, are mixed in the gate array, first, each DFF that operates on the rising edge is connected in a shift register mode. Apply scan input to the shift register. Then, by giving rise transition of the clock signal to each DFF, a scan output is obtained after a predetermined clock and compared with the scan input. After that, each DF that operates on the falling edge
F is connected in a shift register fashion and provides a scan input to this shift register. Then, by giving a falling change of the clock signal to each DFF, a scan output is obtained after a predetermined clock and compared with the scan input. Therefore, when two types of DFFs that operate at the rising edge and the falling edge of the clock signal are mixed, it is necessary to configure a shift register for each FF type and compare the scan input and the scan output for each FF type. Get up. Therefore, it takes a lot of time and time to test the DFF by the scan path method.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and inverts input data in one state of the sync signal and outputs the inverted data, and does not input data in the other state of the sync signal. An inverting circuit, an input data holding circuit that inverts and outputs data from the sync inverting circuit when the sync signal is in one state, and holds data that was input during the other state of the sync signal, and input data when the sync signal is in one state A switching circuit that does not accept the output of the holding circuit when the synchronization signal is in the other state, and takes in the held data of the input data holding circuit, and a data that was input when the synchronization signal is in one state, and outputs the switching circuit when the synchronization signal is in the other state An output data holding circuit that inverts and outputs the sync signal, and when the control signal is in one state, changes the sync signal to the same state as the clock signal It is obtained by a synchronizing signal generating circuit for changing to the opposite state.

[0008]

When the synchronizing signal generating circuit changes the synchronizing signal to the same state as the clock signal, the input data is taken in at either the rising or falling timing of the clock signal. Also, when the sync signal is changed to a state opposite to the clock signal by the sync signal generation circuit,
Input data is taken in at the other timing of the clock signal.

[0009]

1 is a circuit diagram showing a DFF according to an embodiment of the present invention.

FIG. 1A shows the logic circuit of the DFF, and FIG. 1B shows the generation circuit of the synchronization signal given to this logic circuit. Further, FIG. 7C shows the internal structure of this synchronization signal generation circuit.

The synchronizing signal generating circuit shown in FIG.
It is composed of an XOR circuit 51 and a NOT circuit 52. The clock signal CK and the enable signal E are input to the EXOR circuit 51. The EXOR circuit 51 takes the exclusive OR of the input signals. That is, 0 is output when each input signal is the same signal. If each input signal is a different signal, 1 is output. EXO
The signal output from the R circuit 51 is output as the in-phase signal P, and the signal obtained by inverting the output signal of the EXOR circuit 51 in the NOT circuit 52 is output as the anti-phase signal bar P.

FIG. 1C shows the inside of the EXOR circuit 51, which is a P-channel MOSF.
ET53a-e and N-channel MOSFET 54a-
It is composed of e.

The timing signal generating circuit having the above configuration outputs the in-phase signal P shown in the following Table 1 according to the input clock signal CK and enable signal E.

[0014]

[Table 1]

The in-phase signal P and the anti-phase signal bar P are given to the respective signal lines marked with the symbol P and bar P corresponding to FIG.

The logic circuit shown in FIG. 1A is constructed as follows.

A signal from the data input terminal D is applied to the clocked inverter 41. The clocked inverter 41 inverts and outputs the input signal when the in-phase signal P is 0, and when the in-phase signal P is 1, enters a high impedance state and blocks the input signal without accepting it. The output of the clocked inverter 41 is given to the NOT circuit 42, and the output of the NOT circuit 42 is given to the NOT circuit 43. Further, the output of the NOT circuit 43 is given to the transfer gate 44, and the output of the transfer gate 44 is given to the input of the NOT circuit 42. The transfer gate 44 is turned on when the negative-phase signal bar P is 0, that is, when the in-phase signal P is 1, and the output of the NOT circuit 43 is directly transmitted to the input of the NOT circuit 42. Also,
The transfer gate 44 is turned off when the in-phase signal P is 1, that is, when the in-phase signal P is 0, and the output of the NOT circuit 43 is cut off. That is, when the in-phase signal P is 1, the NOT circuits 42 and 43 and the transfer gate 44 form a closed circuit to form a sequential circuit and hold the input data. On the other hand, when the in-phase signal P is 0, this closed circuit is opened and the connection of the sequential circuit is released. When this connection is released, the clocked inverter 41
The output from is transmitted via the NOT circuit 42 to the transfer gate 45 whose input is connected to this output.

The transfer gate 45 has a reverse phase signal bar P.
Is 0, that is, when the in-phase signal P is 1, it is turned on, and when the anti-phase signal bar P is 1, that is, when the in-phase signal P is 0, it is turned off. Therefore, the transfer gate 45 transmits the output of the NOT circuit 42 to the NOT circuit 46 when the in-phase signal P is 1, and the NOT when the in-phase signal P is 0.
The output of the circuit 42 is cut off.

The NOT circuit 46 inverts the input data to N
The data is output to the OT circuit 47, and the NOT circuit 47 inverts the input data and outputs it to the transfer gate 48. The output of the transfer gate 48 is connected to the input of the NOT circuit 46. The transfer gate 48 is turned on when the in-phase signal P is 0, and the output of the NOT circuit 47 is NO.
Notify the T circuit 46. Further, the transfer gate 48 is turned off when the in-phase signal P is 1, and the NOT circuit 47
From the output to the NOT circuit 46. That is, NOT
The circuits 46 and 47 and the transfer gate 48 form a closed circuit by forming a closed circuit when the in-phase signal P is 0, and release the connection of the sequential circuit when the in-phase signal P is 1.

The output of the NOT circuit 46 is also connected to the input of the NOT circuit 49, and the output of the NOT circuit 49 is connected to the Q terminal. The output of the NOT circuit 47 is also connected to the input of the NOT circuit 50.
The output of the circuit 50 is connected to the QN terminal.

In such a configuration, the synchronizing signal generating circuit generates the in-phase signal P according to the clock signal CK as shown in Table 1 when the enable signal E is 0.
Therefore, when the enable signal E is 0, the DFF captures the data input to the D terminal at the rising edge of the clock signal CK, outputs the same data as the input data to the Q terminal, and inverts the input data to the QN terminal. Is output.

That is, when the in-phase signal P is 0, the clocked inverter 41 takes in the data input to the D terminal, inverts it, and outputs it. Further, at this time, the transfer gate 44 is in the off state, and the connection of the sequential circuit is released. Therefore, the NOT circuit 42 operates in the clocked inverter 41.
Is transmitted to the transfer gate 45. However, since the transfer gate 45 is in the off state, the data from the NOT circuit 42 is not transmitted to the subsequent circuit. On the other hand, the transfer gate 48 is in the ON state and NOT
The circuits 46 and 47 and the transfer gate 48 form a sequential circuit and hold the past data that has already been input. Therefore, this held data is stored in the NOT circuits 49, 5
It is output from 0 to the Q terminal and the QN terminal.

At the rising timing when the in-phase signal P changes from 0 to 1, the clocked inverter 41 is turned off and the data input from the D terminal is stopped. Further, the transfer gate 44 changes from the off state to the on state, and the NOT circuits 42 and 43 and the transfer gate 44 form a sequential circuit and hold the input data. Here, the input data is the data input to the D terminal when the in-phase signal P is 0. Also,
When the clock signal CK that changes equally to the in-phase signal P rises, the transfer gate 45 changes from the off state to the on state, and the data held in the NOT circuit 42 becomes NO.
Notify the T circuit 46. At this time, the transfer gate 48
Is in the off state, this NOT circuit 46
The data input from the OT circuit 42 is inverted and output.
The NOT circuit 49 further inverts the inverted data of the input data output from the NOT circuit 46. Therefore, the same data as the data input to the D terminal is output from the Q terminal at the timing when the in-phase signal P changes from 0 to 1. Further, the NOT circuit 47 further inverts the inverted data of the input data output from the NOT circuit 46 to make it the same signal as the input data. The NOT circuit 50 is the NOT circuit 47.
Further invert the output of. Therefore, the inverted data of the data input to the D terminal from the QN terminal is the in-phase signal P.
Is output at the timing when changes from 0 to 1.

On the other hand, when the enable signal E is 1, the synchronizing signal generating circuit causes the in-phase signal P to be in the inverted state of the clock signal CK as shown in Table 1. Therefore, when the enable signal E is 1, the DFF fetches the data input to the D terminal at the falling edge of the clock signal CK,
The same data as the input data is output to the Q terminal, and the inverted data of the input data is output to the QN terminal.

That is, when the enable signal E is 1,
The in-phase signal P and the anti-phase signal bar P have values opposite to the values when the enable signal E is 0. Therefore, when the enable signal E is 0, the change of the clock signal CK from 0 to 1 is the same as the change of the in-phase signal P from 0 to 1, but when the enable signal E is 1, it is synchronous. The signal generation circuit causes the rising change of the clock signal CK from 0 to 1 to correspond to the falling change of the in-phase signal P from 1 to 0. In addition, 1 to 0 of the clock signal CK
The change in the rising edge of the in-phase signal corresponds to the change in the rising edge of the in-phase signal P from 0 to 1. That is, the enable signal E is 1
At this time, the clock signal CK is converted into a signal corresponding to the conventional negative clock signal CN by the synchronization signal generation circuit. Since the logic circuit of the DFF shown in FIG. 1A does not change, the DFF has 1 to 0 of the clock signal CK.
At the falling edge of, the same operation as described above is performed. That is, the DFF takes in the data input to the D terminal at the falling edge of the clock signal CK, outputs the input data to the Q terminal as it is, and outputs the inverted data of the input data to the QN terminal.

As described above, according to this embodiment, the synchronization signal generation circuit controls the enable signal E to convert the clock signal CK into the negative clock signal CN. Therefore, the same one DFF inputs data at the rising edge and also inputs data at the falling edge. Therefore, according to this embodiment, a versatile DFF is provided.

For example, by implementing the DFF according to the present embodiment with a gate array, evaluation on the gate array can be easily performed using the scan path method. That is, the DF operating on the rising edge of the gate array
Even if F and DFFs operating at the falling edge are mixed, it becomes possible to operate all the DFFs at the same changing edge of the clock signal CK.

At the time of testing by the scan path method, FIG.
The information holding circuit 61 according to the present embodiment shown in is connected in a shift register mode. This one information holding circuit 61 is based on the circuit configuration shown in FIGS. 1A and 1B and is one primitive. Here, when each DFF is tested by the scan path method, the enable signal E input to the sync signal generation circuit of the DFF operating at the rising edge is set to 0 and input to the sync signal generation circuit of the DFF operating at the falling edge. The enable signal E is set to 1. With this setting, each DFF is all clock signal CK.
The data is input from the D terminal at the timing of rising from 0 to 1. Therefore, each DFF that originally operates at a different edge captures data at the same clock edge, and the data input from Scan In is clock signal CK.
Is sequentially transmitted to the next DFF adjacent to each of the rising edges of the DFF. Therefore, the input data is output to Scan Out in the same manner as when there is a single type of DFF.
Therefore, the DFF that operates at the rising edge as in the past
Therefore, it becomes unnecessary to separately test the DFFs operating at the falling edge and the DFFs, and each DFF can be easily tested in a short time by using the scan path method.

[0029]

As described above, according to the present invention, when the sync signal is changed to the same state as the clock signal by the sync signal generating circuit, the input data has the rising or falling timing of the clock signal. It is captured. Further, when the sync signal is changed to a state opposite to the clock signal by the sync signal generation circuit, the input data is taken in at the other timing of the clock signal.

Therefore, according to the present invention, an FF circuit which operates at both rising and falling edges of a clock signal is realized, and a versatile FF circuit is provided. Therefore, when the FF circuit according to the present invention is applied to, for example, a gate array, a test using the scan path method can be easily performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a DFF according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration when a gate array is configured by using a DFF according to an embodiment and a test is performed by using a scan path method.

FIG. 3 is a circuit diagram showing a configuration of a conventional first DFF.

FIG. 4 is a circuit diagram showing a configuration of a second conventional DFF.

[Explanation of symbols]

41 ... Clocked inverter, 42, 43, 46, 4
7, 49, 50, 52 ... NOT circuit, 44, 45, 48
... Transfer gate, 51 ... EXOR circuit, 53a-
e ... P-channel MOSFETs 54a to e ... N-channel MOSFETs.

Claims (2)

[Claims] 1. A sync inversion circuit that inverts and outputs input data when one state of a sync signal and does not input data when the sync signal is in another state, and an inversion of data from the sync inversion circuit when one state of a sync signal. An input data holding circuit that holds the data that was output and was input during the other state of the synchronization signal; and an input data holding circuit that does not accept the output of the input data holding circuit when the synchronization signal is in one state A switching circuit that takes in the held data, an output data holding circuit that holds the data that was input when the synchronization signal is in one state and inverts the output of the switching circuit when the synchronization signal is in another state, and one state of the control signal And a synchronization signal generation circuit for changing the synchronization signal to the same state as the clock signal and changing the synchronization signal to the opposite state of the clock signal when the control signal is in another state. A flip-flop circuit characterized by: 2. The synchronous inverting circuit comprises a clocked inverter, and the input data holding circuit includes a first inverting circuit having an input connected to the output of the clocked inverter, and the first inverting circuit.
And a second inverting circuit whose input is connected to the output of the inverting circuit, and an input which is connected to the output of the second inverting circuit and whose output is connected to the input of the first inverting circuit A first transfer gate that is turned off and is turned on when the synchronization signal is in another state, and the switching circuit has an input connected to an output of the first inverting circuit and is turned off when the synchronization signal is in one state. And a second transfer gate that is turned on when the synchronization signal is in another state, and the output data holding circuit includes a third inverting circuit having an input connected to the output of the second transfer gate, and the third inverting circuit. A fourth inverting circuit whose input is connected to the output of the third inverting circuit, and an input which is connected to the output of the fourth inverting circuit and whose output is connected to the input of the third inverting circuit Sometimes turned on The synchronization signal generating circuit comprises a third transfer gate which is turned off when the synchronization signal is in another state, and the synchronization signal generation circuit includes an exclusive OR circuit for exclusive ORing the control signal and the clock signal, and the exclusive OR circuit. A fifth inverting circuit for inverting the output of the circuit, wherein the output of the exclusive OR circuit corresponds to one state of the synchronizing signal and the output of the fifth inverting circuit corresponds to the other state of the synchronizing signal. The flip-flop circuit according to claim 1, wherein: