JPH06187231A - Computer system - Google Patents

Abstract

PURPOSE:To reduce the decrease in throughput at the time of access from an input/output device to a storage as to a computer consisting of the input/ output device, plural processors, the storage, and a storage controller which has a buffer for storing copy data of part of data in the storage. CONSTITUTION:An ID adding circuit 310 which adds an access order identifier to an access request, an order guaranteeing circuit 312 which performs control for sending answer data back to an access source according to the access order identifier, a CBS storage detecting circuit 311 which detects the timing of data storage in the buffer 305 from the storage device 4, and a priority level determining circuit 300 provided with a function for stopping the acceptance of the access request based on the detection result of the circuit 311 are provided in the storage controller 3. Consequently, answers in access order are guaranteed, so access is performed in parallel and the data storage in the buffer 305 from the storage device 4 is given priority to the access; and there is no conflict and the decrease of throughput is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly to a computer system having a hierarchical storage device.

[0002]

2. Description of the Related Art Conventionally, in a computer system, a storage device is hierarchized by providing a buffer storage in a processor or a work storage between a buffer storage and a main storage device. (Level near access side)
A RAM (Ran that enables high-speed access with a small capacity)
Dom Access Memory) is used to speed up access to data. Further, as disclosed in Japanese Patent Laid-Open No. 3-228169, in a computer system having a plurality of processors, a buffer storage (communication buffer) having a limited purpose is provided in the storage control device in order to speed up communication between the processors. Sometimes.

Access to a storage device in a computer system having a communication buffer will be described below with reference to FIG. In FIG. 6, 1 is an input / output processing device (I
OP), 2a to 2d are instruction processors (IP0 to IP0)
3), 3 is a storage control device (SC), 4 is a main storage device (M
S). Here, the storage control device 3 is located between the input / output device and the instruction processor and the main storage device 4, and controls access from the input / output device and the instruction processor to the main storage device.

Reference numeral 300 denotes an access request from an input / output device and an instruction processor according to a predetermined priority order.
A priority determination circuit for narrowing down to three, 301 indicates whether the requested data is stored in the communication buffer CBS,
Address array CBA of communication buffer CBS holding information indicating where it is stored, if any
A, 302 is a HIT detection circuit that determines whether or not to access the communication buffer CBS from the search result of the address array CBAA, and 303 is a communication buffer CB described later.
Control circuit for controlling S, control information stack, data stack, etc., 304 is a stack for holding control information related to access to the main storage device MS in the storage control device SC, and 305 is communication. Buffer CB
S and 306 are data stacks for the I / O device IOP, and 307a to 307d are instruction processors IP.
A data stack for 0 to 3; a selector 308 for selecting data to be sent to the input / output processing unit IOP; and 309a to 309d, respectively, an instruction processor IP.
It is a selector for selecting data to be sent to 0 to IP3. The communication buffer (CBS) 305 is
A buffer that can be accessed at high speed, and is provided to speed up communication between instruction processors. Generally, the communication via the memory shared between the instruction processors is performed by using an interlock instruction that guarantees exclusive access to the main memory device MS by each instruction processor. Is stored in the communication buffer CBS, and if the operand is in the communication buffer CBS when the interlock instruction is executed, the communication can be speeded up by reading from the communication buffer CBS.

The processing of the access request in the storage controller SC will be described separately for the case of the access request from the instruction processor and the case of the access request from the input / output device.

(1) Processing for an access request from the instruction processor When the access request from the instruction processor IP0 is selected by the priority determining circuit 300, the address array CBAA is searched. As a result of the search, the HIT detection circuit 302 accesses the communication buffer CBS if the requested data is in the communication buffer CBS, and the main memory M
Do not access S. (However, in order to control the matching of the data between the storage device MS and the communication buffer CBS, the
When the method (a method of simultaneously writing data in the storage device MS and the communication buffer CBS) is adopted, the write request causes access to the main storage device MS even if the data is stored in the communication buffer CBS. On the other hand, as a result of the search, the requested data is the communication buffer CB.
If it is not in S, it depends on whether the requested data is an operand of an interlock instruction. If it is an interlock instruction, a unit of data containing the requested data.
Data (called a block or a line) is the main memory device MS
Is read out from and stored in the communication buffer CBS, and the address of the data is registered in the address array CBAA. After that, access to this block can be made to the communication buffer CBS.
If the requested data is not the operand of the interlock instruction, the main memory MS is accessed. The instruction processors IP1 to IP3 are similarly processed.

(2) Processing for Access Request from I / O Device IOP When an access request from the I / O device IOP is selected by the priority determination circuit 300, the address array CB
AA301 is searched. If the requested data is found in the communication buffer CBS as a result of the search, the HIT detection circuit 302 accesses the communication buffer CBS and does not access the main memory device MS. (However, when the store-through method is used to control the matching of data between the main memory device MS and the communication buffer CBS, even when the write request is stored in the communication buffer CBS, access to the main memory device MS is performed. On the other hand, as a result of the search, if the requested data does not exist in the communication buffer CBS, the main memory device MS is accessed (in the case of access from the I / O device IOP, communication is performed from the main memory device MS). No block transfers to buffer CBS and no registration to address array CBAA).

When the access request selected by the priority determination circuit 300 is sent to the HIT detection circuit 302,
The HIT detection circuit 302 sends the access request source, access type and address, and the search result of the address array CBAA to the control circuit 303 as control information.

In the case of access to the communication buffer CBS, the control circuit 303 sends the control information to the communication buffer CBS, the selectors 308 and 309a to 309.
d, or data stacks 306 and 307a-307d. On the other hand, the main memory M
In the case of access to S, the control circuit 303 stacks the control information on the control information stack 304,
The control information is taken out according to the response from the main storage device MS, and the communication buffer CBS, selectors 308 and 309.
a to 309d or data stack 306 and 307a to 307d. When accessing the main memory (MS) 4,
The control information once stacked on the control information stack 304 is used to control the communication buffer CBS. By this stack operation, when the operand of the interlock instruction described in (1) above is not stored in the communication buffer, the control information is held during the block transfer from the main storage device MS to the communication buffer CBS. .

When the access request from the instruction processors IP0 to IP3 or the input / output device IOP is read, the data read from the main memory MS or the communication buffer CBS is stored in the data 308 or 309a to 309d. The data corresponding to the request source selected from the selectors 306 or 307a to 307d selected by the selector corresponding to the request source.
Sent to the requestor via the data stack.

[0011]

In the above prior art, since the access to the communication buffer CBS is faster than the access to the main memory device MS, if the responses are returned in the order of the end of the access, the access request sequence and the response are returned. The order will not match. Therefore, in the storage controller SC, in order to guarantee that the responses are returned to the input / output device IOP in the order of access requests from the input / output device IOP,
Before accessing the communication buffer CBS, the main memory device MS
Access to the main memory device MS
You have to wait until the access to is finished.

Before the access to the communication buffer CBS from the input / output device IOP, the operand of the interlock instruction is accessed from one instruction processor (any of IP0 to IP3), and the operand exists in the communication buffer CBS. Without the main memory MS to the communication buffer C
When the block including the operand is being transferred to the BS, the block is transferred from the main memory device MS to the communication buffer CBS and written to the communication buffer CBS, and the communication buffer CBS from the input / output device IOP is used. Since there is a possibility of conflicting with the access to the block, the access from the I / O device IOP must be started after the completion of the transfer of the preceding block.

Due to the above-mentioned cause, there is a problem that throughput for access from the input / output device IOP is lowered.

Further, the path from the main memory device MS to the data stacks 306 and 307a to 307d and the data stacks 306 and 3 from the communication buffer CBS.
Since the paths to 07a to 307d are individually provided and selected by the selectors 308 and 309a to 309d, the data in the storage controller SC and the number of signals for controlling the data become enormous, and the physical quantity is increased. However, there is a problem in that the performance is deteriorated due to an increase in the delay time or an increase in the signal delay time. This problem becomes more remarkable as the number of processors sharing the main memory device MS increases.

According to the present invention, parallel access is made to a plurality of storage devices of different hierarchies such as the main storage device MS and the communication buffer CBS (access to the main storage device MS and access to the communication buffer CBS, communication from the main storage device MS. Access at the time of block transfer to the buffer CBS and input / output device IO
Provide a computer system that enables access from P to the communication buffer CBS) within a possible range, and input / output device IO
This is to suppress the decrease in throughput for the access from P to the main memory device MS or the communication buffer CBS.

Another object of the present invention is to send the data received from a plurality of storage devices of different hierarchies, such as the main storage device MS and the communication buffer CBS, which can be accessed in parallel to the request source. It is intended to provide a high-performance computer system by reducing the number of storages in the storage control device, and by suppressing the amount of material and eliminating the delay.

[0017]

To achieve the above object, there is provided a storage control device having a plurality of processors, an input / output device, a storage device, and a shared buffer storage for copying and storing a part of data of the storage device. The storage control device, which is provided between the plurality of processors and the input / output device and the storage device, provides access to the storage device or the shared buffer storage from the plurality of processors or the input / output device. In a computer system that selects, executes and returns a response to the processor or the input / output device that has made the access, an access request identifier indicating an access order is given to an access request from the input / output device to the storage device or the shared buffer storage. Means for adding and detecting that the access to which the access request identifier has been added has ended, Means for returning a response to the input / output device in the order uniquely determined by the access request identifier, and sharing for detecting the timing of storing a part of the data in the shared buffer storage in response to the execution of the access to the storage device The storage control device is provided with buffer storage storage timing detection means and means for stopping the selection of the access request for a period determined in accordance with the detection result of the shared buffer storage storage timing detection means.

Further, in the computer system, when the access to the storage device from the plurality of processors and the input / output device is a write request, if the target of the write request is also stored in the shared buffer storage. A means for writing to both the storage device and the shared buffer storage; and, if an access to the storage device from the input / output device is a read request, whether or not the target of the read request is the shared buffer. Regardless of whether or not the storage device reads the object of the read request and returns a response to the input / output device, a part of the data is stored in the shared buffer storage when the access to the storage device is executed. A shared buffer storage storage timing detection means for detecting timing, and a shared buffer storage storage timing detection means Period which is determined in response to the detection result,
A means for stopping the selection of the access request is provided in the storage controller.

Further, a storage control device having a plurality of processors, an input / output device, a storage device and a buffer storage device is provided, and the storage device and the buffer storage device form a hierarchical structure, and the storage control device comprises the plurality of storage devices. In the computer system for controlling access to the storage device or the buffer storage device from the processor or the input / output device, from the storage device and the buffer storage device forming the hierarchical structure, the storage device capable of parallel access , The system clock nT corresponding to the access
Data transmitted at a pitch of T, converted into a pitch of T, and out of n time zones within a time nT, in a time zone of a predetermined order for each of the storage devices capable of parallel access. In the storage control device, means for outputting data and means for receiving the output of the means and converting the data into nT pitch data and outputting the data to the processor or the input / output device of the access request source Set up in.

[0020]

In the computer system of the present invention, by means for adding an access request identifier to an access request from an input / output device and means for returning a response to the input / output processing device in an order uniquely determined by the added access request identifier. Since the access order can be guaranteed for the input / output device regardless of the order of responses from the storage device or the shared buffer storage, the storage device or shared buffer storage that is originally capable of parallel access is not It becomes possible to issue an access request to the shared buffer storage in parallel without waiting for the end of access. Even when a process of copying a part of the data from the storage device to the shared buffer storage and storing the same is performed, the shared buffer storage storage timing detection means and the access request during the specific timing period corresponding to the detection result. By means of stopping the selection of the storage device, it is possible to prioritize the process of copying a part of the data from the storage device to the shared buffer storage and storing it, so that the storage device can be avoided while avoiding the access conflict of the shared buffer storage. And allows parallel access to shared buffer storage.

Further, in another computer system of the present invention, when the access to the storage device from the plurality of processors or the input / output device is a write request, the target of the write request is also in the shared buffer storage. If stored, means for writing to both the storage device and the shared buffer storage, and if the access from the input / output device to the storage device is a read request,
Regardless of whether the target of the read request is in the shared buffer or not, the means for reading the target of the read request from the storage device and returning a response to the input / output device allows access from the input / output device to be always stored in the storage device. Since it can be performed on the device, the access order to the input / output device can be guaranteed. Even when a process of copying a part of the data from the storage device to the shared buffer storage and storing the same is performed, the shared buffer storage storage timing detection means and the access request during the specific timing period corresponding to the detection result. By means of stopping the selection of the storage device, it is possible to prioritize the process of copying a part of the data from the storage device to the shared buffer storage and storing it, so that the storage device can be avoided while avoiding the access conflict of the shared buffer storage. And allows parallel access to shared buffer storage.

Further, a storage controller having a plurality of processors, an input / output device, a storage device and a buffer storage device is provided, and the storage device and the buffer storage device form a hierarchical structure. In a computer system for controlling access from the processor or the input / output device to the storage device or the buffer storage device, a data sent from a plurality of storage devices of different hierarchies that can be accessed in parallel at a pitch of a system clock nT. Data, converts it to a pitch of T, and n in time nT
Means for outputting data in a time zone of a predetermined order for each storage device among the number of time zones, and the processor of the request source or input by converting the output of the means into the data of nT pitch. By means of outputting data to the output device, the data lines in the storage control device can be shared by a plurality of storage devices of different hierarchies which can be accessed in parallel, and the number of signals in the storage control device is reduced accordingly. As a result, the quantity is reduced and the performance can be improved. When the T pitch data is sent from the storage control device to the access request source processor,
Since the data is converted into the nT pitch data, the portion operating with the clock of the period T can be limited to a very limited part of the system, so that the system design is not made extremely difficult.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a computer system according to an embodiment of the present invention. In FIG. 1, reference numeral 310 denotes an ID adding circuit for adding an access request identifier for identifying an access order to an access request from the input / output device IOP, and 311 is taken out from the control information stack 304 in response to a response from the main memory device MS. Based on the information obtained, the transfer of the block from the main memory device MS to the communication buffer CBS is detected, and the write timing to the communication buffer is determined by the priority determination circuit (access requests are narrowed down according to the priority determined in advance, that is, The CBS storage detection circuit 312 for reporting to the access request selecting circuit 300 returns responses to the input / output device IOP in the order in which the access requests are accepted based on the access request identifier added to the access request from the input / output device IOP. It is an order guarantee circuit that guarantees that. Also, the priority determination circuit 300
To the data stack 306 and the selector 3 is added a function to operate according to the input from the CBS storage detection circuit.
08 is controlled by the order guarantee circuit 312. This will be specifically described in the following embodiments. The other components indicated by the same numbers represent the same contents in FIGS. 1 and 6.

The method of processing the access request from the input / output device IOP in this embodiment will be described by taking the case where the access request from the storage device MS or the communication buffer CBS is read.

When a read request is issued from the input / output device IOP to the storage controller SC and selected by the priority order determination circuit 300, the selected access request (read-out) from the priority order determination circuit 300 to the HIT detection circuit 302. Request) and the identification information of the input / output device IOP are notified.
Then, the HIT search circuit 302 searches the address array CBAA. As a result of the search, if the data corresponding to the access request is in the communication buffer CBS, only the communication buffer CBS is accessed and the main memory device MS is not accessed. If it is not in the communication buffer CBS, the communication buffer CBS is not accessed and only the main memory device MS is accessed.

The HIT detection circuit 302 is a main memory device MS.
Access control (read request), identification information of the input / output device IOP, and control information including information indicating whether to access the main storage device MS or the communication buffer CBS only when accessing The control information including the access request (reading request) is sent to the main storage device MS. The main storage device MS
When the control information is received, the process is executed according to the control information and a response is returned to the storage controller. ID addition circuit 310
Recognizes from the control information sent from the HIT detection circuit 302 that it is an access request from the input / output device IOP, and adds an access request identifier as new information to the control information. This access request identifier is attached so that the order selected by the priority order determination circuit 300 regarding the access request from the input / output device IOP being processed in the storage controller SC can be uniquely known. ID adding circuit 31
The control information to which the access request identifier is added by 0 is sent to the control circuit 303. The control circuit 303 identifies whether the access is to the main storage device MS or the communication buffer CBS based on the received control information. The process after identification is performed as follows.

(1) Access to the main storage device MS The control circuit 303 controls the storage device S from the main storage device MS.
In order to wait for the arrival of the response to C, the control information is temporarily stored in the control information stack 304. When there is a response from the main storage device MS to the control information stack 304, the control information stack 3
The control information is fetched from 04 and sent to the data stack group. Further, the control information including the information indicating that the access request source is the input / output device IOP is sent to the order assurance circuit 312. On the other hand, the data from the main memory device MS is also sent to the data stack group. Sequence guarantee circuit 3
A selector 308 selects the read data from the main storage device MS corresponding to the control information. Further, the order assurance circuit 312 determines the address in the data stack storing the data selected by the selector 308 as the ID addition circuit 3.
The selected data is determined in the data stack by determining based on the control information including the access request identifier added by 10 and pointing the determined address of the data stack to the data stack. Store at address. Further, the order assurance circuit 312 uses the input / output device IO based on the control information including the access request identifier.
It has a function of reproducing the access order from P, retrieves data from the data stack 306 in the order instructed by this function, and outputs the I / O device IO as the access request source.
Send to P. The function of reproducing the access sequence from the input / output device IOP of the sequence assurance circuit 312 is provided by the ID addition circuit 310.
In the case of the case where one integer from 0 to N (N is an appropriate integer) is added as an access request identifier in the order in which the access request is received by the priority determination circuit 300 (for example, until N is reached). Then, a counter from 0 to N is provided, and when the data is stored in the position in the data stack indicated by the counter, the data is input to the I / O device IOP. Is returned, the counter is incremented by 1, and this is repeated thereafter. However, it goes without saying that the function of reproducing the access sequence from the input / output device IOP of the sequence assurance circuit 312 can be realized by a method other than using the counter depending on how the access request identifier is given.

(2) Access to the communication buffer CBS When the data is read from the communication buffer CBS, the main storage device MS is not accessed, so it is not necessary to store the control information in the control information stack 304. There is no. The control circuit 303 gives a read instruction to the communication buffer CBS and sends control information to the data stack group. The data read from the communication buffer CBS is also sent to the data stack group. After that, the data is sent to the input / output device IOP, which is the access request source, by using the access request identifier in the same manner as the access to the main memory device MS.

The above is summarized as follows. Since access to the communication buffer CBS is faster than access to the main memory device MS, even if the priority determination circuit 300 processes the access requests from the input / output devices in the order received, The order of arrival of data to the stack 306 does not always match the order of accepting access requests from the input / output device. However, the order guarantee circuit 312 of the present invention takes out data from the data stack in the order determined by the access request identifier (added by the ID adding circuit) which is the same as the order in which the access requests are received, and the input / output device Since data can be sent to the IOP,
The access order is guaranteed to the I / O device IOP while preventing the drop in throughput by starting the access to the subsequent communication buffer CBS without waiting for the end of the access to the preceding main memory device MS. can do.

Next, as another factor that lowers the throughput of access from the input / output device IOP to the main memory device MS or the communication buffer CBS, part of the data from the main memory device MS is transferred to the communication buffer CBS. A means for solving the problem that the access to the communication buffer CBS from the input / output device IOP must be stopped in order to avoid the access conflict to the communication buffer CBS during the process of copying and storing the data in the storage buffer.

The control information stack 304 is stored in the main memory M.
Upon receiving a response from S, the communication buffer CBS is instructed to write, and the control information is sent to the CBS storage detection circuit 311.
Send to. The CBS storage detection circuit 311 is a main memory device MS.
From the control information retrieved from the control information stack 304 in response to the response from the control information stack 304, it can be seen that an access to the operand of the interlock instruction is being made to the main memory device MS. It is identified that the process of copying and storing a part of it in the communication buffer CBS is performed. Further, the CBS storage detection circuit 311 detects the timing of actually writing the data to the communication buffer CBS from the time relationship between the arrival of the response from the main storage device MS and the arrival of the data from the main storage device MS. To do.

Specifically, when the main memory device MS sends the data for the access request to the communication buffer CBS, it sends a response to each control data to the control stack 304, and after a certain time after sending the response, the data is sent to the communication buffer CBS. send. When the control stack 304 receives the response, the communication stack CB
Instruct S to write the data from the main memory,
It also sends control information to the CBS storage detection circuit 311. Here, depending on the design conditions, the time from the time when the main storage device transmits a response to the time when the control information corresponding to the response arrives at the CBS storage detection circuit, the time from the transmission of the response to the data transmission to the main storage device. Since the time until the data is transmitted from the main storage device and written in the communication buffer is set, the CBS storage detection circuit 311 considers the system clock and determines when the data is actually written in the communication buffer (write timing). ) Can be detected.

Further, the CBS storage detection circuit 311 reports the detected write timing to the communication buffer CBS to the priority order determination circuit 300. Priority decision circuit 3
00 is the communication buffer CB unless the access to the communication buffer CBS is stopped from the write timing to the communication buffer CBS received from the CBS storage detection circuit 311.
The priority determination (selection) of access to the communication buffer CBS is stopped at a specific timing when an access conflict with S occurs. Specifically, the priority determination circuit selects the access request according to the design condition and selects the communication buffer CBS.
Since the time until access (access delay time) is determined, the priority order determination circuit 300 determines from the write timing notified from the CBS storage detection circuit 311 that
Communication buffer CBS before the access delay time
Stop prioritizing (selecting) access to.

Therefore, the CBS storage detection circuit 311 and the priority order determination circuit 300 cooperate to make the communication buffer CB
I / O device I to avoid access contention for S
Since the time for stopping the access from OP to the communication buffer CBS becomes short, during the process of copying a part of the data from the main storage device MS to the communication buffer CBS and storing it, the I / O device IOP transfers the communication buffer CBS. As compared with the case of stopping the access to the main memory device MS or the communication buffer CBS from the input / output device IOP, the throughput of access to the main memory device MS or the communication buffer CBS is not significantly reduced.

Next, another embodiment of the computer system of the present invention will be described. FIG. 2 is a block diagram showing the configuration of the computer system according to the second embodiment of the present invention. In FIG. 1 and FIG. 2, the same numbers represent the same contents. In FIG. 2, reference numeral 313 denotes an address array CBA when the access request from the I / O device IOP is read.
Even if the search result of A indicates that the target data exists in the communication buffer CBS, it makes the HIT detection circuit look like the target data does not exist in the communication buffer. This is a HIT suppression control circuit. The difference between FIG. 2 and FIG. 1 is that the ID addition circuit 310 and the order guarantee circuit 31 of FIG.
2 is not present, but there is the HIT suppression control circuit 313 in FIG. In the computer system shown in FIG. 2, the mechanism for guaranteeing the access order from the I / O device IOP is as follows.

An access request from the I / O device IOP is
In the case of writing, the result of searching the address array CBAA is directly transmitted to the HIT detection circuit 302.
According to the search result, the HIT detection circuit 302 writes the data in both the main memory device MS and the communication buffer CBS if the write request operand is stored in the communication buffer CBS, and the operand must be stored in the communication buffer CBS. For example, the data is written only in the main memory device MS. When data is written in the communication buffer CBS, it is also written in the main memory device MS, so the communication buffer C
The contents of BS and main memory MS always match.

The access request from the I / O device IOP is
In the case of reading, the result of searching the address array CBAA is made to appear as if the operand is not stored in the communication buffer CBS by the HIT inhibition control circuit 313. That is, the operand is the communication buffer CBS
, The operand in the communication buffer CBS is ignored. Therefore, the HIT detection circuit 302
Gives an instruction to read an operand from the main storage device MS. Since the contents of the communication buffer CBS and the contents of the main storage device MS always match, even if the data to be read is stored in the communication buffer CBS, even if it is read from the main storage device MS. There is no mistake in the data.

By doing so, the input / output device I
Since all reading from OP is performed to the main storage device MS, data can be obtained from the main storage device MS in the order in which the HIT detection circuit 302 gives a read instruction to the main storage device MS, and storage control is performed. By sending data to the input / output device IOP in the same order as the device SC,
The access order can be guaranteed for the input / output device IOP. Therefore, from the input / output device IOP to the communication buffer C
Compared with the case where access to the BS is stopped, the access to the main memory device MS from the I / O device IOP is passed.
Does not reduce the put.

The HIT suppression control circuit 313 transmits the search result of the address array CBAA to the HIT detection circuit 302 as it is, regardless of whether the access request is a read or a write, with respect to the instruction processes IP0 to IP3.

In FIG. 2, the HIT suppression control circuit 313
Other than that, the same operation as described in FIG. 1 is performed. Here, also in the computer system of FIG. 2, the CBS storage detection circuit 311 and the priority determination circuit 300 for stopping the priority determination of the access to the communication buffer CBS for a specific period according to the report from the CBS storage detection circuit 311 are required. The reason for this is that there is no access to the communication buffer CBS when the access request is read from the input / output device IOP, but there is access to the communication buffer CBS when the access request is written (from the input / output device IOP). In the case of writing, the communication buffer CBS and the main memory M
To keep the contents of S consistent. ).

FIG. 3 is a block diagram showing the configuration of a computer system according to the third embodiment of the present invention. In the computer system shown in FIG. 6, signal lines of data from the main memory device MS to the data stacks 306 and 307a to 307d, and from the communication buffer CBS to the data stack 30.
6 and 307a to 307d data lines separately required. In the computer system of FIG.
The signal lines of the data from the pitch conversion circuit 314b to the data stack 306 and 307a to 307d are
Pitch conversion circuit 314b and data stack 306
The data read from the main memory device MS and the data read from the communication buffer CBS can be shared by the functions 307a to 307d. Also,
By sharing this signal line, the selectors 308 and 309a to 309 required in the computer system of FIG.
d is unnecessary in the computer system of FIG. Regarding the signal lines of the control information from the control circuit 303 and the control information stack 304 to the data stacks 306 and 307a to 307d, the pitch conversion circuit 314a and the data stacks 306 and 307a to 307d function the data. The same can be said for the signal line of.

FIG. 4 is a diagram for explaining the pitch conversion circuit 314b of FIG. 3 in detail. In FIG. 4, 1 is a register for storing the data sent from the main memory device MS, 2 is a register for storing the data sent from the communication buffer CBS, and 3 is generated by 5 described later. Selector for selecting either the data stored in the register 1 or the data stored in the register 2 according to the selection signal. 4 is a register for receiving the data sent from the selector 3 and 5 is a selection signal for the selector 3. Is a selection signal generation circuit for supplying Here, the registers 1 and 2 are operated by the system clock CLK20 having the cycle 2T, while the register 3 is operated by the clock CLK0 having the cycle T. The selection signal generating circuit 5 is composed of one flip-flop operating with the system clock CLK20, one flip-flop operating with the clock CLK0, an inverter, and an exclusive OR gate. The selection signal generation circuit 5 uses the system clock CLK.
The logic value "0" is output only during the first half time T of the time 2T defined by 20, and the logic value "1" is output during the second half time T. Therefore, the data stored in the register 1, that is, the data sent from the main memory device MS is stored in the register 3 during the first half time T of the time 2T defined by the system clock CLK20. And the latter half of the time T
During the period, the data stored in the register 2, that is, the data sent from the communication buffer CBS is stored. As described above, the register 3 can output two data during the period 2T of the system clock.

FIG. 5 is a time chart showing the operation of the pitch conversion circuit shown in FIG. Main memory MS at a pitch of a cycle of 2T of system clock CLK20
Data sent from A0, A1, A2, ...
Similarly, the data B0, B1, B2, ... That are sent from the communication buffer CBS at a pitch of 2T are selected by the selection signal output from the selection signal generation circuit 5, and are registered in the register 3
By being stored in, the output of the register 3 is converted into the data of the pitch of T.

As described with reference to FIGS. 4 and 5,
Since the pitch conversion circuit 314b shown in FIG. 3 can output two data during the period 2T of the system clock, the pitch conversion circuit 314b outputs the data stack 3 to the data stack 3.
There is only one set of signal lines for transferring data to 06 and 307a to 307d, as shown in the figure. Figure 3
Pitch conversion circuit 314a to data stack 306
Similarly, regarding the signal lines for transmitting the control information to 307a to 307d, only one set is required.

The data stacks 306 and 30 of FIG.
7a to 307d are basically the same as the data stack 306 and 307a to 307d of FIG. 6, but also have a function of returning a response to the access request source at the pitch of the system clock 2T (see FIG. 6 data
In the stack, two pieces of data may be simultaneously stored at the pitch of the system clock 2T, and one piece of data is read at the pitch of the system clock 2T, while the data of FIG. System clock 2 in stack
Data is stored one by one at a pitch T which is half of T, and is read one by one at a pitch of the system clock 2T. ).

As described above, by providing the pitch conversion circuit and sharing the signal line, the number of signals in the storage control device can be reduced, and the physical quantity is reduced by eliminating the need for a selector. be able to. Further, by reducing the physical quantity, it becomes possible to increase the frequency of the system clock, and there is also an effect that a higher performance computer system can be provided.

In FIGS. 3, 4 and 5, the case where the output from the pitch conversion circuit has a pitch of ½ of the system clock has been described. Generally, n is an integer of 3 or more and 1 / n. You may make it output at the pitch of.

[0048]

As described above, according to the present invention, in a computer system provided with a buffer shared by a plurality of processors and input / output devices, which is located in an upper hierarchy of a main storage device, an access order is given to access requests. By means for giving an access request identifier indicating, and means for returning a response to the access request according to the access request identifier,
The access sequence to the storage device seen from the I / O device is
This has the effect of preventing a reverse from the difference between the access time for the main memory and the access time for the shared buffer.

Further, in the case of a write request to the storage device from a plurality of processors and input / output devices, if the write target is also stored in the shared buffer, means for writing to both the storage device and the shared buffer, When the output device issues a read request to the storage device, the input / output device can always access the storage device by means of ignoring the read target stored in the shared buffer. The effect is that responses can be returned in the order of access to.

Furthermore, the means for detecting the timing of storing the data in the shared buffer storage and the means for stopping the determination of the priority order of the access request from the detection result of the timing make it possible to store the data in the buffer from the storage device by the access. While priority is given to avoiding contention for access to the shared buffer storage, parallel access to the storage device and the shared buffer storage is enabled, and there is an effect of reducing deterioration in throughput of access from the input / output device to the storage device.

Furthermore, means for receiving data read at a pitch of nT from different storage layers, converting it to a pitch of T and outputting it (pitch conversion output means), and receiving the output of the means, the nT pitch The means for converting the data into data and outputting the data to the requesting processor or input / output device (data output means) makes it possible to share the data signal line in the storage controller of the computer system. This has the effect of reducing the quantity of signal lines inside. The pitch conversion output means and the data output means have an effect of reducing the physical quantity of the signal line in the storage control device even for the signal line of the data control signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a computer system according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a computer system according to a third embodiment of the present invention.

FIG. 4 is a diagram showing details of a pitch conversion circuit.

FIG. 5 is a time chart showing the operation of the pitch conversion circuit.

FIG. 6 is a block diagram showing a configuration of a computer system according to a conventional technique.

[Explanation of symbols]

1 I / O device (IOP) 2a, 2b, 2c, 2d Instruction processor (IP0, I
P1, IP2, IP3) 3 Storage controller (SC) 4 Main memory (MS) 300 Priority determination circuit 301 Address array (CBAA) 302 HIT detection circuit 303 Control circuit 304 Control information stack 305 Communication buffer (CBS) 306 , 307a, 307b, 307c, 307d Data stack 308, 309a, 309b, 309c, 309d Selector 310 ID addition circuit 311 CBS storage detection circuit 312 Sequence assurance circuit 313 HIT inhibition control circuit 314a, 314b Pitch conversion circuit

Claims (3)

[Claims] 1. A storage control device having a plurality of processors, an input / output device, a storage device, and a shared buffer storage for copying and storing a part of data of the storage device, the plurality of processors and the input / output device. And the storage control device located between the storage device and the storage device selects and executes an access to the storage device or the shared buffer storage from the plurality of processors or the input / output device, and sends a response to the access. In the computer system for returning to the processor or the input / output device, means for adding an access request identifier indicating an access order to an access request from the input / output device to the storage device or the shared buffer storage, and adding the access request identifier Is detected uniquely by the access request identifier. A means for returning a response to the input / output device in accordance with the order; a shared buffer storage storage timing detection means for detecting a timing for storing a part of the data in the shared buffer storage when the storage device is accessed; A computer system characterized in that the storage control device is provided with means for stopping the selection of an access request for a period determined in accordance with the detection result of the shared buffer storage storage timing detection means. 2. The computer system according to claim 1, wherein when the access to the storage device from the plurality of processors and the input / output device is a write request, the target of the write request is also stored in the shared buffer storage. If so, means for writing to both the storage device and the shared buffer storage; and if the access to the storage device from the input / output device is a read request, the target of the read request is the shared buffer. Whether or not the storage device reads the target of the read request from the storage device and returns a response to the input / output device; and a part of the data when the access to the storage device is executed. Shared buffer storage storage timing detection means for detecting timing of storing in buffer storage, and the shared buffer storage storage timing Computer system, wherein a period determined in response to the detection result of the grayed detecting means, and means for stopping the selection of access requests, provided in the storage control device. 3. A storage control device having a plurality of processors, an input / output device, a storage device, and a buffer storage device, wherein the storage device and the buffer storage device form a hierarchical structure, and the storage control device comprises the plurality of storage devices. In the computer system for controlling access to the storage device or the buffer storage device from the processor or the input / output device, in the storage device or the buffer storage configuring the hierarchical structure, from a storage device capable of parallel access, Corresponding to the access, the data sent at the pitch of the system clock nT is received, converted into the pitch of T, and the parallel accessible storage device is included in n time zones within the time nT. Means for outputting data in a predetermined time zone for each time, and an nT pitch for receiving the output of the means De - de to convert the data the access request source processor or input device - computer system characterized by comprising a means for outputting the data to the storage controller.