JPH06187173A - Task activation system - Google Patents

Abstract

PURPOSE:To reduce the management of a CPU, and to attain a high speed task activation with a little overhead by selecting the task number of a queue top in a priority level, and outputting it as task number information. CONSTITUTION:Each kind of signal is transferred between a task activating device 10 and a CPU 20 in a controller. The task activating device 10 is constituted of a task queue file 1, task priority level discriminating circuit 2, task number setting register 3, and task number selecting means 4 such as a multiplexer in an outline. Then, when a task processing in the previous task number is ended by the CPU 20, the set content of a mask register 23 is restored from a saving register 24, and the next task request is issued. Therefore, the task number can be set in the queue file corresponding to the level as a processing for issuing the task request since a task activation event such as an outside interruption or a soft interruption is generated, so that the processing of the CPU 20 can be simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a sequencer,
In a control device using a CPU, such as a vending machine or a fuel injection device of an automobile, a program to be executed is managed as a divided module called a task, and the task start is controlled by software or hardware. Regarding the scheme.

[0002]

2. Description of the Related Art A conventional task activation device manages task activation by a program (Operating System). This is the process of queuing the task number for each level indicating the priority of the task when a task activation event due to an external interrupt or a soft interrupt or a task activation event due to a fixed-cycle interrupt occurs, or for the queue top of each level. The process of determining the priority of the task request and the process of pulling out the task of which the priority is determined from the queue are executed by the program.

[0003]

However, in the conventional task activation device described above, the processing from the task activation event to the task request is performed by the program, which causes overhead, and this overhead is managed. There was a problem that it increased with the number of tasks to be performed.

The present invention greatly reduces the CPU management when a task activation event occurs due to an external interrupt or a soft interrupt, or when a task activation event occurs due to a fixed-cycle program, and a high-speed task activation with less overhead is performed. The purpose is to realize a task activation method that enables

[0005]

FIG. 1 is a block diagram for explaining the principle of the present invention. The configuration of FIG. 1 is for processing a task activation event by an external interrupt or a soft interrupt.

In the figure, 10 is a task starting device of the present invention, which exchanges various signals with the CPU 20 in the control device. The task activation device 10 is roughly
It comprises a task queue file 1, a task priority level judgment circuit 2, a task number setting register 3, and a task number selecting means 4 such as a multiplexer.

The task priority level determination circuit 2 has a task request flag 21 (hereinafter referred to as flag 21), a task priority level register 22 (hereinafter referred to as priority level register 22), and a task priority level mask register 23 (hereinafter referred to as mask register 23). The mask register interrupt save register 24 (hereinafter referred to as save register 24) and the priority encoder 25.

When a task activation event occurs due to an external interrupt or a soft interrupt, the CPU 20 sets the task number in the task queue file 1 managed for each level. At this time, for example, task queue file 1
No. 0 level file has task numbers # 0, # 1, #
2 ... is queued, and task numbers # 10, # 20, # 30 ...
• Task numbers are queued for each priority level, such as is queued. Since the queue is first-in first-out, the task number at the top of the queue is # 0 in the case of the 0-level task queue file.

When the task number is set in the task queue file 1 corresponding to each priority level, the task number of the queue top of each level is set in the task number setting register 3 for each level and the flag is set. 21
Is set for each level.

The mask register 23 is a register in which mask information is set. If the priority sequence of each level is, for example, 0 level> 1 level> 2 level, “0” is set in the mask register 23. When set, all levels below 0 are masked. in this case,
Since all the 0 level, 1 level, and 2 level task requests are masked, no task request is generated even if the task numbers are set in the task number setting register 3 and the respective flags 21 are set. It will be.

Similarly, when "1" is set in the mask register 23, 1-level and 2-level task requests are masked, and when "2" is set, only 2-level task requests are masked. When "3" is set, task requests of all levels are not masked.

The priority encoder 25 determines the priority based on the mask information of the mask register 23 and the flag set information of the flag 21, and sets the priority level register which is not masked and has a high priority. 22 and outputs a task request to the CPU 20.

When the CPU 20 receives this task request, the contents of the priority level register 22 are read out and the level of the task request is known from the contents. Then, when the CPU 20 reads the task number from the task number setting register 3, the task number selecting means 4 automatically selects the task number at that time.

Further, the save register 24 temporarily fetches the mask information set in the mask register 23 until the task number is read by the CPU 20.

[0015]

When a task event such as an external interrupt or a soft interrupt occurs, the CPU sets the task number in the task queue file 1 according to the priority level of the task. Then, the task number of the queue top of each level is set in the task number setting register 3 for each level and the corresponding task request flag is set.

Then, the priority encoder 25
Determines the priority of the level based on the mask information and the flag setting information, sets the highest-priority level that is not masked (here, 1 level) in the priority level register 22, and sets the CPU 20 at the same time. Issue a task request to.

When the CPU 20 receives this task request,
The contents (1 level) of the priority level register 22 are read to know that there is a 1 level task request. Then, the task number selecting means 4 causes the priority level register 2 to
1 from the task number setting register 3 in response to the signal from 2.
The task number of the queue top of the level (this is called task number # 10) is selected, and the task number # 10 is given to the CPU 20.

By reading the task number in this way, the task activation device 10 saves the set contents of the mask register 23 up to this point in the save register 24.

Then, the CPU 20 sends the previous task number # 1.
When the task processing of 0 is completed, the set contents of the mask register 23 are restored from the save register 24, and the next task request is generated.

Therefore, after a task activation event such as an external interrupt or a soft interrupt occurs, as a process for generating a task request, it suffices to set the task number in the queue file corresponding to the level.
The processing of U can be simplified, and high-speed task activation with less overhead becomes possible.

FIG. 2 shows a preset programmable cycle, and when a task activation event of a fixed cycle task occurs, the task number is automatically set in the task queue file 1 shown in FIG. 1 according to the priority level. FIG. 3 is a block diagram showing a fixed-cycle task activating means for performing.

The fixed-cycle task starting means includes a fixed-cycle timer 31 capable of setting a base time T of a fixed-cycle interrupt,
It is composed of a periodic task activation circuit 41 provided for each level and for each task number of that level, and the task activation device 10 shown in FIG. Note that in FIG. 2, the fixed-cycle task starting circuit 41 only shows the fixed-cycle task starting circuit corresponding to a certain task number.
The fixed-cycle task activation circuits corresponding to other task numbers have the same configuration.

The fixed cycle task starting circuit 41 comprises a task number register 51 for setting a task number, a cycle setting register 52 for setting the task cycle N, and a down counter 53 as a counting means.

The CPU 20 initializes the fixed-cycle task activation circuit 41 for the fixed-cycle task.
That is, in the processing of the CPU 20 as initial setting, the base time T of the interrupt cycle is set in the fixed cycle timer 31, the task number is set in the task number register 51, and the cycle N is set in the cycle setting register 52.
When this cycle N is set, the contents are down counter 53.
Is also set. At this time, the cycle in which the fixed-cycle interrupt task is activated is determined by N × T.

The task number generated from the fixed cycle task activation circuit 41 is stored in the corresponding queue file of the task queue file 1 shown in FIG. As described above, the CPU processing performed at initialization as the initial setting sets the base time T, the task number, and the cycle N, and then issues the fixed cycle timer control command to enable the fixed cycle timer 31. To This allows
The content (N) of the down counter 53 is decremented in synchronization with the count clock (clock cycle T) output from the fixed cycle timer 31. That is, N is decremented by 1 at every cycle period T of the clock. When the down counter 53 reaches 0, the task number set in the task number register 51 is set in the queue file of the corresponding level of the task queue file 1 shown in FIG. Then, the cycle N is set again in the down counter 53, and the above operation is repeated. Therefore, the task activation cycle is N × T.

After the task number is set in the task queue file 1, the CP is executed by the operation described in FIG.
A task request is output to U20. Therefore,
When a task activation event of a fixed-cycle task occurs at a preset programmable period, the task number is automatically set in the corresponding queue file without managing whether the task activation event occurs or not. can do.

[0027]

EXAMPLES Examples of the present invention will be described below. FIG. 3 is a block diagram of an embodiment (hereinafter, referred to as a first embodiment) of a task starting means for a task starting event caused by an external interrupt or a soft interrupt, and FIG. 1 explained on the principle of the present invention.
It corresponds to. In the figure, 10 is a task activation device, which exchanges various signals with the CPU 20 in the control device.

As shown in FIG. 1, the task activating device 10 is composed of a task queue file 1, a task priority level judging circuit 2, a task number register 3, and a multiplexer (MPX) 4 as a task number selecting means. Has been done.

In the task queue file 1, for example, the order of occurrence of 1-level task events is task number # 1.
When the order is 0, # 11, # 12, ..., The 1-level queue file 1 1 of the task queue file ₁ is stored as shown in FIG. In addition, when a task activation event such as an external interrupt or a soft interrupt occurs, the CPU 20 sets the task number in the task queue file 1 according to the task priority level. For example, task queue file 1 0 level file 1 ₀
The task number generation order # 0, # 1, # 2, ... are queued, one level area 1 # 10 as described above in _1, # 11, # 12, ... are queued ,
The 2-level file 1 ₂ # 20, # 21, # 22, &
.. are queued, and task numbers are queued for each level.

[0030] In addition, the queue since has become a first-in-first-out, take a 0 level file 1 ₀ as an example, the task number of the queue top in the 0 level file 1 ₀ will be # 0.

Further, the task priority level determination circuit 2
Is composed of a flag 21, a priority level register 22, a mask register 23, a save register 24, and a priority encoder 25.

When the task number is set in the task queue file 1 corresponding to each level as described above, the task number of the queue top of each level is set in each level area of the task number setting register 3. For example, in the 0-level area 3 ₀ of the task number setting register 3, task number # 0 and in the 1-level area 3 ₁ task number # 1
0,2 The level region 3 ₂ task number # 20, the task number of the queue top at that time at each level so that is set to the corresponding level region.

At the same time when the task number is set in the task number setting register 3, the flags 21 are set to the respective levels. That is, when task numbers are queued in the 0 level file 1 ₀ , 1 level file 1 ₁ and 2 level file 1 ₂ of the task queue file 1, the flags of the corresponding levels are set. For example, when a task number is queued in the 0 level file 1 ₀ , the 0 level flag 21 ₀ is set, and when a task number is queued in the 1 level file 1 ₁ , the 1 level flag 21 ₁ is set, When the task number is queued in the 2 level file 1 ₂
The second level flag 21 ₂ is set.

Further, the mask register 23 is set with mask information as described above. Here, 0 level,
Assuming that the priority levels of the first level and the second level are 0 level> 1 level> 2 level, when "0" is set in the mask register 23, all levels below the 0 level are masked. 0 level, 1 level, and 2 level task requests are masked. When the task request is masked, even if the task number is set in the task number setting register 3 and the task request flag 21 is set, the masked task request does not occur.

When the CPU 20 reads the task number, the save register 24 stores the mask register 2 up to that point.
3 is a register for temporarily taking in the mask information of No. 3. For example, if "3" is set in the mask register 23 until the task number is read by the CPU 20,
After reading the task number of the CPU 20, the mask register 2
The contents of 3 are 0 level areas 24 ₀ and 1 of the save register 24.
It is saved in any of the level areas 24 ₁ and 24 ₂ (the level area corresponding to the task number read by the CPU 20).

The priority encoder 25 uses the flag information of the task request flag 21 and the mask register 23.
The highest priority level is output to the priority level register 22 according to the mask information of the
It is output to U20.

The operation of the above arrangement will be described below. When a task event such as an external interrupt or a soft interrupt occurs, the CPU 20 sets the task number in the task queue file 1 according to the priority level of the task. As a result, the task number of the queue top for each level is set in the task number register 3 for each level, and the task request flag 21 for each corresponding level is set. This will be described using a specific example.

Here, tasks are not queued in the 0 level file 1 ₀ of the task queue file _1, and task numbers # 10 and # 1 are stored in the 1 level file 1 1.
1 and # 12 are queued and 2 level files 1 ₂
It is assumed that task numbers # 20, # 21, and # 22 are queued in the. Further, it is assumed that "3" is set in the mask register 23.

Since no tasks are queued in the 0 level file 1 ₀ of the task queue file 1 as described above, the 0 level area 3 ₀ and the 0 level flag 21 ₀ of the task number setting register 3 are not set. On the other hand, the task number # 10, which is the queue top of the 1-level file 1 ₁ of the task queue file ₁ , is set in the 1-level area 3 ₁ of the task number setting register 3, and similarly, the 2-level area 3 ₂ has 2 levels. The task number # 20 which is the queue top of the file 1 ₂ is set. At the same time, the 1st level flag 21 ₁ and the 2nd level flag 21 ₂
Is set.

In such a state, the priority
The encoder 25 uses the mask information of the mask register 23 and the mask information.
Flag information of the disk request flag 21, that is, in this case
Is unmasked for all levels of task requests, and
Level 2 and Level 2 flags 21 ₁, 21₂Is set
The priority of 1 level> 2 levels
Determine that it is This allows priority level cash register
1 level is set in the star 22 and the CPU 20
The task request is output to.

When the CPU 20 accepts this task request, the priority level register 22 is read to know that there is a 1-level task request. Generally, the CPU 20 uses the task level for task control.

When the CPU 20 reads the task number from the task number setting register 3, the multiplexer 4 receives the contents of the priority level register 22, and in this case, automatically selects the task request number register of 1 level. The task number # 10 can be obtained.

Since the task number is read from the task starting device 10 in this way, the task starting device 1
0 saves the previous contents of the mask register 23 to the 1-level area 24 ₁ of the save register 24, sets “1” to the mask register 23, and further saves the 1-level area 3 ₁ of the task number setting register 3 The contents and the contents of the 1st level flag 21 ₁ of the task request flag 21 are cleared.

After that, one level of the task queue file 1
File 1₁Queue Top Tas at that time
The task number # 11 is the 1st level area of the task number setting register 3.
Area 3 ₁Is set to 1 and the task request flag 21 is set to 1
Level flag 21₁Is set. But at this time
Set the task priority level mask register to "1".
Since 1 level and 2 levels are masked,
Bells and level 2 task requests will not be output.
It However, the 0 level is not masked at this time.
Then, if 0 level cue file 1₀The task number is
If set, a 0 level task request is generated
It

Then, the CPU 20 uses the task number # 1.
When the process of 0 is completed,
A restore instruction for the mask register 23 is issued to the save register 24. As a result, the mask information “3” stored in the 1-level area 24 ₁ of the save register 24 is returned to the mask register 23. In this way, the mask information "3" before the task number # 10 is read by the CPU 20 is returned to the mask register 23, and the next task request is generated. In this case, the task number # 11, which is the queue top at the 1st level at that time, is generated as the task request. The generation of the task request of the task number # 11 is performed in the same operation process as the case of the task number # 10.

As described above, in this embodiment, the task number is set in the queue corresponding to the level as the processing for generating the task request after the task activation event such as the external interrupt or the soft interrupt occurs. Processing is possible, and high-speed task startup with little overhead becomes possible.

FIG. 5 shows the task queue file 1 described in the first embodiment in which the task number is changed according to the priority level when a task activation event of a fixed-cycle task occurs at a preset programmable period. An embodiment (hereinafter, referred to as a second embodiment) of the means for automatically setting to the first embodiment will be described, and corresponds to FIG. 2 described in the principle of the invention.

In FIG. 5, the same parts as those in FIGS. 2 and 3 are designated by the same reference numerals. That is, 10 is the task activation device described in the first embodiment, and its configuration is the same as that in FIG. 3. Therefore, in order to prevent complication of FIG. 3, each component is shown in FIG. Absent.

In FIG. 5, reference numeral 30 is a fixed-cycle interrupt control circuit, and generally, a fixed-cycle timer 31 capable of setting the base time T of the fixed-cycle interrupt, and 0 level, 1 level, and 2 level levels. Each periodic task activation circuit group 40 is provided for each.

Each of the above-mentioned fixed-cycle task start-up circuit groups 40 has a fixed-cycle task start-up circuit 4 corresponding to the task number of each level.
1 _0, 41 _1, has a configuration in which ... is provided.
For example, taking the 0 level fixed cycle task activation circuit group 40 as an example, the 0 level task number # 0,
# 1, ... for each fixed-cycle task activation circuit 40 ₀ , 40
₁ , ... are provided. Each of the periodic task activation circuits 40 ₀ , 40 ₁ , ... Has a task number register 5 for setting a task number, as described with reference to FIG.
1 and cycle setting register 5 that sets the cycle N of the task
2, and a down counter 53.

When the cycle N is set in the cycle setting register 52, the content (cycle N) is also set in the down counter 53. Next, the operation of this structure will be described with reference to the time chart of FIG. First, the CPU 20 sets the base time T of the interrupt cycle in the fixed cycle timer 31, and also performs the fixed cycle task initial setting for the fixed cycle task activation circuit group 40 for each level.
For example, the initialization of the task number # 0 of the 0-level fixed cycle task activation circuit group 40 will be described as an example. First, the task number is set in the task number register 51 and the task cycle N is set in the cycle setting register 52.
(Here, N = 4) is set. When the task cycle N is set, its contents are also set in the down counter 53.

Such initialization is similarly performed for other fixed-cycle task activation circuits. When the initialization of all fixed-cycle tasks is completed, the fixed-cycle timer 31 is activated by the CPU 20 to specify the fixed-cycle timer 31. To enable. The processing up to this point is the processing of the CPU 20 as the initial setting.

When the fixed-cycle timer 31 becomes valid, the count clock signal CL is issued after the time T, which causes
The down counter 53 is decremented by 1. That is, since the down counter 53 is set to "4", it is decremented by 1 by the first count clock signal CL and the content of the down counter 53 becomes "3". In this way, when the count clock from the fixed cycle timer 31 decrements one by one and the content of the down counter 53 becomes "0", the task number # 0 stored in the task number register 51 becomes the task level. It is set in the corresponding queue file 1, and a task request is generated by the processing procedure according to the first embodiment as described above.

At the same time, the value N of the cycle setting register 52 is set again in the down counter 53, and the same as above.
The operation of counting down by the count clock from the fixed cycle timer 31 is repeated. Therefore, if T = 100 msec, the cycle at which the fixed-cycle interrupt of the task number # 0 is activated is 400 msec according to N × T (N = 4 in this case).

When the time (N × T) set in this way elapses, a task start event automatically occurs and C
A task number can be set in a queue file managed for each level without any operation from the PU, and after being set in the queue file, a task request is generated in the processing according to the first embodiment. You can

In the second embodiment, the down counter 53 is always in the valid state and the fixed period timer 3
Although the example in which the down counter 53 is decremented by the count clock output when 1 becomes valid is shown, the count clock of the fixed-cycle timer 31 is always output and the down counter 53 is not limited to this method.
Alternatively, a system may be used in which the down clock 53 is enabled and the down counter 53 is enabled to decrement by the count clock.

[0057]

According to the present invention, the task number is set in the queue file corresponding to the level of the task as the processing for generating the task request after the task activation event by the external interrupt or the soft interrupt occurs. However, the CPU processing for the task queue management, the priority determination in consideration of the interrupt task, and the interrupt mask register control becomes unnecessary, and the task can be started at high speed.

Further, it becomes unnecessary to manage whether or not such a task activation event occurs with respect to the task activation event by the fixed cycle program. Furthermore, after a task activation event occurs, the task number can be automatically set in the queue file according to the level of the task, so high-speed task activation with less overhead becomes possible.

[Brief description of drawings]

FIG. 1 is a configuration diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram illustrating the principle of the present invention in the case of a task activation event by a fixed cycle program.

FIG. 3 is a configuration diagram illustrating a first embodiment of the present invention.

FIG. 4 is a diagram illustrating a task queue file in the example.

FIG. 5 is a configuration diagram illustrating a second embodiment of the present invention.

FIG. 6 is a time chart explaining the operation of the second embodiment.

[Explanation of symbols]

 1 task queue file 2 task priority level determination circuit 3 task number setting register 4 task number selecting means 31 fixed period timer 51 task number register 52 period setting register 53 counting means (down counter)

Claims (4)

[Claims] 1. A task queue file (1) for queuing a task number for each priority level according to the priority of the task, and a task number is queued for this task queue file (1) according to the level. Then, the task number register (3) in which the task number of the queue top of each level is set for each level and the priority of each level are determined and the priority level information with the highest priority at that time is output. Task priority level determination circuit that outputs a task request together with (2)
And receiving the priority level information from the task priority level determination circuit (2), the task number setting register (3)
The task number selecting means (4) for selecting the task number of the queue top of the above priority level among the task numbers of the queue top for each level set in the above and outputting it as the task number information, A featured task activation method. 2. A task queue file (1) for queuing the task number for each priority level according to the priority of the task, and the task number is queued for this task queue file (1) according to the level. Then, the task number setting register (3) in which the task number of the queue top of each level is set for each level and the priority of each level are judged and the priority level information with the highest priority at that time is output. Task priority level determination circuit (2) that outputs a task request
And receiving the priority level information from the task priority level determination circuit (2), the task number setting register (3)
Task number selecting means (4) for selecting the task number of the queue top of the above priority level and outputting it as the task number information among the task numbers of the queue top for each register set in the A fixed period timer (31) capable of setting the time T, a task number register (51) provided for each task of each level and setting each task number, and a task number register for each task of each level. , A task cycle setting level (52) for setting each task cycle N, and the task cycle N in synchronization with a count clock output by the fixed cycle timer (31) provided for each task of each level. Counting means (53) for counting, and when the count value of the counting means (53) counts N, the corresponding task number The task starting method, characterized in that set to the corresponding level area of the task queue file (1). 3. The task priority level determination circuit (2)
Is a task request flag (21) that sets a flag of a corresponding level when a task number is queued in the task queue file (1) and a masking is possible for each level. A task priority level mask register (23) in which mask information for masking all priority levels below that level is set, mask information of this task priority level mask register (23) and flag of the task request flag (21). A priority encoder (25) that determines a task level priority based on the information, outputs the highest priority level information at that time, and outputs a task request
And the task priority level register (22) in which the priority information obtained by the priority encoder (25) is set, and the external device such as the CPU receives the above task request and reads out the task number. 3. The task starting method according to claim 1, further comprising: a mask information save register (24) for saving the mask information of the task priority level mask register (23) up to. 4. The mask information saved in the mask information save register (24) is stored in the task priority level mask register (2) after task processing is completed by an external device such as a CPU.
The task starting method according to claim 1 or 2, wherein the task is returned to step 3).