JPH06181478A - Rds detection circuit - Google Patents

Abstract

PURPOSE:To control a PLL circuit with a stable RDS lock detection section by making the detection of RDS stable. CONSTITUTION:A latch circuit 6 latching an RDS lock detection section is provided between a PLL circuit 3 and an RDS lock detection section 4 in this configuration and the PLL circuit 3 is controlled by using an AND between a latched low level RDS lock detection signal and an initial synchronization identification signal. Even when the initial synchronization identification signal is fed from a clock recovery section 2 to an AND gate 7, since the RDS lock detection signal is at a low level, the initial synchronization identification signal is not fed to the PLL circuit 3 and the PLL circuit 3 is not frequently switched to the initial synchronization mode and the RDS lock detection signal is made stable.

Description

Detailed Description of the Invention

[0001]

[Industrial application] ARI as a traffic information system
The present invention relates to an FM radio receiver capable of demodulating an RDS (Radio Data System) signal transmitted via (Autofahrer Rundfunk Information) broadcasting, and more specifically to an RDS lock detection signal detection circuit used for demodulating an RDS signal. .

[0002]

2. Description of the Related Art Conventionally, ARI broadcasting has been known as a traffic information system for alleviating traffic congestion.
In this ARI broadcasting system, an FM radio station that broadcasts traffic information can be identified by always adding a 57 kHz subcarrier to its radio wave. Furthermore, the start and end of traffic information and the target area can be distinguished by the DK and BK signals in which the subcarrier is amplitude-modulated at a specific frequency.

Further, there is known FM multiplex data broadcasting (RDS) which is a broadcasting system in which a 57 kHz subcarrier is added to an FM radio wave to multiplex digital data for channel selection and the like. The data multiplexed in this RDS broadcast is
It consists of 104-bit groups, and various messages whose main purpose is the channel selection function have been standardized.
The transmission speed of RDS data is 1.1875.
Two-phase PSK (Phase Shift Keying) modulation of the kHz clock. Further, the subcarrier (57 kHz) is amplitude-modulated with carrier suppression type by the two-phase PSK signal, and the double sideband (DSB) signal is multiplexed with the voice signal and transmitted. Here, the subcarrier of the RDS data is set in the in-phase or quadrature phase relationship with the third harmonic of the pilot signal (19 kHz) indicating stereo broadcasting. Further, in broadcasting where compatibility with the ARI signal is required, the RDS modulated signal and the ARI signal have the same frequency and are always set in a quadrature phase relationship, and are simultaneously transmitted.

FIG. 2 shows an FM signal with an RDS modulation signal and an AR signal.
FIG. 3 shows a spectrum when the I signal is multiplexed, and FIG.
1 is a schematic block diagram of the basic configuration of an FM multiplex data broadcast receiver.

As shown in FIG. 2, the RDS modulation signal is 57 kH.
It is distributed at a low level near the z subcarrier and does not affect the voice band. In the FM multiplex data broadcast receiver, as shown in FIG. 3, in the FM multiplex broadcast received by the antenna 101, the desired station is selected by the front end 102, the IF (intermediate frequency) amplifier 103, the FM detector (DET) are selected. ) 104 and a multiplexer (MPX) demodulation circuit 105, the audio signal is separated into L (left) and R (right) channel audio signals and output in the case of stereo broadcasting. The output signal from the IF amplifier is also supplied to the controller 110 via the level detection circuit 113. The level detection circuit 113 outputs an SD (Signal Detect) signal when the signal level has not reached a certain value. Further, the detection output of the FM detector 104 is supplied to the filter 106, and the RDS modulation signal of the 57 kHz subcarrier is separated. The separated RDS modulated signal has its clock regenerated by an RDS decoding clock regenerator 107 to demodulate RDS data. Further, the output signal of the RDS decode / clock regenerator 107 is the group / block sync / error detector 108 and the error correction circuit 109.
Is supplied to the controller 110 via the, the code information is analyzed, and stored in the memory 111 such as a RAM. At this time, the controller 110 performs a tuning operation on the front end 102 based on a tuning command from the operation unit 112. The RDS data is reproduced by the FM multiplex data broadcasting receiver having the above-mentioned configuration.

FIG. 4 shows a waveform diagram for explaining the principle of extracting the RDS clock signal. Two-phase PSK signal (FIG. 4 (b)) included in the RDS modulation signal (FIG. 4 (a))
Is the periodicity of the RDS clock signal (arrow in FIG. 4 (c))
Is hidden, and RD is extracted by extracting this periodicity.
The S clock signal can be reproduced.

Therefore, the time when the two-phase PSK signal is inverted is identified (FIG. 4 (c)), and then the RD is detected by the window signal (FIG. 4 (d)) synchronized with the RDS clock signal.
The periodicity of the S clock signal is extracted (FIG. 4 (e)), and the RDS clock signal is reproduced from this signal (FIG. 4).
(F)).

FIG. 5 is a block diagram showing the configuration of a conventional RDS detection circuit. This conventional RDS detection circuit includes a clock recovery unit 2, a PLL circuit 3, and an RDS lock detection unit 4. Here, the PLL circuit 3 has a multiplier 3a, a sequential loop filter 3b, and a variable frequency divider (VCO) 3c.

The specific operation will be described below. The clock recovery unit 2 converts the two-phase PSK signal (FIG. 4B) input from the input terminal 1 into the RDS clock signal (FIG. 4F).
To extract. At this time, the PLL circuit 3 outputs the R signal included in the window signal (FIG. 4D) and the two-phase PSK signal.
The periodicity of the DS clock signal (FIG. 4C) is always synchronized. The multiplier 3a compares the phase of the reference clock signal supplied from the variable frequency divider (VCO) 3c with the RDS clock signal reproduced by the clock reproduction unit 2. The output of the multiplier 3a is supplied to the variable frequency divider (VCO) 3c via the sequential loop filter 3b, and controls the variable frequency divider (VCO) 3c. When there is no phase difference between the reference clock signal and the regenerated RDS clock signal, the PLL circuit 3 enters the locked state. At this time, a signal orthogonal to the reference clock signal input to the multiplier 3a is used as a window signal (FIG. 4D), and the window signal is a signal obtained by extracting a change point of the two-phase PSK signal (FIG. 4).
By multiplying (c)), a stable RDS clock signal (FIG. 4 (e)) can be extracted.

The RDS lock detecting section 4 receives the RDS clock signal reproduced by the clock reproducing section 2 and a variable frequency divider (V
The phase difference from the reference clock signal supplied from the CO) 3c is detected to determine whether or not the PLL circuit 3 is locked. When locked, the RDS lock detection signal is output.

FIG. 6 shows a state (a) in which the RDS clock signal can be extracted and a state (b) in which the RDS clock signal cannot be extracted. In the initial state immediately after the two-phase PSK signal is input, the phase relationship between the change point of the two-phase PSK signal and the window signal is such that the clock signal can be extracted (see FIG. 6).
There are two cases, (a)) and a state where it cannot be taken out (FIG. 6 (b)).

A state in which the clock signal can be taken out (see FIG. 6).
In the case of (a)), the clock reproduction unit 2 of FIG. 5 reproduces the RDS clock signal from the signal extracted from the window signal, and after the PLL circuit 3 is locked, the RDS lock detection unit 4 outputs the RDS lock detection signal. Output and AND gate 7
Supply to. At this time, the RDS lock detection signal is at a low level.

However, in the case where the clock signal cannot be taken out (FIG. 6 (b)), the clock reproduction unit 2 of FIG. 5 reproduces the RDS clock signal because the signal extracted by the window signal is discontinuous. I can't. Therefore, the clock reproduction unit 2 detects the discontinuity of the extracted signal and supplies the initial synchronization identification signal to the AND gate 7. The AND gate 7 supplies the initial synchronization identification signal to the variable frequency divider (VCO) 3c of the PLL circuit 3 when the RDS lock detection signal is at a high level, that is, when the lock of the PLL circuit 3 is not established. At this time, the PLL circuit 3 switches to the initial synchronization mode, and this initial synchronization mode continues until the state in which the clock signal cannot be extracted (FIG. 6B) switches to the state in which the clock signal can be extracted (FIG. 6A). . Clock signal can be taken out (Fig. 6)
When switching to (a)), there are no discontinuities in the extracted signal, and the clock regeneration unit 2 in FIG. 5 regenerates the RDS clock signal from the signal extracted from the window signal,
After the PLL circuit 3 is locked, the RDS lock detector 4 outputs the RDS lock detection signal.

As described above, in any of the above cases, the RDS lock detection unit 4 finally outputs the RDS lock detection signal.

[0015]

However, in the case of the conventional RDS detection circuit described above, the initial synchronization identification signal is directly PL
It is supplied to the L circuit 3 for control. Therefore, the external noise such as multipath noise disturbs the RDS modulation signal,
When the periodicity of the RDS clock signal in the two-phase PSK signal is disturbed, the initial synchronization identification signal is supplied to the PLL circuit 3,
The PLL circuit 3 switches to the initial synchronization mode. When the mode is switched to the initial synchronization mode, the lock of the PLL circuit 3 is forcibly released, and the RDS lock detection signal becomes unstable. In particular, when the external noise extends for a long time, it is difficult to obtain a stable RDS lock detection signal.

It is an object of the present invention to stabilize RDS lock detection and control a PLL circuit with a stable RDS data signal.

[0017]

[Means for Solving the Problems] To achieve this purpose,
The RDS lock detection circuit according to the present invention reproduces and outputs an RDS clock signal for demodulating RDS data from an RDS signal, and outputs an initial synchronization identification signal when the RDS clock signal cannot be reproduced. ), And a PLL for detecting the phase difference between the reference clock signal supplied from the built-in reference clock generation means (3c) and the RDS clock signal, and synchronizing the operation timing of the radio receiver with the RDS clock signal.
The circuit (3) and the PLL by detecting the phase difference between the RDS clock signal and the reference clock signal.
An RDS detection circuit comprising: an RDS lock detection unit (4) for determining whether the circuit is locked to the phase of the RDS clock signal and outputting an RDS lock detection signal when the circuit is locked; A latch circuit (6) for latching the RDS lock detection signal, and a latched R
A control means (7) for controlling the PLL circuit (3) using a logical product of the DS lock detection signal and the initial synchronization identification signal is provided.

[0018]

According to the structure of the present invention, the latch circuit (6) for latching the RDS lock detection signal is provided between the PLL circuit (3) and the RDS lock detection section (4) and latched. The PLL circuit (3) can be controlled by using the logical product of the low level RDS lock detection signal and the initial synchronization identification signal. Clock recovery unit (2)
Even if the initial synchronization identification signal is supplied from the AND gate (7) to the AND gate (7), since the RDS lock detection signal is at the low level, the initial synchronization identification signal is not supplied to the PLL circuit (3) and the PLL circuit (3) Can stabilize the RDS lock detection signal without switching to the initial synchronization mode frequently.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a block diagram of the configuration of an RDS detection circuit according to the present invention. In the drawings, the same components as those in FIG. 5 are designated by the same reference numerals.

In the configuration of the RDS detection circuit according to the present invention,
A latch circuit 6 is provided between the RDS lock detector 4 and the AND gate 7 of the conventional RDS detector circuit shown in FIG. The operation of the RDS detection circuit according to the present invention will be described below.

The operation of the RDS detection circuit according to the present invention is 2
The operation is the same as the operation of the conventional RDS detection circuit from the initial state immediately after the input of the phase PSK signal to the establishment of the lock of the PLL circuit, and the description thereof will be omitted. When the clock signal is reproduced from the clock reproduction unit 2 and the lock of the PLL circuit 3 is established, R output from the lock detection unit 4 is output.
The DS lock detection signal becomes low level, and the low level RDS lock detection signal is latched by the latch circuit 6. As described above, after the PLL circuit 3 is locked, the latched low level RDS lock detection signal is supplied to one input terminal of the AND gate. Therefore, even if the RDS modulation signal is disturbed by external noise after the lock is established, the periodicity of the RDS clock signal in the two-phase PSK signal is disturbed, and the initial synchronization identification signal is supplied to the other input terminal of the AND gate 7, R supplied to the input terminal of
Since the DS lock detection signal is at the low level, the initial synchronization identification signal is not supplied to the PLL circuit 3.

For resetting the latch circuit 6, the SD signal supplied from the SD input terminal 8 when reception becomes impossible is used.

[0023]

According to the configuration of the present invention, the conventional RD
By providing the latch circuit in the S detection device, the PLL circuit 3 can be controlled by taking the product of the latched low level RDS lock detection signal and the initial synchronization identification signal. As a result, even if the RDS modulation is disturbed by the external noise after the PLL circuit 3 is locked and the periodicity of the RDS clock signal is disturbed, and the initial synchronization identification signal is supplied from the clock recovery unit 2 to the AND gate 7, the RDS lock detection is performed. Since the signal is low level, the initial synchronization identification signal is not supplied to the PLL circuit 3. Therefore, the PLL
Circuit 3 does not switch to the initial synchronization mode
The lock detection signal can be stabilized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an RDS detection circuit according to the present invention.

FIG. 2 is a diagram showing a spectrum when an RDS modulation signal and an ARI signal are multiplexed on an FM signal.

FIG. 3 is a schematic block diagram showing a basic configuration of an FM multiplex data broadcast receiver.

FIG. 4 is a waveform diagram for explaining the principle of extracting an RDS clock signal.

FIG. 5 is a block diagram showing a configuration of a conventional RDS detection circuit.

FIG. 6A is a signal waveform diagram in a state in which an RDS clock signal can be extracted, and FIG. 6B is a signal waveform diagram in a state in which an RDS clock signal cannot be extracted.

[Explanation of symbols]

 1 ... Two-phase PSK signal input terminal 2 ... Clock recovery section 3 ... PLL circuit 3a ... Multiplier 3b ... Loop filter 3c ... Variable frequency divider (VCO) 4 ... RDS lock detection section 5 ... RDS lock detection signal output terminal 6 ... Latch circuit 7 ... AND gate 8 ... SD signal input terminal

Claims (1)

[Claims] 1. A clock reproduction for reproducing and outputting an RDS clock signal for demodulating RDS data from a radio data system (RDS) signal, and outputting an initial synchronization identification signal when the RDS clock signal cannot be reproduced. The phase difference between the reference clock signal supplied from the section (2) and the built-in reference clock generation means (3c) and the RDS clock signal is detected, and the operation timing of the radio receiver is determined by the R
PLL circuit for synchronizing with the DS clock signal (3)
And the PLL circuit detects the phase difference between the RDS clock signal and the reference clock signal.
An RDS lock detector (4) that determines whether or not the S clock signal is locked in phase and outputs an RDS lock detection signal when locked.
In the detection circuit, a latch circuit (6) that latches the RDS lock detection signal, and a control unit that controls the PLL circuit (3) by using a logical product of the latched RDS lock detection signal and the initial synchronization identification signal ( 7) The RDS lock detection circuit comprising: