JP2562819B2 - Radio data receiver - Google Patents

Description

TECHNICAL FIELD The present invention relates to a receiver of a radio data system (hereinafter referred to as RDS).
Referred to as a receiver).

BACKGROUND ART Broadcast related information such as information related to the program content of a general broadcasting station is transmitted as data by multiplex modulation, and a desired program content is selected based on the demodulated data on the receiving side. There is a Radio Data System (RDS) that makes it possible to provide that service to radio listeners.

In this radio data system, 57KHz which is the third harmonic of the 19KHz stereo pilot signal outside the frequency band of the FM modulation wave is used as the subcarrier, and this subcarrier is filtered and biphase coded. A radio data signal is amplitude-modulated by a data signal indicating information related to broadcasting such as contents, and the amplitude-modulated subcarrier is frequency-modulated to a main carrier for broadcasting. FIG. 4 shows the spectrum of the bi-phase coded radio data signal.

A radio data signal has 104 bits of 1 as shown in FIG. 5 showing its baseband coding structure.
It is repeatedly multiplexed and transmitted as a group. One group consists of 4 blocks each having 26 bits, and each block consists of a 16-bit information word and a 10-bit check word. In FIG. 5, block 1 is a program identification (PI) code, block 2 is a traffic program identification (TP) code, and block 3 is a station frequency (AF) data of a network station broadcasting the same program. However, in block 4, program service name information (PS) data such as a broadcasting station name and a network name are arranged. In addition, each group is 16 bits of type 0 to 15 with 4 bits according to the contents.
Two versions of A and B are defined for each type (0 to 15), and these identification codes are arranged in block 2. Note that the station frequency (hereinafter abbreviated as AF) data of the network station is transmitted only in the type 0A group, and the program service name information (hereinafter abbreviated as PS) data is transmitted in the type 0A and 0B groups. Has become.

The bi-phase coded radio data signal is the fourth
As shown in the figure, the DSB (Do
Since it becomes a uble side band) signal, when demodulating a radio data signal, a PLL circuit such as Costas loop method that uses energy of LSB (lower sideband) and USB (upper sideband) is usually used. In this PLL circuit, the oscillation frequency of the VCO (voltage controlled oscillator) of the PLL circuit must be controlled to an intermediate frequency between LSB and USB. However, when the reception frequency is detuned from the frequency of the broadcast wave, the reception signal waveform collapses, or the BPF characteristic of 57 KHz shifts, and the VCO oscillation frequency is pulled to the LSB or USB frequency with large energy, and then , Even if an accurate received signal waveform is obtained by tuning, the pulling to the LSB or USB frequency may continue and the 57KHz subcarrier, that is, the radio data may not be reproduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to provide a radio data receiver capable of accurately reproducing radio data.

The RDS receiver of the present invention is a radio data receiver capable of receiving a broadcast wave including a radio data signal which is a DSB signal modulated by a biphase-coded data signal, and is a detector for detecting a received broadcast wave. Means, a demodulating means comprising a PLL circuit for reproducing the bi-phase coded data signal by demodulating the output signal of the detecting means, a tuning means for changing the reception frequency for tuning, When the reception frequency is changed by the station means, in order to prevent the lock of the PLL circuit to the lower side band or the upper side band of the DSB signal obtained from the output of the detection means, And a stopping unit for stopping the demodulation operation of the output signal.

Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an outline of a basic configuration of an RDS receiver according to the present invention. In this receiver,
A desired station is selected by the front end 2 of the FM multiplex broadcast wave received by the antenna 1, converted into an intermediate frequency (IF), and then supplied to the FM detector 4 via the IF amplifier 3. The front end 2 adopts, for example, a PLL synthesizer method using a PLL circuit including a programmable frequency divider, and performs a channel selection operation by controlling the frequency division ratio of the programmable frequency divider by a controller 14 described later. Has become. The detection output of the FM detector 4 is supplied to the MPX (multiplex) demodulation circuit 5, and in the case of stereo broadcasting, L
Separated into (left) and R (right) channel audio signals.

The detection output of the FM detector 4 is supplied to the filter 6 through the gate circuit 17, and the 57 KHz subcarrier amplitude-modulated by the biphase-coded data signal by passing through the filter 6. , Ie the radio data signal is extracted. The opening / closing of the gate circuit 17 is controlled by the controller 14. This radio data signal is supplied to the Costas loop type PLL circuit 7 and demodulated. This demodulated output is supplied to the digital (D) PLL circuit 8 and the decoder 9. In the D-PLL circuit 8, P
A clock for data demodulation is generated based on the demodulation output of the LL circuit 7. The generated clock is supplied to the gate circuit 10. The lock detection circuit 11 detects that the D-PLL circuit 8 is locked, generates a lock detection signal, supplies the lock detection signal to the gate circuit 10, and controls the circuit 10 to be in an open state. In the decoder 9, the bi-phase coded data signal which is the demodulation output of the PLL circuit 7 is D-PL.
It is decoded in synchronization with the clock generated by the L circuit 8.

As shown in FIG. 4, the output data of the decoder 9 is a 104-bit group unit consisting of 4 blocks having a 26-bit structure, and is sequentially supplied to the group / block synchronization & error detection circuit 12. In the group / block synchronization & error detection circuit 12, the group and block are synchronized based on the 10-bit offset word assigned to the 10-bit checkword of each block, and the 16-bit information is based on the checkword. Word error detection is performed. Then, the error-detected data is supplied to the controller 14 after the error is corrected by the error correction circuit 13 at the next stage.

The controller 14 is composed of a microcomputer, and takes in code information of each block in radio data sequentially input in group units, that is, radio data information relating to program contents of a broadcasting station currently being received and RA
Channel selection is performed by controlling the frequency division ratio of a programmable frequency divider (not shown) of the PLL circuit that forms part of the front end 2 based on a channel selection command from the operation unit 16 stored in M15. Take action. The selected reception frequency is written in the RAM 15. In addition, the controller 14
The signal strength based on the F signal level, that is, the detection output of the level detection circuit 18 that detects that the electric field strength has dropped below the set level is also supplied, and the controller 14 is supplied with this detection output. If the reception condition of the broadcasting station currently being received has deteriorated, the frequency division ratio of the programmable frequency divider is set to select another network station based on the AF data of the network station stored in advance in RAM15. It also performs control operations.

Next, the operation of the processor of the controller 14 will be described with reference to the flowchart shown in FIG.

When the tuning process is completed, the processor determines whether or not the frequency division ratio of the programmable frequency divider of the PLL circuit in the front end 11 is changed (step 51), and if the frequency division ratio is not changed, An ON signal is generated for the gate circuit 17 (step 52). The gate circuit 17 is turned on according to the ON signal, and the detection output of the FM detector 4 is the gate circuit.
The radio data signal is demodulated as it is supplied to the filter 6 via 17. On the other hand, when the division ratio is changed, an off signal is generated for the gate circuit 17 (step 5
3). The gate circuit 17 is turned off in response to the off signal, and the supply of the detection output of the FM detector 4 to the filter 6 is cut off.
When the off signal is generated, it is then determined whether or not a predetermined time has passed (step 54). When a predetermined time has elapsed from the generation of the off signal, an on signal is generated for the gate circuit 17 (step 52).

Therefore, when the division ratio changes and the reception frequency changes, the gate circuit 17 is turned off, and the detection output of the FM detector 4 is not supplied to the PLL circuit 7 via the filter 6, so that the radio data signal Demodulation is stopped. The off state of the gate circuit 17 is continued for a predetermined time, after which the gate circuit 17 is turned on and the demodulation of the radio data signal is started. That is, since there is a possibility that the VCO oscillation frequency of the PLL circuit 7 may be pulled into one of the sidebands of the radio data signal due to the change in the division ratio, the gate circuit 17 is turned off to the PLL circuit 7. The VCO oscillation frequency of the PLL circuit 7 is cut off by cutting off the supply of the radio data signal of
Return it to around 57 KHz. After that, if the gate circuit 17 is turned on, the radio data signal can be demodulated.

In the above-mentioned embodiment, the gate circuit 17 is set to FM
Although it is provided between the detection circuit 4 and the filter 6, the present invention is not limited to this, and for example, a gate circuit 17 may be provided between the filter 6 and the PLL circuit 7 as shown in FIG.

As described above, in the radio data receiver of the present invention, the demodulation operation for the output signal of the detection means by the PLL circuit is stopped for a predetermined time only when the reception frequency changes. ing. Therefore, it is possible to avoid a mislock of the PLL circuit that occurs when the reception frequency is detuned from the frequency of the broadcast wave, and thus it is possible to accurately reproduce the radio data.

[Brief description of drawings]

FIG. 1 is a block diagram showing the outline of the basic configuration of the RDS receiver according to the present invention, FIG. 2 is a flow chart showing the operation of the processor in the controller 14 in the receiver of FIG. 1, and FIG. FIG. 4 is a block diagram showing another embodiment of the present invention, FIG. 4 is a diagram showing a spectrum of a bi-phase coded radio data signal, and FIG. 5 is a diagram showing a base band coding structure of radio data. Explanation of main part code 2 …… Front end, 4 …… FM detector 5 …… Multiplex demodulation circuit 8 …… Digital PLL circuit 9 …… Decoder, 10,17 …… Gate circuit 14 …… Controller 18 …… Level detection circuit

Claims (2)

(57) [Claims] 1. A radio data receiver capable of receiving a broadcast wave containing a radio data signal, which is a DSB (double sideband) signal modulated by a bi-phase coded data signal, wherein the received broadcast wave is detected. Detecting means, a demodulating means comprising a PLL circuit for reproducing the bi-phase coded data signal by demodulating the output signal of the detecting means, and a tuning means for changing the reception frequency for tuning. , When the reception frequency is changed by the tuning means, for a predetermined time to prevent locking of the PLL circuit to the lower sideband or the upper sideband of the DSB signal obtained from the output of the detection means A radio data receiver comprising: a stopping unit that stops the demodulation operation of the output signal of the detecting unit by the PLL circuit. 2. The stopping means includes a gate circuit inserted between the output of the detecting means and the input of the PLL circuit, and when the reception frequency is changed by the tuning means, the stopping means continues for the predetermined time. The radio data receiver according to claim 1, further comprising: a control unit that controls the gate circuit to be in an off state.