JPH06180991A - Logic circuit and semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the speed of operation by providing a first transistor between an intermediate node and a ground terminal and a second transistor between a high-potential side power supply terminal and the intermediate node to control them with the logical level of their common input. CONSTITUTION:One-side input terminals b1, b2, b3 of NAND circuits 201, 202, 203 including an inverter INV1 are connected in common. Also, the source electrodes of the n-channel type MOS transistor 13 of the inverter INV1 are connected together to form an intermediate node 16. A MOS transistor 14 is provided between the intermediate node 16 and a power supply Vss (ground), and a MOS transistor 51 controlled with the logical level of the common input terminals b1, b2, b3 is provided between a power supply Vdd terminal and the intermediate node 16. As a result, in spite of the large capacity of the intermediate node 16, the switching speed of logical level is not lowered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and further to a technique for speeding up the operation of the logic circuit, for example, a technique effective when applied to a decoder of a semiconductor memory device.

[0002]

2. Description of the Related Art A combinational circuit as a circuit in which an output logic at a certain time is determined only by an input logic added at the certain time is basically realized by modifying an inverter. There are a NAND circuit and a NOR circuit. In particular, in the CMOS circuit, the transistors are cascaded in both the NAND circuit and the NOR circuit,
A NAND circuit in which n-channel MOS transistors having a high mobility are cascaded is advantageous in terms of higher speed. In either case, the number of stages that can be cascaded is the operating speed,
It is determined in consideration of the occupied area, DC characteristics, etc.

Incidentally, as an example of a document describing the NAND circuit and the NOR circuit, on November 30, 1984,
There is an "LSI Handbook (Page 143-)" issued by Ohmsha Co., Ltd.

[0004]

As shown in FIG. 5, a p-channel type MOS transistor 11 and n-channel type MOS transistors 13 and 14 are connected in series,
In the case where one input terminals b1, b2, b3 in the two-input NAND circuits 101, 102, 103 formed by coupling the p-channel type MOS transistor 12 to them are commonly connected, n transistors in each NAND circuit 101, 102, 103 are connected. The channel-type MOS transistor 14 can be replaced with a single p-channel-type MOS transistor 14 'as shown in FIG. 6, whereby the gate load can be reduced.

However, as the semiconductor integrated circuit becomes finer, the capacitance of the intermediate node 16 cannot be ignored with respect to the gate capacitance. For example, assuming that any one of the input terminals a1, a2, and a3 is selectively set to the high level, the circuit configuration of FIG. 6 has a plurality of n-channel MOS transistors due to the presence of the intermediate node 16. 1
Since the source capacitance CS of 3 is combined, it takes time to charge the source capacitance CS when the p-channel MOS transistor 12 is turned on, and it takes time until the output terminal S and the intermediate node 16 become high level. Takes. Also,
When the above logic circuit is applied to, for example, an address coder of a semiconductor memory device, speeding up of addressing of the memory is hindered.

An object of the present invention is to provide a logic circuit whose operation speed is increased. Another object of the present invention is to provide a semiconductor memory device including such a logic circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, as a first means, an intermediate node is formed by commonly connecting paths for current extraction in a plurality of NAND circuits, and a first transistor is provided between the intermediate node and the ground terminal.
A second transistor having a conductivity type different from that of the first transistor is provided between the high potential side power supply terminal of the circuit and the intermediate node, and the first and second transistors operate in accordance with the logic level of the common input terminal. Configure the logic circuit to be controlled.

As a second means, an intermediate node is formed by commonly connecting the paths for current supply in the plurality of NOR circuits, and a third node is formed between the intermediate node and the power supply terminal on the high potential side of the circuit. A transistor is provided, and a fourth transistor having a conductivity type different from that of the third transistor is provided between the ground terminal and the intermediate node, and the third transistor is provided in accordance with the logic level of the common input terminal.
The operation of the fourth transistor is controlled.

Further, including the above logic circuit,
A decoder in a semiconductor memory device is formed.

[0012]

According to the above-mentioned first means, the second transistor provided between the high potential side power supply terminal and the intermediate node acts so as to assist the driving of the intermediate node in the NAND circuit. That speeds up the operation of the logic circuit.

According to the second means, the fourth transistor provided between the ground terminal and the intermediate node includes:
It acts to assist the driving of the intermediate node in the NOR circuit, which achieves faster operation of the logic circuit.

[0014]

FIG. 7 shows an S (static) RAM which is an embodiment of the present invention.

Although not particularly limited, the SRAM shown in FIG. 7 is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique.

Reference numeral 6 is a memory cell array in which a plurality of static memory cells are arranged in a matrix. Select terminals of the memory cells are connected to word lines in each row direction, and data input / output terminals of the memory cells are arranged in each column direction. Coupling to complementary data lines (also called complementary bit lines). Each complementary data line is commonly connected to the complementary common data line via a Y selection switch circuit 9 including a plurality of column selection switches coupled to the complementary data line in a one-to-one relationship.

Address signals A0-A input from the outside
Among n, A0 to Am are transmitted to the X decoder 74 via the address buffer ABUF arranged corresponding to them, and the address signals Am + 1 to An are Y decoder via the address buffer ABUF arranged corresponding to them. It is transmitted to 78. The word driver 75 is the X decoder 7
Based on the decoded output of 4, the word line corresponding to the input address signal is driven to the selection level. When a predetermined word line is driven, the memory cell coupled to this word line is selected. Further, the Y decoder 78 turns on the column selection switch corresponding to the address signal supplied thereto, so that the column decoder switch is electrically connected to the selected complementary common data line. At this time, the potential of the complementary common data line is amplified by the sense amplifier included in the data input / output circuit 80, whereby the memory cell data is read out. Further, when write data is externally applied to the data input / output circuit 80, the write amplifier included in the data input / output circuit 80 drives the complementary common data line according to the write data, whereby the address data is selected. Charge information corresponding to the data is stored in a predetermined memory cell via the complementary data line.

Further, the detection result of an address transition detection circuit (also referred to as an ATD circuit) 71 for detecting the transition of the address signals A0 to An is transmitted to the control unit 77, and a chip select as a selection signal given from the outside. The signal CS * (* indicates that the signal is low active) and the read / write signal WE * are supplied to the control unit 77 via the CS * buffer 72 and the WE * buffer 3, respectively.
The operation control signal of each part is generated by this control part.

FIG. 4 shows an example of the configuration near the X decoder 74 included in the SRAM.

When the addresses A0 and A1 are input, complementary level signals are output from the corresponding address buffers ABUF, which are input to the predecoder 41 in the subsequent stage. Although not particularly limited, the predecoder 41 is configured to include four 2-input NAND circuits, and one of the four 2-input NAND circuits is set to the low level according to the combination of the addresses A0 and A1. Four inverters corresponding to the two-input NAND circuit are arranged in the subsequent stage of the predecoder 41, and are transmitted to the decoder 43 via the corresponding inverters. This decoder 43
Although not particularly limited, it is configured to include a plurality of 2-input NAND circuits, and the output logic state of the inverter 42 is transmitted to one input terminal of the 2-input NAND circuit. Further, the other input terminal of the 2-input NAND circuit constituting the decoder 43 is commonly connected in units of four,
The output signal of the predecoder 45 that performs predecoding on the upper addresses A2 to Am is transmitted to the above. That is, the 4-input 2-input NAND circuit group is selected in accordance with the output signal of the predecoder 45, and based on the output of the inverter 42, the output of one NAND circuit is stored in the memory shown in FIG. It is adapted to be asserted for driving the word line of the array cell 76.

FIG. 1 shows a detailed structure of the 2-input NAND circuit which constitutes the decoder 43.

As shown in FIG. 1, the decoder 43 is
Is a p-channel MOS transistor
CMOS inverter INV including a transistor 11 and an n-channel MOS transistor 13 connected in series
Including 1. That is, the 2-input NAND circuit is similar to the circuit shown in FIG. 6, the CMOS inverter INV1, the p-channel type MOS transistor 12 provided between the output terminal of the CMOS inverter INV1 and the high potential side power source Vdd terminal, and the CM described above.
N-channel MO that constitutes the OS inverter INV1
S transistor 13 and low potential side power supply Vss (ground)
It is formed by an n-channel type MOS transistor 14 'provided between the terminal and the terminal. Similar to the circuit shown in FIG. 6, the n-channel MOS transistor 14 'has an intermediate node in which the source electrodes of the n-channel MOS transistors 13 forming the CMOS inverter are coupled to each other in order to reduce the gate load. 16 is formed and the n-channel MOS transistor 14 included in each NAND circuit 101, 102, 103 of FIG. 5 is replaced with one transistor. According to FIG. 4, one input terminal of the four 2-input NAND circuits is commonly connected to the output terminal of the predecoder 45. However, in FIG. 20
1, 202 and 203 are representatively shown.

Of the input terminals a1, a2 and a3, only a1 is at high level (other input terminals a2 and a3 are at low level).
Considering the case where the common input terminals b1 to b3 change from the high level to the low level in this state, in the circuit configuration shown in FIG. 6, it is only one that is involved in raising the output S1 and the intermediate node 16 to the high level. Since there is only the p-channel type MOS transistor 12, if the capacitive load on the intermediate node 16 becomes heavy, the pulling to the high level is delayed.

Here, the charge pulling rate can be expressed as follows. t = C · V / I t is the time required for pulling up, C is the capacitance of the node to be pulled up (in this case, the capacitance of the intermediate node 16 is the largest), V is the pulling potential, and I is the current that can flow through the MOS transistor. Proportional to MOS size.

Now, the composite capacity (CS) at the intermediate node 16
However, if it is assumed that the size of the p-channel MOS transistor 12 is increased by 5 times, it is necessary to increase the size of the p-channel type MOS transistor 12 by 5 times in the circuit system shown in FIG. However, the use of such a large-sized MOS transistor requires a gate capacitance at the common input terminals b1 to b3 to be approximately five times, and in view of power consumption and the like, it must be said that the circuit is difficult to handle. Absent.

Therefore, the p-channel MOS transistor 12 has the same size as before, and a p-channel MOS transistor 51 is newly provided between the high potential side power supply Vdd terminal and the intermediate node 16. The gate electrodes of this MOS transistor 51 are common input terminals b1, b2, b.
Combined with 3. p-channel type MOS transistor 5
The size of 1 is p-channel type MOS transistor 12
Is four times. According to this, under the above-mentioned conditions, the MOS transistor
2,51 is involved, resulting in a MOS size of 5
Since the current is supplied by doubling the value, the current is supplied, so that the switching speed of the logic level does not decrease even though the capacity of the intermediate node 16 is large.

FIG. 3A shows the characteristics of the logic circuit shown in FIG. 1 in relation to the logic circuit shown in FIG.

After the common input terminals b1, b2, b3 are set to the low level, the logic level of the output terminal S1 in the logic circuit of FIG. 6 rises gently, whereas in the logic circuit of FIG. Due to the action of the p-channel MOS transistor 51, the voltage rises sharply. Due to such an abrupt change, the time t required for the logic level of the output terminal S1 to reach the high level is significantly shortened.

In practice, the p-channel type MOS transistor 12 pulls up the electric charge of the intermediate node 16 via the n-channel type MOS transistor 13, and the resistance component thereof influences the pulling up speed.
Since the S-transistor 51 has no influence at all, it is sufficient that the size of the S-transistor 51 is about four times as large as that of the p-channel MOS transistor 12. Since only one p-channel type MOS transistor 51 needs to be provided in one intermediate node 16, the corresponding MOS node is not provided in the intermediate node 16.
The increase in capacitance due to the provision of the transistor 51 is small, and there is no particular problem.

The n-channel type MOS transistor 1
Since 4 ′ operates so as to extract all the charges of the intermediate node 16, a device having a size sufficiently larger than the n-channel type MOS transistor 13 is applied.

According to the above embodiment, the following operational effects can be obtained.

(1) One input terminals b1, b2, b3 of a plurality of NAND circuits 201, 202, 203 including the CMOS inverter INV1 are commonly connected, and the n-channel MOS transistor of the CMOS inverter INV1 is provided. The source electrodes of 13 are coupled to each other to form the intermediate node 16, and the logic of the common input terminals b1, b2, b3 is provided between the intermediate node 16 and the low potential side power source Vss (ground) terminal. In the case where the n-channel type MOS transistor 14 'which is on / off controlled by the level is provided, the common input terminals b1, b2, b3 are provided at the logic level between the high potential side power source Vdd terminal and the intermediate node 16. A p-channel MOS transistor 51 that is turned on / off is provided. A result, since the MOS transistors 12 and 51 are involved in the raising of the intermediate node 16, even though the capacity of the intermediate node 16 is large,
It is not necessary to reduce the switching speed of the logic level.

(2) When the logic circuit as described above is applied to the decoder 43 due to the function and effect of the above (1),
The memory access speed can be improved by shortening the time for determining the decode output logic.

FIG. 2 shows another embodiment of the present invention.

In the above embodiment, the case where the 2-input NAND circuit is applied to the decoder has been described. However, when a plurality of 2-input NOR circuits are applied and one of its input terminals is commonly connected to form the decoder. Can also be considered. The logic circuit in that case is, as shown in FIG. 2, a plurality of NOR circuits 401 and 40 each including a CMOS inverter INV2.
The two input terminals b1 and b2 are commonly connected to each other, and the source electrodes of the p-channel MOS transistors of the CMOS inverter INV2 are coupled to each other to form an intermediate node 67. The output node of the inverter INV is the output terminal S of each NOR circuit.
1, S2. This output terminal and the high potential side power supply Vdd
An n-channel MOS transistor 63 is coupled between the terminal and the n-channel MOS transistor 63.
Is used as one input terminal of the NOR circuit.
Further, by providing a p-channel type MOS transistor which is on / off controlled by the logic level of the common input terminals b1 and b2 between the intermediate node 67 and the high potential side power supply Vdd terminal, the gate load is reduced. .

Since such a NOR circuit also has the intermediate node 67, as in the case of the NAND circuit,
The capacity of the intermediate node 67 delays the switching of logic states. Therefore, the low potential power supply Vss (ground)
Between the terminal and the intermediate node 67, an n-channel type MOS transistor 66 which is on / off controlled by the logic level of the common input terminals b1 and b2 is provided, and the intermediate node 67 is auxiliary driven by this MOS transistor 66. Thus, the reduction in the switching speed of the logic level of the intermediate node 67 is avoided. That is, when the n-channel type MOS transistor 66 is not provided, as shown in FIG.
In (b), the logic level of the intermediate node 67 is gently lowered as shown by the characteristic curve 304, whereas when the n-channel type MOS transistor 66 is provided, its auxiliary driving causes the logic level of the output S1. The level sharply decreases as shown by the characteristic curve 303 in FIG.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, although the two-input NAND circuit and the two-input NOR circuit have been described in the above embodiments, the NAND circuit and the NOR circuit may have three or more inputs.

In the above description, SRA, which is the field of application behind the invention mainly made by the present inventor, is the background.
However, the present invention is not limited to this. For example, a dynamic RAM is used.
The invention can be widely applied to other semiconductor memory devices, and further to semiconductor integrated circuits.

The present invention can be applied on condition that it has at least an intermediate node.

[0041]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, an intermediate node is formed by commonly connecting the paths for current extraction in a plurality of NAND circuits, the first transistor is provided between the intermediate node and the ground terminal, and the high potential side of the circuit is provided. By providing a second transistor having a conductivity type different from that of the first transistor between the power supply terminal and the intermediate node, and controlling the operation of the first and second transistors according to the logic level of the common input terminal, Since the intermediate node is auxiliary driven by the second transistor, the operation speed of the logic circuit can be increased.

An intermediate node is formed by commonly connecting the paths for supplying current in the plurality of NOR circuits, and a third transistor is provided between the intermediate node and the power supply terminal on the high potential side of the circuit. A fourth transistor having a conductivity type different from that of the third transistor is provided between the ground terminal and the intermediate node, and the operation of the third and fourth transistors is controlled according to the logic level of the common input terminal. Since the intermediate node is driven auxiliary, the operation speed of the logic circuit can be increased.

Further, by applying the logic circuit as described above to the decoder of the semiconductor memory device, the addressing speed of the semiconductor memory device can be increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a decoder included in an SRAM which is an embodiment of the present invention.

FIG. 2 is a circuit diagram of a main part of a decoder which is another embodiment of the present invention.

3 (a) is a characteristic diagram of the circuit shown in FIG. 1, and FIG. 3 (b) is a characteristic diagram of the circuit shown in FIG.

FIG. 4 is a configuration block diagram around an X decoder of an SRAM which is an embodiment of the present invention.

FIG. 5 is an electrical connection diagram of a logic circuit formed by connecting a plurality of NAND circuits.

FIG. 6 is an electrical connection diagram of a logic circuit which is a premise of the present invention.

FIG. 7 is an overall configuration block diagram of an SRAM which is an embodiment of the present invention.

[Explanation of symbols]

 11 p-channel type MOS transistor 12 p-channel type MOS transistor 13 n-channel type MOS transistor 14 'n-channel type MOS transistor 16 intermediate node 43 decoder 51 p-channel type MOS transistor 61 p-channel type MOS transistor 62 n-channel type MOS transistor 63 n Channel type MOS transistor 65 p Channel type MOS transistor 66 n Channel type MOS transistor 67 Intermediate node 71 Address change detection circuit 72 CS * buffer 73 WE * buffer 74 X decoder 75 Word driver 76 Memory cell array 77 Control section 78 Y decoder 79 Y selection Switch circuit 80 Data input / output circuit 201 NAND circuit 202 NAND circuit 203 NAND circuit 40 NOR circuit 402 NOR circuit ABUF address buffer S1 output terminal S2 output terminal S3 output terminal a1, a2, a3 input terminals b1, b2, b3 input terminal Vdd high potential power source Vss low potential side power supply

Claims (3)

[Claims] 1. In a logic circuit in which one input terminal of a plurality of NAND circuits is commonly connected to each other, an intermediate node is formed by commonly connecting paths for current extraction in the plurality of NAND circuits. A first transistor is provided between the intermediate node and the ground terminal, and a second transistor having a conductivity type different from that of the first transistor is provided between the power supply terminal on the high potential side of the circuit and the intermediate node. A logic circuit characterized in that the operation of the first and second transistors is controlled according to a logic level of a terminal. 2. In a logic circuit in which one input terminal of a plurality of NOR circuits is commonly connected to each other, an intermediate node is formed by commonly connecting paths for supplying current in the plurality of NOR circuits. A third transistor is provided between the intermediate node and the power supply terminal on the high potential side of the circuit, and a fourth transistor having a conductivity type different from that of the third transistor is provided between the ground terminal and the intermediate node. A logic circuit characterized in that the operation of the third and fourth transistors is controlled according to a logic level of a terminal. 3. A semiconductor memory device including a decoder for decoding an input address signal, wherein the decoder is formed by including the logic circuit according to claim 1. Description: