JPH06180670A - Cache storage device - Google Patents

Abstract

PURPOSE:To improve the performance of a cache by reducing a proportion of data, which is the object of an area clear instruction, occupied in the cache to improve the use efficiency of the whole of the cache. CONSTITUTION:A signal indicating a memory access request is sent to the cache when a processor issues the memory access request accompanied with execution of the area clear instruction to the cache, and each entry of a retrieval part 31 is provided with an X part 314 where a flag is set at the time when this entry corresponds to the area of a main storage device accessed by the area clear instruction. When the memory access request accompanied with execution of the area clear instruction is issued to the cache and the entry retrieved by the retrieval part 31 mishits the cache and the retrieved entry has the flag set in the X part 314, a means provided in a replace control part 33 selects the entry and designates the storage area of a data part corresponding to the entry as a replace area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache storage device in an electronic computer system.

[0002]

[Prior art]

(1) Function of cache storage device The cache storage device in the computer hardware is located between the IP that operates at high speed and the main storage that operates at low speed. The cache storage device holds the data portion of the main storage device, reads the data requested from the IP at high speed, and transfers it to the instruction processor IP. That is, it operates as a buffer device for filling the speed difference between the IP and the main storage device. The basic structure of a cache storage device is
A. Smith, Cache Memories,
ACM Computing Surveys, Vo
l. 14 No. 3 (Sept. 1982) systematically.

The memory element forming the cache memory operates at a higher speed than the element forming the main memory, and is designed so as to minimize the delay due to the memory access of the processing such as ALU. However, since it is a high-speed element, it is expensive, and there are restrictions on mounting. Therefore, only a capacity much smaller than the main memory capacity is mounted. For example, M-880
In MS, up to 2 GB can be installed, whereas in BS (Buffer Store) which is a cache dedicated to IP.
ge) is 256 KB, and WS (Wo connected to multiple BSs
rk Storage) is SC (System Con)
4 MB is implemented per troll).

When the data of the memory access request generated by the ALU does not exist in the BS, the block (Bl
The data is transferred to the BS and registered in units called ock: 128B). This operation is performed by BT (Block Tra
nsfer). If the data requested from BS to WS does not exist in WS, the line (Li
The data is transferred to the WS and registered in a unit called ne: 256B). This operation is called LT (Line Tran)
sfer). In order to perform cache coincidence control, a search unit is provided for the data unit WS.
This is composed of an Adr section indicating the data address, a V section indicating the validity / invalidity of the data, and an R section indicating the replay order. As a result, a registration address or the like is registered in WS line units, and replacement of the WS cache is controlled.

The Adr (Address) section records the address of the line registered in the WS. The address requested by the IP is compared with the registered address of the Adr section to determine whether the request is a cache hit or a cache miss. V (Valid) part is A
Indicates whether the address of the dr part is valid. If the WS line becomes invalid due to cache replay, etc.,
An invalid flag is set in the V portion corresponding to the line. R
The (Replace) unit controls replacement of the cache. The BS or WS of the M series machine has a 4-set configuration, and data having the same partial address can be registered in 4 blocks or 4 lines. When data is registered in all four sets, if it is necessary to register the fifth data having the same partial address, which set is to be registered with LRU (Least Recent).
Used) algorithm. This algorithm records the set that has not been accessed for the longest time to date, and updates this record every time access is made to four sets of the same partial address.

(2) Replay control of cache storage device The cache storage device usually has a small storage capacity as compared with the main storage device to which it is connected. Therefore, if the range of the memory accessed by the IP is changed,
Since the cache follows it, it discards the block registered in the past and registers a new block. Such block replacement is called cache refresh. The access to the main memory and the transfer from the main memory to the cache memory are slower than the access to the cache memory itself, so it is desirable to reuse the registered data as much as possible to increase the hit rate of the cache memory. Therefore, during replay, controls called FIFO and LRU are used.

FIFO is First In First
Abbreviation of Out, which is control to replay the oldest block registered in the past. The FIFO is an equal control when the blocks registered in the cache are uniformly accessed. However, it is not the case that old blocks are no longer needed. That is, there is a possibility that frequently accessed data has been registered for a long time. In this case, the frequently accessed data is expelled from the cache memory,
There is a risk of reducing the cache hit rate. LR
U is the abbreviation for Least Recently Used,
This is a control for maximizing the replay order of the oldest accessed data. By using the LRU, frequently accessed data is not evicted and remains in the cache memory. As a result, the LRU can expect a higher cache hit rate than the above-mentioned FIFO.

Japanese Patent Laid-Open No. 2-35544 discloses a technique for preventing data whose average stay time in the cache is shorter than the average access time from being expelled from the cache storage. Data subject to this publicly known example
The data is data that is periodically accessed by a timer interrupt or the like. Therefore, by detecting the periodicity of access to a specific address and lowering the repeat order of the data (that is, if it is raised, it is easy to replace it, if it is lowered, it is difficult to replace it), You can increase the cache hit rate of.

[0009]

The conventional cache memory control method has a problem when an area clear instruction in units of 10 kilobytes such as an MVC instruction is executed by IP. The area clear command is executed when a certain area of the main storage device is desired to be used as a work area, for example. That is, in many cases, unnecessary data is stored in the area desired to be used as the work area, and it is necessary to clear this unnecessary data. Therefore, the data in the cleared area prepared in advance in the main memory is copied to the work area. An area clear instruction is executed when such copying is performed. When the area clear instruction is executed in the system including the conventional cache storage device, the data (all “0” data) of the cleared area prepared in the main storage device is stored in the cache storage device. Next, the work area is stored in the cache storage device from the main storage device, and all "0" data stored in the cache storage device is copied to the work area on the cache storage device. As a result, the data previously registered in the cache storage device is
Regardless of its type, it will be evicted from the cache.
If the target data that has been evicted is an instruction sequence or data that will be used again in IP, it is necessary to register these data again in the cache when using them. However,
The data that is the target of the area clear command, that is, the data in the work area, is registered in the cache once,
It is unlikely to be used again in the cache as compared with other data. Therefore, if the target data of the area clear instruction occupies a large part in the cache, the reusability of the cache storage device is reduced as a result, and the cache performance is deteriorated.

An object of the present invention is to increase the utilization efficiency of the entire cache and improve the performance of the cache by suppressing the ratio of the data targeted by the area clear instruction in the cache to a low level.

[0011]

To achieve the above object, a cache storage device includes a search unit having a plurality of entries having a V section, an Adr section, and an R section, a hit determination section, a replacement control section, and a data section. An area for sending a signal indicating that the request is a memory access request accompanying execution of an area clear instruction to the cache storage device when the instruction processor issues a memory access request to the cache storage device. A clear request interface is provided between the instruction processor and the cache storage device, and a flag is set in the entry of the search unit when the entry is an entry corresponding to the area of the main storage device accessed by the area clear instruction. X section
Further, when a memory access request is issued from the instruction processor to the cache storage device and the request is a memory access request accompanying the execution of the area clear instruction, and the entry searched by the search unit is a cache miss, the search is performed. When there is an entry in which the flag is set in the X section in the specified entry, the replacement control section is provided with means for selecting the entry and designating the storage area of the data section corresponding to the entry as the replacement area. . Further, when the memory access request is issued from the instruction processor to the cache storage device without providing the X section for the entry of the search section and the entry searched by the search section is a cache miss, the entry to be replaced is selected. When the means for selecting and the memory access request are accompanied by the execution of the area clear instruction, the replacement order of the R part of the searched entry is maximized so that the replacement order of the R part of the selected entry becomes the highest. When the memory access request is not accompanied by the execution of the area clear instruction, the replacement order of the R part of the searched entry is specified so that the replacement order of the R part of the selected entry becomes the lowest. And a means for doing so are provided in the replacement control section. Further, in the cache storage device, the data section is divided into a plurality of sets, and the entry of the search section is divided into a plurality of sets.

[0012]

When the instruction processor issues a memory access request to the cache storage device and a cache miss occurs, the entry corresponding to the area of the main storage device accessed by the area clear instruction previously executed is stored in the cache storage. If it exists in the device, the data in the main memory device accessed this time is stored in the memory area in the cache memory device corresponding to the entry. Therefore, it is possible to reduce other necessary data from being ejected from the cache memory by registering the data, as compared with the related art. Further, when the instruction processor issues a memory access request to the cache storage device and a cache miss occurs, the entry to be replaced is selected, and the memory access request is accompanied by the execution of the area clear instruction. Sometimes, the replacement order of the selected entry becomes the highest, and when the memory access request is not accompanied by the execution of the area clear instruction, the replacement order of the selected entry becomes the lowest. For this reason,
By keeping the replay order of the data for area clear always at the highest level, the ratio of the data in the cache can be minimized.

[0013]

EXAMPLES The present invention will be described in more detail with reference to the examples shown in the drawings. (1) First Embodiment: Overall Configuration FIG. 1 shows the overall configuration of an embodiment of the present invention. The components of this figure are roughly composed of an ALU (1), a cache storage device (3), and a main storage device (5). Looking at the configuration of the embodiment in relation to the above description of the prior art, the ALU
(1) is the instruction processor IP and the buffer storage BS
And the cache storage device (3) corresponds to the work storage WS. Between the ALU (1) and the cache storage device (3), in addition to the normal memory access interface (21), the area clear request interface (2
2) is provided.

The inside of the cache storage device (3) is further divided into a search unit (31), a hit determination unit (32), a replay control unit (33), and a data unit (34). The search unit (31) according to this embodiment is divided into four sets according to the division of the data unit (34). 1 in set 0
The entries are V (Valid) part (311) and Adr.
(Address) unit (312), R (Replac)
e) section (313), X (Exclusive) section (31)
4). The V section (311) has a flag for determining validity / invalidity of the entry. Adr section (31
2) saves the address of the data registered in the entry. The R section (313) replays the entry.
The ranking to be registered is registered. The X portion (314) is a feature of the present invention, and indicates that the entry is registration data (data of an area (for example, work area) to be cleared in the main storage device) by the area clear request. Here, the address information consists of, for example, 32 bits and is A
It is divided into a dr section of 12 bits, a column section of 12 bits, and a displacement of 8 bits. Then, the search unit (3
The number of entries in each set in 1) is the number of columns, that is,
In this example, there are only 2 to the 12th power, and each entry is designated by the value of the column portion, that is, the column value.

The search section 31 receives the address information of the memory access request issued by the ALU, searches the entry common to each set by the column section therein, and outputs the search result to the hit determination section (32). Hit determination unit (32)
Compares the Adr part of the search result from the search part (31) with the Adr part of the memory access request address by the memory access request issued by the ALU, and the request hits the cache, and the cache storage device (3) It is determined whether the request can be processed in the memory or whether the request has a cache miss and accesses the main storage device (5). When accessing the main memory, control is passed to the repeat control unit (33), and in the case of a cache hit, control is passed to the data unit (34).

When the memory access request issued by the ALU causes a cache miss, the replay control section (33) receives control from the hit determination section (32) and sends a data transfer request to the main storage device (5). Issue. Further, it is determined where the data transferred from the main memory device is stored in the data unit (34) of the cache memory device. The details will be described later. The data unit (34) stores the data in the cache storage device (3). The structure of sets and columns is the same as that of the search unit (31). The data is updated in response to a data write request from the ALU, and the data is transferred to the ALU in response to a data read request. A
If the data requested by the LU is not stored in the cache storage device, it is transferred from the main storage device, and it also has a function of storing this transfer data. Search unit (3
1), the detailed configuration of the hit determination unit (32) is shown in FIG. 2, and the detailed configuration of the replay control unit (33) is shown in FIG. A detailed description of each will be given later.

(2) First Embodiment: Details of Operation A region clear command such as an MVC command registers data in a region (for example, a work region) on the main memory device desired to be cleared in the cache memory device. The registration location on the cache storage device in which this registration is made is called a clear area registration location. The means for reusing the clear area registration place can be realized as follows. It is assumed that ALU (1) executes the MVC instruction and a memory access request is generated accordingly. Then, the address of the memory access appears in the interface (21), and the area clear request interface (22) shows a signal areaClear indicating that it is an MVC instruction in synchronization with the memory access.
The signal (23) appears. At this time, the judgment is made according to the following cases depending on the data registration status in the cache.

(A) When the request has a cache hit When the data of the request has already been registered in the cache storage device, the hit determination unit (32) makes a cache hit determination. That is, the column of the search unit (31) to be searched is determined by the address of the request.
Then, for all four entries in the column, the address of the request is compared with the address registered in the Adr unit (312) of the search unit. Whether or not each data is valid is also determined by searching the V section (311). As a result, if the address of the requested data and the registered address of the Adr part are the same in any of the entries and the V part of the same entry is 1, the data is judged to be a cache hit. As a result, the request flows to the data unit (34), and the data unit (34) reads / writes the data as requested.

The following cases (B), (C) and (D) are all cases where the data of the request is cache miss, contrary to the above (A). As a result of the request being searched by the search unit (31), if there is no entry in which the V part = 1 and the Adr part matches the data of the request for all four entries of the column, it is not a cache hit. Is found in the hit determination section (32). As a result, control is passed to the repeat control unit (33), and a data transfer request is issued to the main storage device (5).

(B) When any of the entries is X = 1 Of the four entries in the column corresponding to the area clear request,
If X of one entry is 1, then V of another entry
Irrespective of whether or not is 1, the entry with X = 1 is invalidated once, and the data of the area clear request (data of the area (for example, work area) to be cleared in the main memory) is deleted. Register there. (C) An invalid entry exists, and other entries have X = 0.
When it is, as a result of searching the search unit (31), at least one of the four entries in the column is V = 0, that is, one of the entries is empty, and X of all other entries is 0,
In other words, all entries are
When the data is not stored, the data of the area clear request is stored in the entry of V = 0 (in case of a plurality, one of them). Reflecting this result, in the entry of the search unit (31), V part = 1, the address of the request in the Adr part, and X part = 1 are registered. (D) All are valid, but there is no data registration for area clear. All of the corresponding column sets 0 to 3 of the retrieval unit (31) are X = 0, that is, data that is not for area clear is stored. Further, if all of the sets 0 to 3 are V = 1, that is, valid data, the one having the highest replay order among the sets 0 to 3, that is, the set having a large R, The data is stored. Reflecting this result, as in the case of (C), in the entry of the search unit (31), V part = 1, the address of the request in the Adr part,
X part = 1 is registered.

With this operation, the number of entries used for the area clear request in one column is at most one,
It doesn't increase any more. In the case of a cache memory device having a four-set configuration, the cache occupied by the area clear request is at most 25%.

FIG. 2 is a block diagram of the search / hit determination unit (300) showing the details of the search unit (31) and the hit determination unit (32) in FIG. ALU in FIG.
A request is issued from (1), and its address is transmitted to the cache storage device (3) by the interface (21). In the area clear request interface (22), a signal areaClear (23) indicating the MVC instruction appears in synchronization with the memory access. The address is divided into an entry address and a column address when searching the search unit (31).
As shown in, the column address of the address (10) is used to specify the column position of the search portion. Here, the search part is the V part (311) and the Adr part (31
2), the results of the R section (313) and the X section (314) are output. The search result of the Adr unit (312) is compared with the entry address of the request by the comparator (320). Furthermore,
An AND circuit (360) performs a logical product of the comparison result and the search result of the V section (311). The V section (311) indicates whether or not the in-cache data of the address shown in the Adr section (312) is valid. The address comparison and the logical product output (410) of the V unit (32) determine whether the data registered in the cache is the same as the request address. Similarly, V portion (311), R portion (313), X
Part (314) search results (420), (430), (4
40) is also output. The cache storage device of this embodiment has four
Since it is a set configuration, as shown in FIG. 2, the search / hit determination device described above has a four-sided structure, and the output thereof is also a bundled line in units of four.

FIG. 3 shows a replay control unit (33) shown in FIG.
2 shows a detailed configuration of the replay target determining circuit (100). With this configuration, the search result of FIG.
Of the replay target set signal (7
00) is output. This logic does not operate in the case of a cache hit because it is intended for the replay at the time of a cache miss. Although a logic circuit diagram is omitted in the figure, only in the case of a cache miss, that is, the output of the replay target determining circuit is gated and output.

Hereinafter, (B) in the above description,
Cases (C) and (D) will be described in order. (B) When any one of the entries has X = 1, one of the inputs X <0-3> becomes 1, so the OR gate
AND (201) is satisfied and the signal areaClear (23) indicating the MVC instruction is “1”, AND
The gate 200 is established, and the signal isSetForClear
r (105) becomes "1". Signal areaClear
If (23) is not "1", then four bundled lines fo
Either one of rClearSet (104) becomes "1". Therefore, AND circuits (601), (604), (6
Either of 07) and (610) is established. Further, at this time, neither of the AND circuits (204) and (205) which receives the negation of the signal isSetForClear (105) as input. Therefore, the signal isMissed (10
7) and replaced (108) are both "0". From this, AND circuits (602), (603),
(605), (606), (608), (609),
All of (611) and (612) are not established. As a result,
Only one of the AND circuits (601 to 612) is established, which is the set that outputs X = 1. In the OR circuit (71 to 74) which is a combination of these AND circuits, the set is “1”, and the replay target set is X = 1
Will result in a set of. Note that the signal area
If Clear (23) is not "1", the above operation is not performed.

(C) An invalid entry exists and other entries have X = 0, or other entries have X ≠ 0.
Even if the signal areaClear (23) is “0”, X = 0 for all the sets, or the signal areaClear (2
If 3) is “0”, the signal isSetForClear
r (105) becomes “0”. In addition, V <0-3> (1
The OR gate (202) which inputs the negation of 02) is V
If any of <0-3> (102) is "0", the AND gate (204) is established together with "0" of isSetForClear (105), and the signal isMissed (107) is output. To establish. If there are multiple invalid entries, Lowest # Select
or (203) selects the minimum number set, and the bundle signal missedSet (10
6) becomes "1". At this time, the signal replac
Since the negative output of the OR gate (202) is "0", the ed (108) remains "0". Signal isSetF
The orClear (105) is also “0”. Therefore, A
Of the ND circuits (601 to 612), the one that can be satisfied is (6
02), (605), (608), or (611). This is a realization of targeting the set as a replay target when all the sets of X = 0 and V = 0 exist (in the case of a plurality of sets, the set of the minimum number is set). ).

(D) There are no invalid entries and X = 0 for other entries, or X ≠ for other entries.
Even if it is 0, the signal areaClear (23) is "0".
If it is signal isSetForClear (105) and signal is
Missed (107) are both "0" and their negated signal replaced (108) is "1". In this case, the set with the highest replay order is selected. The replay rank of each set is R <
0-3> (103).
Analyzed with the best # Selector (208) and set the replay target set to setToBeReplaced.
Output as (109). Here, the AND circuits that are satisfied are (603), (606), (609), and (612).
Whichever is the case, and no other AND circuit is established. Therefore, the set designated by the normal replay control is selected as the replay target set.

As described above, the above-mentioned means for reusing the clear area registration block is realized.

(3) Second Embodiment The second embodiment realizes the fastest replenishing means in the clear area. This will be described below with reference to FIG. FIG. 4 shows almost the same configuration as FIG. The difference from FIG. 1 is that the search section (31) is not provided with the X section which is a flag section for area clearing.
The difference is that the control algorithm of the replay control unit (33) is different. In order to replay the block storing the clear area earliest, the replay order of the target block among all the sets including the block may be set to the highest. Therefore, when registering a block in the clear area, the normal block registration and the method of assigning the replay order are changed.

FIG. 5 shows a block diagram of the search / hit determination unit in the second embodiment. The same parts as those in FIG. 2 are designated by the same reference numerals. A signal ar is sent from the ALU via the request address and the area clear request interface (22).
eaClear (23) is transmitted. Signal areaC
“Lear (23)” determines that the ALU is a memory access accompanying the area clear by the MVC instruction and “1”.
And Otherwise, it is "0". The address is divided into an entry address and a column address when the search unit (31) is searched. As shown in FIG. 2, the column address of the address (10) is used to specify the column position of the search portion. used. Here, the search portion is the V portion (311), the Adr portion (312), and the R portion (313).
The result of is output. The search result of the Adr unit (312) is the request entry address (21) and the comparator (32
0) is compared. Furthermore, the comparison result and the V part (31
The logical product of the search results of 1) is calculated (360). V part (31
1) indicates whether or not the in-cache data of the address shown in the Adr section (312) is valid. The address comparison and the logical sum output (410) of the V unit (311) determine whether the data registered in the cache is the same as the request address. Similarly, V part (311), R
The search results (420) and (430) of the copy (313) are also output.

FIG. 6 shows a replay control unit (33) shown in FIG.
The detailed configuration of the replay target determining circuit (60) is shown.
In this configuration, the search result of FIG. 5 is input, the set of the replay is determined, and the replay target set signal (70
0) is output. This logic does not operate in the case of a cache hit because it is intended for the replay at the time of a cache miss. Although the logic circuit diagram is omitted in the figure, only in the case of a cache miss, that is, the replay
The output of the target determination circuit is gated and output. The same parts as those in FIG. 3 are designated by the same reference numerals. (E) When an invalid entry exists Also, the OR of which the negative of V <0-3> (102) is input
The gate (202) is established when any of V <0-3> (102) is "0", whereby the signal i
sMissed (107) is established. If there are multiple invalid entries, Lowest # Selecto
The minimum number set is selected by r (203),
The bundle signal missedSet (106) becomes "1" in the set. At this time, the signal replaced
In (108), the negative output of the OR gate (202) is "0".
Therefore, it remains “0”. Therefore, the AND circuit (6
(602) and (6)
05), (608), or (611). This is a realization that, when a set of V = 0 exists, the set is set as a replay target (in the case where a plurality of sets are applicable, a set of minimum numbers).

(F) When all entries are valid When the signal isMissed (107) is "0" and its negated signal replaced (108) is "1", the replay order is the highest. The set is selected. The replay rank of each set is R <0-3> (1
03), so change this to Highest # S
It is analyzed by the elector (208), and the replay target set is output as setToBeReplaced (109). Here, the established AND circuit is (60
3), (606), (609), or (612), and no other AND circuit is established. Therefore, the set designated by the normal replay control is selected as the replay target set, and is output as the replay target set signal (700).

Next, FIG. 7 shows an example of the replacement order change selection circuit (70) for changing the replacement order in the replacement control unit (33). The first replacement order changing circuit R-change (1) (70
1) is a replacement order changing circuit in a normal case,
Since the newly registered set has been accessed most recently, the replacement order of each set is changed so that the replacement order of the set becomes the lowest. R-change which is a second replacement order changing circuit
(2) (702) is the signal areaClear (23)
It is a replacement order change circuit when
Since it is desired to expel a newly registered set earlier, the replacement order of each set is changed so that the replacement order of the set becomes the highest.

R-change (1) (701) and R-
The change (2) (702) inputs the inspection result (430) of the R section (313) and the replay target set signal (700) which is the output of the replay target determination circuit (60), respectively, and replaces them. And replace order signals are output. AND GATE (711) 〜
R-change (1) (7
01), and the negative signal of the signal areaClear (23) is input.
R for each of AND gates (715) to (718)
-The replacement order signal from the change (2) (702) is input and the signal areaClear (2
3) is input. This causes the signal areaClea
When r (23) is "0", that is, when the memory access is not accompanied by the area clear, the AND gate (7
11) to (714) to R-change (1) (70
The replacement order signal from 1) is output, and the R-change is output from AND gates (715) to (718).
(2) The replacement order signal from (702) is not output. Conversely, the signal areaClear (23) is "1".
When the memory access is due to area clear, the AND gates (711) to (714) do not output the replacement order signal from the R-change (1) (701) and the AND gate (715). ~
From (718), the replacement order signal from R-change (2) (702) is output. The outputs from the AND gates (711) to (714) and the outputs from the AND gates (715) to (718) are the OR gate (7
21) to (724), and the OR gate (721)
The replacement order signal for registration (730) selected from (-) to (724) is output.

This registration sequence signal for registration (730)
Then, the original request address signal (62) is also re-registered in the search unit, and the cache is replayed.
In this way, when the relevant data is registered in the cache by the request accompanied by the establishment of the signal areaClear (23), the replay rank can always be the highest.

[0035]

According to the present invention, when the data for clearing the area has already been registered in the cache memory, the registration of the new data for clearing the area recreates the existing clearing data. Since the data is registered in the same manner, it is possible to obtain an effect that other necessary data can be removed from the cache memory by registering the data as compared with the conventional case. Further, by always setting the replay order of the data for area clearing to the highest level, it is possible to minimize the ratio of the data in the cache.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a search / hit determination unit.

FIG. 3 is a diagram showing a detailed configuration of a replay target determining circuit.

FIG. 4 is a diagram showing an overall configuration of a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a search / hit determination unit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a detailed configuration of a replay target determining circuit in a second embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a replacement order change selection circuit according to a second exemplary embodiment of the present invention.

[Explanation of symbols]

 1 ALU 3 cache storage device 5 main storage device 31 search unit 32 hit determination unit 33 replacement control unit 34 data unit

Claims (4)

[Claims] 1. A search unit, which is connected between an instruction processor and a main memory, has a plurality of entries having a V section, an Adr section, and an R section, a hit determination section, a replacement control section, and a data section. In a cache storage device provided with, when the instruction processor issues a memory access request to the cache storage device, a signal indicating that the request is a memory access request accompanying execution of a region clear instruction is sent to the cache storage device. An area clear request interface for sending is provided between the instruction processor and the cache storage device, and the entry of the search unit is an entry corresponding to the area of the main storage device accessed by the area clear instruction. An X section in which a flag is set is provided, and the instruction processor stores the cache data. When a memory access request is issued to the device, the request is a memory access request accompanying the execution of a region clear instruction, and the entry searched by the search unit is a cache miss, the X entry is added to the searched entry. When there is an entry with a flag set, the replacement control unit is provided with means for selecting the entry and designating a storage area of the data section corresponding to the entry as a replacement area. . 2. The cache storage device according to claim 1, wherein the data section is divided into a plurality of sets and the entries of the search section are divided into a plurality of sets. 3. A search unit, which is connected between an instruction processor and a main memory, has a plurality of entries having a V section, an Adr section, and an R section, a hit determination section, a replacement control section, and a data section. In a cache storage device provided with, when the instruction processor issues a memory access request to the cache storage device, a signal indicating that the request is a memory access request accompanying execution of a region clear instruction is sent to the cache storage device. An area clear request interface for transmission is provided between the instruction processor and the cache storage device, and when the instruction processor issues a memory access request to the cache storage device and the entry searched by the search unit is a cache miss. , Means for selecting an entry to be replaced, and the memory access When the memory request is associated with the execution of the area clear instruction, the replacement order of the R part of the searched entry is specified so that the replacement order of the R part of the selected entry becomes the highest, and the memory access is performed. When the request is not accompanied by the execution of the area clear instruction, the means for designating the replacement order of the R part of the searched entry so that the replacement order of the R part of the selected entry becomes the lowest. A cache storage device provided in a section. 4. The cache storage device according to claim 3, wherein the data section is divided into a plurality of sets, and the entries of the search section are divided into a plurality of sets.