JPH06178192A - Picture processor - Google Patents

Abstract

PURPOSE:To improve reproducibility by applying the original picture element data itself of one of corresponding four points as inter-polated picture element data corresponding to a pattern without using weighted average operation when there is the pattern to make the edge of an oblique line. CONSTITUTION:Each output of size comparison circuits 12 and 13 is inputted to AND gates 14 to 17. Accordingly, the output is generated from the AND gates 14, 15, 16, and 17 in response to conditions (1), (2), (3) and (4). Since the outputs of the AND gates 14 and 15 are inputted to an OR gate 18, and the outputs of the AND gates 16 and 17 are inputted to the OR gate 19, the outputs of the OR gates 18 and 19 are sent to a selector 11 as the control signal of the selector 11. Namely, control to select #1 picture element data in the case of the conditions (1) and (2) and select #2 picture element data in the case of the conditions (3) and (4) by the selector 11 is executed. Therefore, the output of an adder 10 of four points weighted average interpolated data, #1 data and #2 data are supplied to the input terminals 11a, 11b, and 11c of the selector 11.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus with improved reproducibility of diagonal lines and edges. 2. Description of the Related Art In an image processing apparatus such as an electronic still camera, coordinate conversion processing such as electronic zoom processing and image rotation processing is performed. For example, a rotation shift of a photographed image caused by camera shake that occurs when photographing with an electronic still camera is compensated by rotating the obtained image data by address (coordinate) conversion. At that time, in order to generate a necessary new pixel, a pixel interpolation method by four-point weighted average processing is used. FIG. 7 is a diagram for explaining the principle of the rotation processing based on the above coordinate conversion. The original image shown by a thin line is represented by θ.
It shows the address (coordinates) positional relationship when the image is rotated by only 1 to obtain a thick line image by oblique scanning. In the figure, white circles represent real pixels stored in the memory, and black circles represent virtual pixels read from the memory. Each address position P (00), P (1
0), P (20), P (01), P (11), P (2
Pixel data corresponding to 1), P (02), P (12), and P (22) are written in the field memory, and the pixel data at these address positions are used to make θ around the position P (00). Corresponding address positions Q (10), Q (20), Q (01), Q (1
1), Q (21), ... Are obtained and sent to the field memory as an address signal. For example, the address position Q (1
The virtual pixel addresses of 0), Q (20), Q (01), Q (11) are obtained as follows from the relationship shown in the figure. Q (10): x ... P (00) + cos θ y ... P (00) + sin θ Q (20): x ... P (00) +2 cos θ = P (10) +2 cos θ-1 y ... P (00) +2 sin θ = P (10 ) +2 sin θ Q (01): x ... P (00) -sin θ y ... P (00) + cos θ Q (11): x ... P (00) -sin θ + cos θ = P (01) -sin θ + cos θ y ... P (00) + cos θ + sin θ = P (01) + cos θ + sin θ−1 FIG. 8 shows an example of a circuit for generating the X address. In the XST register 111X, the pixel address to be read first, 0 in this example, is set, and XW
XW = cos θ shown in FIG. 7 is generated from the register 112X, and X shown in FIG. 7 is generated from the X0 register 113X.
0 = −sin θ has been generated. The output of the adder 114X is delayed by one clock (for one pixel) by the delay device 116X. The adder 114X adds cos θ from the XW register 112X and the output from the delay device 116X.
The output of the delay device 116X is added to the output (0 in this example) from the XST register 111X in the adder 118X. The delay device 117X outputs the output of the adder 115X to 1
Delay by H. The adder 115X is connected to the X0 register 11
The −sin θ from 3X and the output from the delay device 117X are added. The adder 119X adds the output of the delay device 117X and the output of the adder 118X and outputs the result as an X address signal. FIG. 9 shows an example of a circuit for generating a Y address signal similar to that shown in FIG. YST register 111Y
Is set to 0, YW = sin θ shown in FIG. 7 is generated from the YW register 112Y, and the Y0 register 11
From 3Y, Y0 = cos θ shown in FIG. 7 is generated.
The output of the adder 114Y is delayed by one clock (for one pixel) by the delay device 116Y. The adder 114Y adds sin θ from the YW register 112Y and the output from the delay device 116Y. The output of the delay device 116Y is the output from the YST register 111Y (0 in this example) and the adder 1
18Y is added. The delay device 117Y is the adder 1
The output of 15Y is delayed by 1H. The adder 115Y is
Cos θ from the Y0 register 113Y and the delay device 117
Add the output from Y. The adder 119Y adds the output of the delay device 117Y and the output of the adder 118Y and outputs the result as a Y address signal. By changing the set values of the XST register 111X and the YST register 111Y, it is possible to correct the blurring of the image in the horizontal and vertical directions.
2X, YW register 112Y, X0 register 113X,
The rotation angle is adjusted by changing the set value of the Y0 register 113Y. FIG. 10 is an address conversion diagram when the address conversion principle diagram shown in FIG. 7 is applied to the aspect ratio of 3 to 4 (768 pixels, 240 lines) shown in FIG. 11 and rotated by 30 degrees. It is shown. In this case, as shown in FIG. 11, one pixel has a horizontal and vertical size of 2.4: 1. At this time, XST = 0 XW = 0.866 X
0 = −2.4 × 0.5 YST = 0 YW = 0.5 / 2.4 Y0 = 0.8
66, and as is clear from the figure, the general formula expressing the X address Xmn and the Y address Ymn when the number of pixels is m and the number of lines is n is as follows. Xmn = XST + m * XW + n * X0 Ymn = YST + m * YW + n * Y0 For example, the address (coordinates) of the 0th line (n = 0) is (XY) = (0,0), (0.866,0.208) ，
(1.732, 0.417), ... In the first line (n = 1), (XY) = (-1.2,
0.866), (-0.334, 1.074), (0.
532, 1.28), ... Here, it is clear from the figure that the integer part of each address indicates the address Add and the decimal part indicates the interpolation coefficient K. For the interpolation processing, it is preferable to use a 4-point weighting method as shown in FIG. 12, for example. The address position Q to be read from the memory is determined by defining X1 and X2 as shown in the figure, and the four surrounding points P (11), P (21), P (1
2), using the weighted average of P (22), it is calculated by the following formula. Q = (1-Ky) X1 + Ky * X2 X1 = (1-Kx) P (11) + KxP (21) X2 = (1-Kx) P (12) + KxP (22) Therefore, Q = (1-Kx) ( 1-Ky) P (11) + Kx (1-Ky) P (21) + Ky (1-Kx) P (12) + Kx · Ky · P (22) (1) The operation of the formula (1) is one cycle. 4 pixel address P in
This can be realized by reading (11), P (21), P (12), and P (22) at the same time. The simultaneous reading of the four pixels can be performed using a memory configuration as shown in FIG. 13, for example. In the example shown in FIG. 13, even-numbered columns are arranged so that four pixels can be read by supplying an address once.
Even row dedicated memory (A), odd column, even row dedicated memory (B), even column, odd row dedicated memory (C) and odd column,
Four independent memories of the odd row memory (D) are provided. FIG. 14 shows an address generation circuit for reading data from a memory for performing an arithmetic operation by the above-mentioned four-point weighted average circuit, which is composed of column addresses 0 to 9 bits and row addresses 0 to 7 bits for odd column memory columns. An address, a column address for even column memory, a row address for odd row memory, and a row address for even row memory are generated. 0 for column address
The bits are output as the select signal HSEL and added by the adder 211 with bits 1 to 9. 1 to
9 bits become the column address for the odd column memory, and the adder 2
The output of 11 becomes the column address for the even column memory. Similarly, the 0-bit of the row address is output as the select signal VSEL, and is added by the adder 212 to 1 to 7 bits. Bits 1 to 7 become the row address for the odd row memory, and the output of the adder 212 becomes the row address for the even row memory. FIG. 15 shows an example of a circuit for performing the 4-point weighted average calculation shown in the equation (1) using the read data read from the memory. In FIG. 15, the selectors 21 and 22 are the selection signals HSEL obtained in FIG.
"H" terminal when is "H", "L" when "L"
The terminal is selected, and the selector 7 similarly selects the select signal V
The corresponding terminal is selected by SEL. Selector 21
To the selector 22, the even-numbered even-row read data and the odd-numbered even-row read data are input to the selector 22. The two outputs from the selector 21 are multiplied by the coefficients (1-Kx) and Kx by the multipliers 1 and 2, respectively. The outputs of the multipliers 1 and 2 are added by the adder 5 and output to the 2 input terminals (L, H) of the selector 7. on the other hand,
The two outputs from the selector 22 are the multipliers 3 and 3, respectively.
4 multiplies the coefficients (1-Kx) and Kx. The outputs of the multipliers 3 and 4 are added by the adder 6 and output to the other two input terminals (L, H) of the selector 7. The two outputs from the selector 7 are X1 and X2, which are multiplied by the coefficients (1-Kx) and Kx by the multipliers 8 and 9, respectively.
The outputs of the multipliers 8 and 9 are added by the adder 10 to obtain the interpolated data Q. As described above, the conventional image processing apparatus for performing the interpolation processing based on the original pixel data of four points has the horizontal and vertical directions among the original pixel data of four points. Since the interpolation data is obtained based on certain two original pixel data, as described below, when the diagonal line or the edge part is interpolated, the diagonal line or the edge part is jagged as shown in FIG. It becomes difficult to see the display screen. FIG. 16 is an image of an oblique edge, and the numerical values in the figure indicate the luminance level, 16 corresponds to the white level, and 0 corresponds to the black level. In this case, the brightness levels at the four corners are # 16 at the upper right end and # 0 at the other. When the above-described conventional interpolation processing is performed, as shown in the figure, the shaded area indicated by the dotted line is originally a black portion, but has some brightness level, so that it is grayed and completely black. There is a problem that the level part becomes slightly brighter, the diagonal line part becomes unclear, and the boundary part between the white part and the black part becomes jagged. Therefore, an object of the present invention relates to an image processing apparatus which improves the reproducibility of diagonal lines and edge portions in a four-point weighted average interpolation process. In order to solve the above-mentioned problems, the image processing apparatus according to the present invention calculates the weighted average of the interpolated pixel data based on the original pixel data of four points located in the vicinity thereof. The determining means determines the presence of a pattern forming an edge of an oblique line in the area surrounded by the four points based on the distribution mode of the image data of the four points, and the determining means. When it is determined that a pattern forming an edge of a diagonal line exists in an area surrounded by four points, the four points are determined as the interpolation pixel data corresponding to the pattern forming an edge of the diagonal line in the area regardless of the calculation means. And means for applying one of the original pixel data itself. According to the present invention, when a pattern forming an edge of a diagonal line exists in the area surrounded by the four points based on the distribution mode of the image data of the four points located in the vicinity, The original pixel data itself of any of the four points is used as the interpolated pixel data corresponding to the pattern forming the edge of the diagonal line, regardless of the four-point weighted average calculation. Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of an image processing apparatus according to the present invention. In FIG.
Elements having the same reference numerals as are elements having the same function. In this embodiment, the state of the triangular portions separated by diagonal lines is judged based on the mutual magnitude relation of the brightness levels at the four corners, and the interpolation process is stopped based on the judgment result. To eliminate deterioration of reproducibility. For example, in FIG.
Consider a case where the image data after interpolation (same as in FIG. 16) obtained by the conventional interpolation as shown in FIG. In the present embodiment, if the luminance level at three points of the image data (luminance level) at the four corners is "0", it is surrounded by these three points as shown in FIG. The brightness levels of the pixels in the area should all be "0". Therefore, in this case, all the brightness levels in the area A get "0", and there may be diagonal lines in the area B, but in this example, four-point interpolation processing is performed to obtain the interpolation data. It has gained. The recognition of the pattern when the original image has one diagonal line will be described with reference to FIG. Let the pixel brightness levels at the four corners of FIG. 3A be # 1, # 2, # 3, and # 4, respectively, and let the x-direction and y-direction distances of the interpolation pixel from # 1 be Kx and Ky, respectively. Condition (11): # 1 = # 4 and # 1 ≠ # 2 and # 1 ≠ #
In the case of 3, if Kx = Ky, it is recognized as a pattern as shown in FIG. 7B, and the interpolated pixels are on the straight line connecting # 1 and # 4, and the interpolation processing is performed as the pixel data on this straight line. The data of # 1 or # 4 may be output as it is without performing it. Condition (12): # 2 = # 3 and # 1 ≠ # 2 and # 2 ≠ #
When 4, when 1-Kx = Ky (Kx = 1-Ky),
Interpolated pixels are recognized as the pattern shown in FIG. 6C, and the interpolated pixels are on a straight line connecting # 2 and # 3, and the pixel data on this straight line is # 2 or # without performing interpolation processing.
The data of 3 may be output as it is. Next, the processing when the original image is an oblique edge as shown in FIGS. 4A to 4D will be described. Condition (21): # 1 = # 4 and # 1 = # 2 and # 1 ≠ #
If Kx> Ky in the case of 3, the pixel data in the area of the triangle (hatched portion) connecting # 1- # 2- # 4 including the diagonal edges shown in FIG. Alternatively, the data of # 4 may be output as it is. Condition (22): # 1 = # 4 and # 1 = # 3 and # 1 ≠ #
If Kx <Ky in the case of 2, it is recognized as the pattern shown in FIG. 9B, and the pixel data of # 1, # 3, or # 4 may be directly output as the pixel data in the shaded triangular area. . Condition (23): # 2 = # 3 and # 1 = # 2 and # 2 ≠ #
In the case of 4, if 1-Kx> Ky, it is recognized as the pattern shown in FIG. 7C, and if the pixel data in the shaded triangular area is the pixel data of # 2, # 1 or # 3, it is output as it is. good. Condition (24): # 2 = # 3 and # 2 = # 4 and # 1 ≠ #
In the case of 2, if 1−Kx <Ky, it is recognized as the pattern shown in FIG. 7D, and if the pixel data in the shaded triangular area is the pixel data of # 2, # 3 or # 4, it is output as it is. good. Next, if there are four points in the shaded area or white area shown in FIG. 4E, the pixel data at all four points may be made equal. That is, when condition (31): # 1 = # 2 = # 3 = # 4, K
Regardless of x and Ky, each pixel data may be the data of # 1, # 2, # 3 or # 4 as it is. From the above, the conditions (11), (12) and (31) are included in the conditions (21) to (24). These can be summarized as the following conditions (1) to (4). Condition (1): # 1 = # 4 and # 1 = # 2 and Kx ≧ Ky
If so, the pixel data of # 1 is output as it is. Condition (2): # 1 = # 4 and # 1 = # 3 and Kx ≦ Ky
If so, the pixel data of # 1 is output as it is. Condition (3): # 2 = # 3 and # 1 = # 2 and 1-Kx ≧
If it is Ky, the pixel data of # 2 is output as it is. Condition (4): # 2 = # 3 and # 2 = # 4 and 1-Kx ≦
If it is Ky, the pixel data of # 2 is output as it is. This embodiment is based on the conventional circuit shown in FIG. 15, but includes a selector 11, magnitude comparison circuits 12 and 13,
AND gates 14 to 17 and OR gates 18 and 19 are added. The magnitude comparison circuit 12 has the above conditions (1) to (1).
In the circuit for judging the relative size relationship of # 1 to # 4 in (4), # 1 = # 2, # 1 = # 3, # 1 = # 4, #
When 2 = # 3, # 2 = # 4, an output is generated from each output terminal. Further, the magnitude comparison circuit 13 includes Kx, Ky, 1-K.
This is a circuit for judging the mutual magnitude relation of x, and Kx ≧ K
When y, Kx≤Ky, 1-Kx≥Ky, 1-Kx≤Ky, an output is generated from each output terminal. The outputs of the magnitude comparison circuits 12 and 13 are input to the AND gates 14 to 17, as shown in the figure. Therefore, the AND gates 14, 15, 16 and 17 generate outputs in response to the conditions (1), (2), (3) and (4). The outputs of AND gates 14 and 15 are O
The output of the AND gates 16 and 17 is ORed to the R gate 18.
Since it is input to the gate 19, the outputs of the OR gates 18 and 19 are sent to the selector 11 as the control signal of the selector 11. That is, in the case of the conditions (1) and (2), #
In the case of the conditions (3) and (4), the pixel data of 1 is # 2.
The pixel data of 1 is selected by the selector 11. Therefore, the input terminals 11a, 1 of the selector 11
The outputs of the adder 10, which are 4-point weighted average interpolation data, the data of # 1 and the data of # 2 are supplied to 1b and 11c. FIG. 5 shows a configuration example of the magnitude comparison circuits 12 and 13. For example, the value obtained by the subtractor 121 #
The difference data between 1 data and # 2 data is the NOR gate 122.
Is input, and when all the inputs are "L", "H" is output. Further, FIG. 6 shows a circuit in which two data are provided with some margin in consideration of redundancy.
In this example, when the difference between the two data is within a predetermined allowable value x, both data are judged to be the same and are processed. Therefore, the absolute value B of the difference between the two data obtained by the subtractor 121 is calculated by the absolute value circuit 123, and the comparator 124
Then, the absolute value is compared with the allowable value A (= x), and A ≧ B
Produces an output when. As described above, according to the image processing apparatus of the present invention, when the pixel interpolation in the four-point weighted average is performed, the sharpness is obtained even when the oblique line or the oblique edge is included. Thus, it is possible to avoid deterioration of reproducibility of diagonal lines and edge portions.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration block diagram showing an embodiment of an image processing apparatus according to the present invention. FIG. 2 is a diagram for explaining the operation of the embodiment shown in FIG. FIG. 3 is a diagram for explaining the operation of the embodiment shown in FIG. FIG. 4 is a diagram for explaining the operation of the embodiment shown in FIG. 5 is a block diagram showing a configuration example of a size comparison circuit of the embodiment shown in FIG. FIG. 6 is a block diagram showing another configuration example of the size comparison circuit of the embodiment shown in FIG. FIG. 7 is an address generation principle diagram showing an image rotation principle in the embodiment of the present invention. 8 is a circuit diagram for generating an X address according to the principle diagram shown in FIG. 7. FIG. 9 is a circuit diagram for generating a Y address according to the principle diagram shown in FIG. 7. FIG. FIG. 10 is a diagram showing an address generation principle when the principle shown in FIG. 7 is applied to actual image rotation. 11 is an image configuration diagram which is a basis of the principle diagram shown in FIG. FIG. 12 is a principle diagram of performing interpolation processing by an interpolation processing circuit 7 according to an embodiment of the present invention by a 4-point weighted average calculation. FIG. 13 is a memory configuration diagram used for performing the interpolation process shown in FIG. 12; 14 is a circuit diagram showing an example of a memory read address generation circuit used in the interpolation processing shown in FIG. 12; 15 is a circuit diagram showing an example of the interpolation process shown in FIG. FIG. 16 is a diagram for explaining a problem of the conventional image processing apparatus. [Explanation of reference numerals] 1-4,8,9 multipliers 5,6,10 adders 7,11,12,22 selectors 12,13 size comparison circuits 14-17 AND gates 18,19 OR gates

Claims (1)

Claims: The interpolation pixel data is calculated by a weighted average calculation based on the original pixel data of four points located in the vicinity of the interpolation pixel data; Judgment means for judging that a pattern forming an oblique line edge exists in the enclosed area, and the judgment means judges that a pattern forming an oblique line edge exists in the area surrounded by the four points. Sometimes, a means for applying the original pixel data itself of any of the four points as interpolation pixel data corresponding to a pattern forming an edge of an oblique line in the area, is provided. Image processing device.