JPH06178129A - Demodulator - Google Patents

Abstract

PURPOSE:To effectively use a computer for control by making a modulator/ demodulator perform the part of a transmission control and reducing the processing amount of the host MPU, etc., of a facsimile device. CONSTITUTION:The shift clock of a serial parallel modulator 109 is also inputted in a 8-frequency divider 107, the output of the modulator 109 is written in an output register 108 every 8-bit, and at the same time, the output of an FF 106 becomes 1. Thus, a host MPU monitors the output of the. FF 106, and if the data of the output register 108 is read when this output becomes 1, the output of the FF 106 is also reset at the same time and becomes 1. Namely, if the data of the output register 108 is read every time the output of the FF 106 becomes 1, the host MPU is capable of directly obtaining image data. As a result, the processing amount of the host MPU, etc., of a facsimile device can be reduced by making a modulator/demodulator perform the part of a control transmission.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator used for G3 standard facsimile communication.

[0002]

2. Description of the Related Art Conventionally, in a modulator / demodulator used in a communication part of a facsimile machine for performing G3 standard facsimile communication, CCITT recommendation T.264 is used. The functions related to encoding and decoding for compressing the transmission amount conforming to No. 4 were not installed. Here, CCITT Recommendation T. An encoding method based on 4 will be described.

First, one-dimensional coding called MH coding will be described. When transmitting an image original, first, the data for one line is read horizontally. Then, the encoding is performed for each line. The line spacing is 3.8.
5 lines / mm or 7.7 lines / mm. Further, all data of one line is 1728 pixels (white =
0, black = 1 bit).

Focusing on the data of one line, as shown in FIG. 5, the white bit sequence and the black bit sequence are repeated. In the MH system, encoding is performed so that the number of bits (called run length) is transmitted for each of the white and black bit strings. There are make-up codes and terminating codes for white and black. An example of makeup code is shown in FIG. 6, an addition of makeup code is shown in FIG. 7, and an example of termination code is shown in FIG.
Shown in.

In the case of white or black of less than 64 bits, only the terminating code shown in FIG. 8 is coded. 64
In the case of a bit string of more than bits, it is encoded by a combination of make-up code and terminating code. Figure 5
In the case of, each pixel is converted into a code as shown below and transmitted. That is, 1728 pixels are compressed to 31 bits.

The data encoded as described above is
As shown in FIG. 3, EOL (End Of Line: 0
12 bits for each 00000000001) and 6 consecutive signals of EOL called RTC are added at the end of the image signal of one page. Next, one-dimensional encoding + two-dimensional decoding called MR encoding will be described. For MH encoding,
After EOL, one Tag bit is added. Ta
When g bit is 1, the data for one line after that is 1.
Indicates dimensional coding and is coded as previously described.

When the Tag bit is 0, the data for the next one line represents two-dimensional coding, and the data for the immediately preceding one line is used as reference data and is coded with a relative value (change) from the pixel. By further converting the data, the data is further compressed.
The ratio of one-dimensional encoding is 1 line out of 2 lines or 1 line out of 4 lines. Conventionally, the facsimile machine has the configuration shown in FIG. In FIG. 9, the analog signal input from the line interface unit 95 is demodulated by the modulation / demodulation circuit 94 and converted into a digital signal.
The modulation / demodulation circuit 94 is purely configured to perform demodulation processing of received data and modulation processing of transmission data, and, for example, only outputs demodulated data as it is to the MPU 91 of the host. Reference numeral 92 is a ROM that stores the operation control procedure of the MPU 91, 93 is a RAM, and 96 is an I / O such as a reader that reads image information, a printer that outputs image information, and an operation unit.

Therefore, the work of extracting the image data from the received data, decoding each code to decode the white or black run length, and checking whether the received data of the line is error-free data are all performed by the host. MPU
It was processed by 91.

[0009]

Therefore, the processing of data during communication requires a lot of processing time of the MPU 91. Further, in the above-mentioned conventional example, the host MPU 91 decodes the data encoded for each line during the reception of the image data, converts the data into white or black run lengths, expands the image data, and prints or stores the data in the memory. It is necessary to check whether the image data has a reception error while performing processing such as storing. For this reason, it is necessary to add all the decoded run-length data line by line and compare the number with the number of pixels corresponding to the image original. If they are equal, there is no error, and if they are not equal, there is an error. Therefore, a high-performance MPU having a high processing speed is required, and an inexpensive MPU cannot be used.

[0010]

The present invention has been made for the purpose of solving the above-mentioned problems, and has the following structure as one means for solving the above-mentioned problems. That is, G3
Decoding means for demodulating a received image signal in standard facsimile communication and decoding a one-dimensional encoded code included in the demodulated image data into a white or black run length, and an EOL code in the demodulated image data. The detecting means for detecting, the calculating means for obtaining the sum of the run lengths decoded by the decoding means between the EOL code and the next EOL code, the setting means for setting an arbitrary value from the outside, and the setting means Comparing means for comparing the set value with the total value of run lengths calculated by the computing means, storage means for storing the comparison result by the comparing means, and the storage result for the storage means can be read out from the outside. And a reading means configured as described above.

Alternatively, a decoding means for demodulating a received image signal in facsimile communication of G3 standard and decoding a one-dimensional encoded code included in the demodulated image data into a white or black run length, and the decoding means It comprises a generating means for generating a bit string of 0 or 1 having a bit number proportional to the decoded run length value, and a reading means for reading out the bit string generated by the generating means from the outside.

Alternatively, a decoding means for demodulating a received image signal in facsimile communication of G3 standard and decoding a one-dimensional code included in the demodulated image data into a white or black run length, and the decoding means A storage unit for storing the decoded white or black run length value and a reading unit configured to be able to read the value stored in the storage unit from the outside are provided.

Alternatively, in a modulator / demodulator for demodulating a received image signal in G3 standard facsimile transmission, a detection means for detecting an EOL code in received information and a predetermined number of EOL code detections by the detection means are continuously received. The storage means stores the information that has been stored, and the reading means configured to read the data stored in the storage means from the outside.

[0014]

With the above-mentioned structure, the host MPU of the facsimile machine requires very little software processing at the time of image reception, so that an inexpensive MPU can be used.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a drawing best showing the characteristics of the demodulation unit in the facsimile apparatus of one embodiment according to the present invention. The part shown in FIG. 1 corresponds to a part of the part corresponding to the modulation / demodulation circuit 94 in FIG. 9 described above, and the other parts of the facsimile apparatus can use a well-known structure, and therefore detailed description thereof is omitted.

In FIG. 1, reference numeral 101 denotes an MH / M for selecting an encoding method for facsimile communication in the G3 standard.
An R selection register 102 is a line bit setting register for setting the number of data bits of one image line, 103
Is an error register that stores the presence or absence of an error in the received image data, and 104 is a comparator that compares the outputs of the accumulator 105 and the line bit setting register 102 when the EOL detector 117 detects an EOL code. If so, the error information 1 is output to the error register 103.

105 is an accumulator, 111 is an AND
A gate, 112 is an OR gate, 113 is a down counter with preset input, 116 is an MH decoder for decoding the run length of MH code and white and black, 114
Is an oscillator, 110 is an AND gate, 108 is an 8 frequency divider,
106 is a set-up flip-flop, 109 is 8
A bit serial-to-parallel converter, and 108 is an 8-bit output register.

Reference numeral 115 is a run length register for storing and outputting the run length data decoded by the MH decoder 116, 124 is a set reset flip-flop, and 118 is a run length data decoded by 116. W / to memorize and output white or black
B register, 119 is shift register, 120 is CCI
TT Recommendation V. 29, and CCITT Recommendation V.29. 27ter
A demodulation section for demodulating the modulated wave of the signal, 121 is an output register for storing and outputting the parallel output of the shift register 119 every 8 bits, and 122 is a frequency divider for dividing the data clock output from the demodulation section 120. 8 divider for 1
23 to 125 are settling flip flops.

The operation at the time of transmitting / receiving an image signal in this embodiment having the above configuration will be described below. First, CCITT
Recommendation T. A series of operation examples of transmitting and receiving image signals conforming to H.30 will be described with reference to FIG. FIG. 2 shows the CCITT recommendation T.264 in this embodiment. It is a figure which shows a series of transmission control procedures of transmission and reception of the image signal based on 30.

In FIG. 2, the transmitting side first calls the receiving side. The receiving side that has detected this called is CE
The D signal (2100 Hz) is transmitted and the DIS signal is output. The DIS signal includes information on the capability of the reception side facsimile (communicable bit rate, recording width capability, etc.), but information about the coding capability of the receiving side is also transmitted at the same time.

The transmitting side, which has received this DIS, determines the communication bit rate, recording width, coding method, etc., and sends it out as a DCS signal. After that, the training signal of the determined communication speed is transmitted, and subsequently, the TCF signal which is continuous data of 0 is transmitted. On the receiving side, the TCF signal is checked, and if the number of errors (1) is less than a certain amount, it is determined that communication is possible and the CFR signal is output.

The transmitting side which has received the CFR outputs the image signal to be transmitted subsequently. An example of the image signal transmission format is shown in FIG. Image signal transmission format,
There are two types of messages, one-dimensional coding only (MH) and one-dimensional coding + two-dimensional coding (MR). First, the image data receiving operation of this embodiment when MH coding is selected by the DCS signal will be described.

The host MPU reads the DCS signal,
When MH coding is recognized, 1 is written in the MH / MR selection register 101 of FIG. Then, since the output of the MH / MR selection register 101 is connected to one output of the OR gate 112, the output of 112 is fixed to 1. Further, the host MPU writes 0 in the line bit setting register 102.

Here, a detailed view of the EOL detector 117 and the shift register 119 is shown in FIG. Shift register 1
19 is 13 bits, 12 bits on the left side are connected to the EOL detector 17, and 000000000001 (EOL
When the code) is detected, the output becomes 1. When the first EOL of the image data shown in FIG. 3 is demodulated by the demodulation unit 120 and input to the shift register 119, the EOL detector 1
The output of 17 becomes 1. Since the output of the OR gate 112 is 1, the output of the AND gate 111 is 1, and the reset input of the accumulator is 1. Therefore, the accumulator 105 is reset.

At the same time, the comparator 104 outputs the data of the line bit setting register 102 and the accumulator 10 to each other.
Compare the outputs of 5. Here, since 0 is initially written in the line bit setting register 102, the comparison results are equal and the output is also 0. Therefore, 0 is also stored in the error register 103. The set-set flip-flop 125 is set when the output of the EOL detector 117 goes to one. Therefore, if the host MPU monitors the output of the set reset flip-flop 125, it can be seen that the EOL has been detected. Host MPU
Is set after the output of the set reset flip-flop 125 first becomes 1.
Then, the number of data bits for one line designated by the DCS signal is set. For example, in the case of A4 size paper, it is 1,728.

After the first EOL reception, the MH-coded received data is input to the shift register 119. The MH decoder 116 connected to the parallel output of the shift register 119 decodes the white and black run lengths. Each time the run length value is decoded, M
The dec output of the H decoder 116 rises, and the W / B output register 118 is written with data of 0 for white and 1 for black.

At the same time, the run length of the decoded result is written in the run length register 115, and the run length of the decoded result is written in the down counter 113 as a preset value. In addition, the MH decoder 116
The output of is also input to the accumulator 105,
Each time the run length is decoded, the accumulator 10
Added to 5.

The host MPU has a flip-flop 124.
Of the output of W / B
By reading the values of the output register 118 and the run length register 115, the white and black run lengths can be directly extracted. Further, the down counter 113, when the decoded preset value is set, counts down the clock oscillated by the oscillator 114 and outputs 1 until 0.

With this configuration, the AND gate 110 outputs clocks corresponding to the number of preset values. The clock is serial-parallel converter 10.
9 shift clock input. Therefore, the data of the serial / parallel converter 109 is shifted by the preset value, that is, the run length value. At that time, W / B is input to the input of the serial-parallel converter 109.
The output of the register 118 (0 for white, 1 for black) is connected, and the final image data is reproduced in the serial-parallel converter 109.

The shift clock of the serial / parallel converter 109 is also input to the divide-by-eight frequency divider 107.
The output of the serial / parallel converter 109 is written in the output register 108 for each bit, and at the same time, the output of the flip-flop 106 becomes 1. Therefore, the host MPU monitors the output of the flip-flop 106, and if the data of the output register 108 is read when this output becomes 1, the output of the flip-flop 106 is reset and becomes 0 at the same time. That is, the host MPU can directly obtain the image data by reading the data 108 every time the output of the flip-flop 106 becomes 1.

As described above, the MH-encoded data of one line is sequentially decoded and output to the host MPU, while the accumulator 105 adds all the run lengths. When the EOL is received at the end of one line, the output of the EOL detector 117 rises. Accordingly, the comparator 104 compares the value set in the line bit setting register 102 with the sum of the run lengths added by the accumulator 105 after the previous EOL. When the comparison results are equal, there is no error in the received data, the output of the comparator 104 becomes 0, and 0 is set in the error register 103.

If the addition result of the accumulator 105 is not equal to the set value of the line bit setting register 102, it means that the received data has an error. At that time, the output of the comparator 104 becomes 1, and 1 is set in the error register 103. Also, when EOL is detected by the EOL detector 117, the set-set flip-flop 125 is also set to 1. Therefore, the host MPU can know the reception of the EOL only by monitoring the output of the set reset flip-flop 125.

At that time, the error bit is read out, and if it is 0, it can be seen that the received data is normally received without any error. Therefore, when the error bit is 0, the image data is processed normally. On the other hand, if the error bit is 1, it means that an error has been detected in the received data corresponding to the image data of the one line, an error has occurred during data transmission, and the received image data is used. Copy the previous line without doing. Alternatively, the line may be subjected to processing such as skipping.

As described above, according to this embodiment, the host MPU can directly obtain the image data of the MH-encoded received image data without special control, and the received data of each line can be obtained. You can also check the error. Further, at the end of the image data, as shown in FIG. 3, data called RTC in which six EOLs are continuous is transmitted. However, in this embodiment, this RT
RTC detection in C data is also possible.

The counter 126 of FIG. 1 is a counter which outputs 1 when 6 clocks are input. For this reason,
The EOL is detected by the EOL detector 117, the accumulator is reset, and at the same time, the clock is also input to the counter 126. In the normal case, before the next EOL is detected, a certain run length is decoded by the MH decoder 116 and output from the down counter 113.

Therefore, the counter 126 is reset, and if the run length is not detected and the EOL is repeated 6 times, the counter 126 outputs 1. Therefore, the host MPU can know the end of the image data only by monitoring this output. Next, MR encoding (1
The receiving operation in the case of (dimensional coding + two-dimensional coding) will be described.

In the transmission control procedure shown in FIG. 2, when MR encoding is instructed, the receiving-side host MPU sets MH /
0 is written in the MR selection register 101. Then, since one input of the OR gate 112 is 0, the output of 112 becomes 1 only when the other input terminal is 1, that is, when the bit at the right end of the shift register 119 shown in FIG. 4 is 1.

Therefore, the output of the AND gate 111 is E
When the OL is detected and the next bit is 1, that is, when the EOL before the line of the one-dimensional encoding is detected, the value becomes 1 and the contents of the accumulator are reset. Next EO
When L is detected, the error bit 103 is set to 1 or 0 by the comparator 104 according to the presence or absence of an error in the received data, as in the case of MH encoding.

After that, since the two-dimensional coding is performed, the host MPU performs the conventional decoding. For that purpose, it is necessary to directly read the reception data demodulated by the demodulation unit 120. At that time, the serial output of the shift register 119 is directly read by the data clock from the demodulation unit 120, or the value of the output register 121 written from the shift register 119 every 8 bits is output to the set-set flip-flop 123. It suffices to read each time when becomes 1.

That is, according to the present embodiment, even in the case of the MR coding, it is possible to perform the run-length decoding, the image data decoding, and the check for the presence or absence of an error for each line for the one-dimensional coding portion. . Also, R
Also for TC, since EOL + 1 is received 6 times in succession, the counter 126 becomes 1 and can be detected in this embodiment as described above.

In the above description, an example in which the output register 108 and the output register 121 have an 8-bit configuration has been described, but the present invention is not limited to the above example, and any number of bits may be used. At that time, the frequency division ratios of the frequency divider 107 and the frequency divider 122 and the number of bits of the serial-parallel converter may be changed according to the number of bits. Further, since the file bit in one line shown in FIG. 3 is a bit string of 0 for guaranteeing the minimum transmission time of one line, there is no data decoded by the MH decoder 116 and there is no influence.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus. As described above, according to the present embodiment, the host MPU sets the white and black run length values at the time of receiving one-dimensionally decoded image data by configuring the facsimile device using the above-described modulation / demodulation device. It becomes possible to read.

Further, it is possible to directly read in as a bit string of white and black image data. Further, the reception data error for each line can be confirmed only by monitoring a bit indicating that the EOL has been detected and checking the bit indicating the error each time the EOL is detected. Furthermore, for RTC detection, it is only necessary to monitor the bit indicating it.

As described above, since the load of the software processing of the host MPU is greatly reduced at the time of receiving the image data, other processing can be performed in parallel, or the facsimile apparatus can be configured by a cheaper MPU. effective.

[0045]

As described above, according to the present invention, various controls can be substituted in the demodulator, and the load on the control computer, which controls the overall control of the facsimile machine, is greatly reduced. It is no longer necessary to use a high-performance computer as a computer, and the facsimile machine can be constructed at low cost.

Further, by significantly reducing the load on the control computer that controls the overall control, other processing can be performed, and a demodulation device that can provide a high performance facsimile apparatus can be provided. .

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment according to the present invention.

FIG. 2 is a diagram showing a transmission control procedure in facsimile communication in the present embodiment.

FIG. 3 is a diagram showing a detailed configuration of an image signal in communication of the present embodiment.

FIG. 4 is a diagram showing a detailed configuration of a shift register SR shown in FIG.

FIG. 5 is a diagram showing a pixel configuration example of one line.

FIG. 6 is a diagram showing a make-up code.

FIG. 7 is a diagram showing a make-up code (addition).

FIG. 8 is a diagram showing a termination code.

FIG. 9 is a diagram showing a configuration example of a general facsimile machine.

[Explanation of symbols]

 101 MH / MR selection register 102 line bit setting register 103 error register 104 comparator 105 accumulator 108, 121 output register 109 serial-parallel converter 113 down counter 114 oscillator 115 run length register 116 MH decoder 117 EOL detector 118 W / B register 119 Shift register 120 demodulator 122 frequency divider 126 counter

Claims (4)

[Claims] 1. Decoding means for demodulating a received image signal in G3 standard facsimile communication, and decoding a one-dimensionally encoded code included in the demodulated image data into a white or black run length, and the demodulating means. Detection means for detecting the EOL code in the image data, operation means for obtaining the sum of the run lengths decoded by the decoding means between the EOL code and the next EOL code, and an arbitrary value can be set externally Setting means, comparing means for comparing the value set in the setting means with the sum of the run lengths calculated by the calculating means, storage means for storing the comparison result by the comparing means, and the storage means And a reading unit configured to be able to externally read the storage result of the demodulation device. 2. A received image signal in G3 standard facsimile communication is demodulated and included in the demodulated image data.
Decoding means for decoding the dimensionally encoded code into a white or black run length, and generating means for generating a bit sequence of 0 or 1 having a bit number proportional to the value of the run length decoded by the decoding means, A demodulation device comprising: a reading unit configured to read the bit string generated by the generating unit from the outside. 3. A demodulated image signal received in G3 standard facsimile communication, and 1 included in the demodulated image data.
Decoding means for decoding the dimensionally encoded code into white or black run lengths, storage means for storing the white or black run length values decoded by the decoding means, and values stored in the storage means And a reading unit configured to be able to read from the outside. 4. A demodulating device for demodulating a received image signal in G3 standard facsimile transmission, wherein a detecting means for detecting an EOL code in received information and a predetermined number of EOL code detections by the detecting means are continuously received. A demodulation device comprising: a storage unit that stores the information stored therein; and a read unit configured to read the data stored in the storage unit from the outside.