JPH06177340A - Semiconductor integrated circuit having logic circuits - Google Patents

Abstract

PURPOSE:To essentially increase the operation speed of a CMOS circuit or a BiMOS circuit in a semiconductor integrated circuit. CONSTITUTION:The driving capability of MOSFET's QP1, QP2 of adjacent connection to the operation potential point Vcc, out of a plurality of series-connected MOSFET's QP1, QP2, QP3 in a CMOS circuit part is set larger than the driving capability of MOSFET QP3 of adjacent connection to a circuit node 1. Thereby the ON resistance of QP1, QP2 of adjacent to the operation potential point Vcc is set small, drain parasitic capacitance of QP2 of adjacent connection to the circuit node 1 is set small, and parasitic capacitances at the mutual connection point of a plurality of the series-connected MOSFET's QP1, QP2, QP3 and the parasitic capacitance at the circuit node 1 are charged at a high speed, so that the operation speed is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit having a logic circuit having a CMOS or BiCMOS circuit configuration.

[0002]

2. Description of the Related Art "Super High Speed M" issued on February 10, 1986
OS device ”, edited by Takuo Sugano, edited by Shin Kayama, Baifukan PP.
As described in 235-236, most highly integrated semiconductor integrated circuits are made by CMOS technology. The greatest feature of this CMOS circuit is low power consumption. The power consumption when stationary is only a small amount due to the leakage current of the device, and the power consumption during operation is also
Power consumption is due to current charging the load capacitance and CMOS
Only the power due to the through current flowing through the CMOS circuit during the transition state in which the signal output from the circuit switches.

The power consumption of the semiconductor integrated circuit by the CMOS circuit is as follows: average operating frequency f of the internal CMOS circuit, average load capacitance C _{L of} the circuit, average operating probability R of the internal CMOS circuit.
And is proportional to the square of the voltage amplitude V of the signal (which is usually equal to the power supply voltage in a CMOS circuit). Therefore, f is increased to speed, fast C _L is increased by high integration,
Highly integrated LSI consumes a large amount of power, and some LSIs require a special container for heat dissipation. Therefore, reduction of power consumption is strongly demanded, and it is necessary to reduce these values in order to reduce power consumption. Conventionally, a method of reducing the power consumption by reducing the power supply voltage V to reduce the signal amplitude has been attempted, and an LSI in which the power supply voltage has already been reduced from 5V to 3.3V has been manufactured. Further, since the CMOS circuit has a slower operation speed than the bipolar circuit, higher speed is also required. On the other hand, in the CMOS circuit, the load driving capability of the N-channel MOSFET is larger than that of the P-channel MOSFET, so that the NAND circuit operates at the highest speed. However, the number of circuits is smaller and the high-speed operation can often be realized in combination with the NOR circuit rather than realizing a desired logical function using only the NAND gate.
Therefore, as seen in the decoder circuit of the memory LSI, a combination circuit of NAND and NOR is generally used.
Further, the BiCMOS circuit, which is a combination of a CMOS circuit and a bipolar transistor, draws attention because it operates at a higher speed than the CMOS circuit because the stationary power consumption, like the CMOS circuit, is only the power consumption based on the leakage current of the device. There is. The high-speed performance of the BiCMOS circuit is based on the high load driving ability by driving the load by amplifying the current flowing in the P-channel MOSFET or the N-channel MOSFET with a bipolar transistor.
Since the circuit configuration is a circuit in which a bipolar transistor for driving a load is added to the CMOS circuit, the NAND gate operates at a higher speed than the NOR gate, but a combination circuit of the NAND and NOR circuits is used like the CMOS circuit. As described above, the BiCMOS gate has a high load driving ability because it drives a load by using a bipolar transistor. Therefore, for example, with a load capacitance of 1 pF, the BiCMOS gate has about 2
Double speed operation. However, when the load capacitance is as small as about 0.1 pF, the speed-up effect by driving the load by using the bipolar transistor and the increase in the delay time by driving the load through the bipolar transistor become almost equal, Only operating speeds comparable to those of CMOS circuits have been realized. Therefore, in the integrated circuit, a CMOS circuit is generally used when the load is light and a BiCMOS circuit is used when the load is heavy. Therefore, when an LSI is designed with such a standard and there are many circuits with a light load, the BiCMOS circuit is used in a small proportion, and the LS configured by the CMOS circuit is used.
It is difficult to greatly improve the performance of I. Also,
The area of the current BiCMOS circuit is about four times larger than that of the CMOS circuit. If BiCMOS circuit is heavily used, L
The number of circuits that can be mounted on the SI is about 1/2 of that when a CMOS circuit is used, and it is difficult to realize a highly integrated LSI. If the number of circuits that can be mounted on the LSI is reduced, it becomes an obstacle to high-speed operation. That is, to realize a circuit having the same function, more LSIs are required. Along with this, it becomes necessary to transmit signals between LSIs, and the delay time increases accordingly. Furthermore, there is a drawback that the cost increases as the required number of LSIs increases. As described above, the CMOS and BiCMOS circuits are required to further reduce the power consumption and the operation speed, and the BiCMOS circuits are also required to reduce the circuit area.

[0004]

As mentioned above, the CMO is used.
In order to realize higher speed of semiconductor integrated circuits such as SLSI and BiCMOSLSI, it is essentially necessary to further speed up CMOS logic circuits of semiconductor integrated circuits. Therefore, it is an object of the present invention to provide a semiconductor integrated circuit having a CMOS logic circuit which realizes an essentially high speed.

[0005]

To achieve the above object, a semiconductor integrated circuit according to a typical embodiment of the present invention is
A plurality of MOSFETs (Q _P1 , Q _P2 , Q _P3 ) of the first conductivity type whose source / drain paths are connected in series between the first operating potential point (Vcc) and the circuit node (1), and source / drain A plurality of MOSFETs (Q _N1A , Q _N2A) of the second conductivity type opposite to the first conductivity type and connected in parallel between the circuit node (1) and the second operating potential point (V _EE1 );
Q _N3A ), each of the plurality of input signals being applied to the gates of the corresponding FETs of the plurality of MOSFETs of the first conductivity type and the plurality of MOSFETs of the second conductivity type. A logic circuit for generating logic signals of the plurality of input signals, and the plurality of first conductivity type MOSFETs (Q _P1 ,
Of the Q _P2 and Q _P3 ), the driving capability of the MOSFET (Q _P1 , Q _P2 ) connected near the first operating potential point (Vcc) is connected near the circuit node (1). M
It is characterized in that it is set to be larger than the driving capability of the OSFET (Q _P3 ).

[0006]

In the CMOS logic circuit, the source / drain paths of a plurality of MOSFETs are connected in series and the plurality of MOSFETs are connected in series.
By connecting the source and drain paths in parallel with each other, it is possible to generate a logical signal for a plurality of input signals. In such a CMOS logic circuit, the first operating potential point (Vc
There is a parasitic capacitance that cannot be ignored at the interconnection point of the MOSFETs (Q _P1 , Q _P2 , Q _P3 ) connected in series between c) and the circuit node (1). This plurality of MOSFETs connected in series (Q _P1 , Q
_In order to quickly generate a predetermined voltage from the first operating potential point (Vcc) to the circuit node (1) by making _P2 and _QP3 ) conductive, it is necessary to connect each interconnection point via the on resistance of each MOSFET. The parasitic capacitance needs to be charged quickly. According to the representative embodiment of the present invention, the driving capability of the MOSFETs (Q _P1 , Q _P2 ) connected close to the first operating potential point (Vcc) is connected close to the circuit node (1). MOSF
Since it is set larger than the drive capacity of ET (Q _P3 ), M connected close to the first operating potential point (Vcc)
The on-resistance of the OSFETs (Q _P1 , Q _P2 ) is set small and M connected close to the circuit node (1)
The parasitic capacitance of the drain region of the OSFET (Q _P3 ) is set small. Therefore, a plurality of MOSFEs connected in series
A semiconductor integrated circuit having a CMOS logic circuit in which the parasitic capacitance of the interconnection point of T (Q _P1 , Q _P2 , Q _P3 ) and the parasitic capacitance of the circuit node (1) are charged at high speed, and an essentially high speed is realized. A circuit can be provided. Other objects and features of the present invention will be apparent from the following examples.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a plane layout diagram and a sectional view of a 3-input NOR circuit having the BiCMOS circuit configuration shown in FIG. 2 formed on an LSI.

In the BiCMOS three-input NOR circuit of FIG. 2, three inputs are applied to the gates G1, G2, and G3, and source / drain paths are connected in series between the positive power supply Vcc and the base of the bipolar transistor Q ₀ . P channel type MOSFETs Q _P1 , Q _P2 , Q _P3 and 3 inputs are gate G
N-channel type MOSFETs Q _N1A , Q applied to G1, G2 and G3 and having source / drain paths connected in parallel between the base of the bipolar transistor Q ₀ and the negative power source V _EE1.
N2A , Q _N3A and an N-channel MOSFET Q _whose three inputs are applied to the gates G1, G2, G3 and whose source / drain paths are connected in parallel between the output OUT of the emitter of the bipolar transistor Q ₀ and the negative power supply V _{EE. N1B} , Q _N2B , Q
_It is composed of _N3B and. Therefore, the BiCM of FIG.
In the three-input NOR circuit of OS, when all three inputs are at low level, P-channel MOSFETs Q _P1 , Q _P2 , Q _P3
And the bipolar transistor Q ₀ become conductive, and N-channel type _MOSFETs Q _N1A , Q _N2A , Q _N3A , Q _N1B , Q
_N2B and Q _N3B become non-conductive, and the output OUT becomes high level. On the other hand, if any of the three inputs goes high,
The bipolar transistor Q ₀ becomes non-conductive, and the output O
UT becomes low level, and the NOR function for three inputs is realized.

As shown in the top plan layout of FIG. 1, a bipolar transistor Q _{0 is provided} on the right side of the semiconductor chip.
Is placed, and a P-channel MOSFET is located next to it.
Q _P1 , Q _P2 , and Q _P3 are arranged, input side N-channel type MOSFETs Q _N1A , Q _N2A , and Q _N3A are arranged on the left side thereof, and an output side N-channel type MOSFET is arranged on the leftmost side.
Q _N1B , Q _N2B and Q _N3B are arranged. In the layout of FIG. 1, the P-channel MOSFETs Q _P1 , Q _P2 ,
The structure surrounding the drain electrode D of the P-channel type MOSFET Q _P3 by bending a gate electrode G1, G2, G3 of Q _P3, as well as reduce the on-resistance of P-channel type MOSFETQ _P1, Q _P2, P-channel type MOSFET Q
The parasitic capacitance of the drain region D of _P3 is reduced.

FIG. 7 is a plan view showing the layout of the circuit of FIG. 2 according to the conventional method, so that the difference in structure can be understood. Devices and the like in each area of FIGS. 1 and 7 are shown in FIG.
The explanation is omitted because it is clear by making it correspond to the circuit diagram of FIG. Note that, in FIGS. 1 and 7, the region corresponding to the drain region D is shaded. In FIG. 1, the drain region D
Area is reduced by 60% compared to the conventional layout method (FIG. 7). By the layout method of FIG. 1, the parasitic capacitance of the drain region D is reduced to about 1/2, the parasitic capacitance of the node 1 in the circuit diagram of FIG. 2 is reduced to about 1/2, and the no-load delay time is about 20%. It will be faster. The gate width (the length of the strip-shaped gate electrode in the longitudinal direction is called the gate width, and the length in the short direction is called the gate length) is such that the ratio of the gates G3, G2, and G1 is 1: 1.6: 2.2. Becomes Thus, the gate G
By increasing the gate widths of G2 and G1 with respect to 3, the circuit can operate at high speed. The lower part of FIG. 1 shows a device cross-sectional structure taken along line XY in the upper plan layout diagram. The right N-type well region is used as the collector region of the bipolar transistor Q _{0 and} the P-channel type MOSFET Q is used. _P1, is also used as a substrate for Q _P2, Q _P3, P-type well region on the left N-channel type _{MOSFETQ N1A, Q N2A, Q N3A} , Q N1B, Q N2B, Q
_{Used as} a substrate for _N3B . Further, from the collector terminal CN of the bipolar transistor Q ₀ to the P-channel type M
The operating voltage Vcc is supplied to the source region LP of the OSFET Q _P1 by the wiring layer shown by the broken line. Therefore, the second
As shown in the figure, the operating voltage reduced by the parasitic resistance r _CS in the collector region of the bipolar transistor Q ₀ is P
Since the source of the channel type MOSFET Q _P1 is supplied with power, the bipolar transistor Q ₀ is not driven to the saturation region, and the latch-up characteristic is greatly improved.
Further, input side N-channel type MOSFETs Q _N1A , Q _N2A , Q connected to the base of the bipolar transistor Q _0.
Negative supply voltage V _EE1 of _N3A sources, N-channel type MOSFET Q _N1B output side connected to the output OUT is an emitter of the bipolar transistor Q _0, Q _N2B, about the negative supply voltage V _EE sources Q _N3B 0 It is set higher by 0.5V. By supplying this V _EE1 , the potential of the base of the bipolar transistor Q ₀ is maintained higher than that of the emitter, and the delay time without load is shortened by about 20%. Although the NOR circuit has been described above, the NAND circuit can be easily understood to have the same circuit and layout, and a description thereof will be omitted.

FIG. 3 shows a logical configuration suitable for realizing a logical function most efficiently when the NAND and NOR circuits of the present invention are used. As a result of studying the logic circuit built in the integrated circuit, as shown in FIG.
It has become clear that there are many combinations in which the subsequent three-input NOR circuit is connected after the AND circuit. Based on this result, when the NAND circuit in the previous stage drives a light load, specifically, under the condition that the parasitic capacitance of the output signal wiring is light,
The NAND circuit at the front stage is designed with a CMOS circuit configuration so that it operates at high speed when the OR circuit is driven.
The R circuit is designed to drive other logic circuits in the LSI, that is, the NOR circuit in the subsequent stage is designed to operate at high speed when driving a heavy load that is an average load of about 0.2 pF as shown in FIG. 1 and FIG. It is designed with the BiCMOS circuit configuration shown in FIG.
Pre-stage NAND of CMOS circuit structure designed in this way
When a logic circuit including a logic circuit and a NOR logic circuit in the latter stage of the BiCMOS circuit configuration as one set is provided inside the LSI, a gate array that operates at high speed can be achieved.

The operation when the three-input logic circuit is used has been described above. However, some logic in the LSI does not require a 3-input logic circuit. Considering a case where a 3-input logic circuit has only two inputs, it is known that a logic circuit specially designed for 2-input operates at a higher speed. Based on this situation, conventional logic circuits for gate arrays have been designed so that they can be rearranged into 2-input logic or 1-input circuits. According to the present invention, even if the exclusive design is made only for the 3-input logic circuit, the gate widths of the gates G1 and G2 of the MOSFETs receiving the first and second input signals are set to the gate widths of the gate G3 of the MOSFET receiving the third input signal. 1.5 to 2 times, and the first and second
The gate length of the gates G1 and G2 of the MOSFET that receives the input signal of is shortened by about 20% with respect to the gate length of the gate G3 of the first MOSFET to improve the driving capability. They have found that they can have comparable high speed and high load driving capability. In this structure, the gate lengths of the first and second MOSFETs are shortened, so that the effect of reducing the increase in the input capacitance due to the increase in the gate width is also found.

FIG. 4 schematically shows an example of a plan view of an LSI chip to which a logic circuit according to an embodiment of the present invention is applied. In FIG. 4, reference numeral 41 denotes an arrangement area of the input / output buffer circuit, which is composed of a circuit for processing an ECL level signal in an LSI that requires high-speed operation. Reference numeral 42 denotes a circuit area designed exclusively for a memory circuit or the like, and a designer of the gate array can only change the memory capacity and the number of read data. Reference numeral 43 denotes a logic circuit area commonly called a gate array in which the logic circuit of the embodiment of the present invention is arranged.
Designers can incorporate the desired logic functionality. By configuring the LSI in three areas in this way, it is possible to operate at high speed without losing the characteristics of the gate array and to have a high-performance LS.
I can provide.

FIG. 5 schematically shows a cross-sectional view of the P-channel MOSFET after this improvement. The cross-sectional view shown in FIG. 5 corresponds to the cross section taken along the dotted line indicated by AB in FIG. As described above, the gates G1, G2, G3
The gate lengths L1 and L2 of are shorter than L3 by about 20%. The reason why the gate length can be reduced by about 20% will be described below.

FIG. 6 shows a P-channel type MOS shown in FIG.
3 shows a time change of the potential of each part when the FET operates in the logic circuit of FIG. The positive power supply voltage Vcc is 0V
It is said that. At time 0, G1, G2, G indicated by broken lines
When the potential of 3 is set to −3V of the V _EE potential, D, D1, D2
The drain has a potential of 0V, and the source has a potential of 0V. At the time of 1 ns, when the potential of the gate G1 changes from −3 V to −0.5 V, the drain potential is lowered and the potential of D becomes −2.5 V of V _EE1.
The potential of 2 drops only to about -2V. Like this
The fact that the potentials of 1 and D2 become higher than the potential of D is a characteristic of the P-channel MOSFETs Q _P1 , Q _P2 and Q _P3 connected in series. Focusing on this phenomenon, the gate length L of G1 and G2
1 and L2 can be shortened as much as no voltage is applied. Next, when the gate potential returns to -3V again, the drain potential rises. At this time, the potentials of D1, D2, and D are highest in D1, lowest in D, and D2 is located in the middle of both. Because of such a change, even if the same gate potential is applied to the gate, the voltage applied between the source and the gate is
1-S is the largest, and G3-D2 is the smallest. That is, P-channel MOSFEs connected in series
In TQ _P1 , Q _P2 , and Q _P3 , the reduction in driving capability is caused by the reduction in driving capability of MOSFET Q _P3 of gate G3. In order to reduce this decrease in driving ability, the driving ability of the MOSFETs of the gates G1 and G2 is improved in the embodiment of the present invention. The method is as described above for the gate length L1,
L2 is shortened, and as shown in FIG. 1, the gate width of G1 and G2 is widened to improve the driving ability. As a result, D1 in the conventional MOSFETs connected in series,
Compared to the potential change of D2, in the structure of the embodiment of the present invention, D
The potentials of 1 and D2 rise rapidly, and the response speed of the output terminal D is increased accordingly. In the structure shown in FIG. 1, G1 and G
The driving capability of a MOSFET having 2 is a G3 MOSFET
The driving powers of 2.5 and 1.5 times, respectively.

Although the BiCMOS circuit has been described above, it is clear that the combination of the NAND and NOR circuits, the change of the gate width and the change of the gate length can be applied to the CMOS circuit.

[0017]

As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit having a CMOS logic circuit which realizes an essentially high speed.

[Brief description of drawings]

FIG. 1 is a diagram showing a device structure of a semiconductor integrated circuit having a 3-input NOR circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a 3-input BiCMOS logic circuit of the embodiment shown in FIG.

FIG. 3 is a diagram showing a logical configuration in which the 3-input NOR circuit of FIG. 2 is connected to the output of a NAND circuit.

FIG. 4 is a conceptual diagram showing a layout configuration of an LSI chip having the 3-input NOR circuit of FIG.

5 is a diagram showing an element cross-sectional structure on the line AB of the semiconductor integrated circuit according to the embodiment of FIG.

FIG. 6 is a diagram showing a change over time in the potential of each part of the semiconductor integrated circuit according to the embodiment of FIG.

FIG. 7 is a diagram showing how the 3-input BiCMOS logic circuit of FIG. 2 is configured by a conventional layout method.

[Explanation of symbols]

LN ... N-channel MOSFET region, LP ... P-channel MOSFET region, Vcc, V _EE , V _EE1 ... Power supply voltage supply terminal, CN ... Collector connection region, E ... Emitter region, B ... Base region, D ... Drain , S ... Source region, G1, G2, G3 ... Gate electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/08 A 8321-5J 9170-4M H01L 27/06 321 J

Claims (5)

[Claims] 1. A plurality of MOSFETs of the first conductivity type having source / drain paths connected in series between a first operating potential point and a circuit node, and source / drain paths having the circuit node and a second operating potential point. A second conductive type opposite to the first conductive type connected in parallel between
A plurality of conductive type MOSFETs, wherein each of a plurality of input signals is a plurality of M of the first conductive type.
A semiconductor integrated circuit having a logic circuit for generating logic signals of the plurality of input signals at the circuit node by being applied to the gates of the FETs corresponding to the OSFET and the plurality of MOSFETs of the second conductivity type. A plurality of the first conductivity type MOSFEs connected in series,
Of T, M connected close to the first operating potential point
The semiconductor integrated circuit is characterized in that the driving capability of the OSFET is set to be larger than that of the MOSFET connected in proximity to the circuit node. 2. The semiconductor integrated circuit according to claim 1, wherein the driving capability of the MOSFET of the logic circuit is set by at least one of the gate width and the gate length of the MOSFET. 3. The MOSFET of the plurality of MOSFETs of the first conductivity type connected in series in the logic circuit, the MOSFET connected in proximity to the first operating potential point is in proximity to the circuit node. By being arranged around the connected MOSFET, the gate length of the MOSFET connected in proximity to the first operating potential point is larger than the gate length of the MOSFET connected in proximity to the circuit node. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is set. 4. The semiconductor according to claim 1, wherein a base of a bipolar transistor is connected to the circuit node of the logic circuit, and an output signal is obtained from an emitter of the bipolar transistor. Integrated circuit. 5. The second operation type MOSFET further comprising a plurality of second conductivity type MOSFETs having source / drain paths connected in parallel between the emitter of the bipolar transistor and a third operation potential point. The semiconductor integrated circuit according to claim 4, wherein the potential of the potential point is set higher than the potential of the third operating potential point.