JPH06177202A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06177202A JPH06177202A JP43A JP32646392A JPH06177202A JP H06177202 A JPH06177202 A JP H06177202A JP 43 A JP43 A JP 43A JP 32646392 A JP32646392 A JP 32646392A JP H06177202 A JPH06177202 A JP H06177202A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- signal
- insulating tape
- power supply
- lead portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明はＴＡＢ（Ｔａｐｅ Ａ
ｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）を用いたＬＯＣ
（Ｌｅａｄ Ｏｎ Ｃｈｉｐ）構造の半導体装置に関す
るものである。BACKGROUND OF THE INVENTION The present invention relates to TAB (Tape A
LOC using automated bonding)
The present invention relates to a semiconductor device having a (Lead On Chip) structure.
【０００２】[0002]
【従来の技術】図９、１０は従来のこの種の半導体装置
を示し、図９はその平面図、図１０は図９のＸ−Ｘ断面
図であり、これらの図において、１はＩＣチップ等の半
導体チップであり、その外面のほぼ中央部に電源用と接
地用の外部接続用電極１ａ、１ｂの２列と、その両側に
信号用の外部接続用電極１ｃ、１ｄが１列ずつ合計４列
に配列されいる。２は電源用の外部接続用電極１ａの電
極面に形成された電源用突子電極、３は接地用の外部接
続用電極１ｂの電極面に形成された例えば金Ａｕよりな
る接地用突子電極、４、５は信号用の外部接続用電極１
ｃ、１ｄの電極面に形成された例えば金Ａｕよりなる信
号用突子電極、６，７は外部接続用電極１ａ、１ｂ、１
ｃ、１ｄを挟みその両側に配設されたポリイミド等によ
り形成された絶縁テープ基材であり、この絶縁テープ基
材６、７はその長手方向の中央部と両端部において一体
に形成されている。８は絶縁テープ基材６上に銅Ｃｕメ
ッキや接着剤を介して張りつけられた銅Ｃｕ箔をエッチ
ングして形成し、錫めっきを施した電源バスバーリー
ド、９は上記電源バスバーリード８と同様にして絶縁テ
ープ基材７上に形成された接地バスバーリード、１０、
１１は上記電源バスバーリード８と同様にして絶縁テー
プ基材７、８上に形成された信号用リードである。電源
用突子電極２と電源用バスバーリード８、接地用突子電
極３と接地用バスバーリード９および信号用突子電極
４、５と信号用リード１０、１１のインナリード部１０
ａ、１１ａとはＴＡＢ法を用いたインナリードボンディ
ングによって接合される。１２は４２アロイによって形
成されたリードフレームであり、電源用、接地用バスバ
ーリード８、９および信号用リード１０、１１のアウタ
ーリード部１０ｂ、１１ｂと接続される。よって、リー
ドフレーム１２が電源用、接地用バスバーリード８、９
および信号用リード１０、１１のアウターリード部とな
る。そして、リードフレーム１２の端部を残して樹脂部
材１３にて封止することによって半導体チップ１および
上記各リードの接続部等が保護された半導体装置が形成
される。2. Description of the Related Art FIGS. 9 and 10 show a conventional semiconductor device of this type, FIG. 9 is a plan view thereof, and FIG. 10 is a sectional view taken along line X--X of FIG. And the like, and two rows of external connection electrodes 1a and 1b for power supply and grounding, and one row of external connection electrodes 1c and 1d for signals on both sides of the semiconductor chip in the approximate center of the outer surface. They are arranged in 4 columns. Reference numeral 2 is a power supply salient electrode formed on the electrode surface of the power supply external connection electrode 1a, and 3 is a grounding salient electrode made of, for example, gold Au, formed on the electrode surface of the grounding external connection electrode 1b. 4 and 5 are external connection electrodes 1 for signals
Signal protrusion electrodes made of, for example, gold Au formed on the electrode surfaces of c and 1d, 6 and 7 are external connection electrodes 1a, 1b and 1
Insulating tape bases made of polyimide or the like are provided on both sides of c and 1d, and the insulating tape bases 6 and 7 are integrally formed at the longitudinal center and both ends. . Reference numeral 8 denotes a power supply bus bar lead which is formed by etching a copper Cu foil adhered on the insulating tape base material 6 through a copper Cu plating or an adhesive, and is tin-plated, and 9 is the same as the above power supply bus bar lead 8. Ground bus bar lead formed on the insulating tape base material 10,
Reference numeral 11 is a signal lead formed on the insulating tape base materials 7 and 8 in the same manner as the power busbar lead 8. Inner lead portion 10 of power supply salient electrode 2 and power supply busbar lead 8, grounding salient electrode 3 and grounding busbar lead 9, signal salient electrode 4, 5 and signal leads 10 and 11.
The a and 11a are joined by inner lead bonding using the TAB method. Reference numeral 12 denotes a lead frame formed of 42 alloy, which is connected to the power supply and ground bus bar leads 8 and 9 and the outer lead portions 10b and 11b of the signal leads 10 and 11. Therefore, the lead frame 12 is used for the power supply and ground bus bar leads 8, 9
And the outer leads of the signal leads 10 and 11. Then, by sealing the lead frame 12 with the resin member 13 except for the end portions, a semiconductor device in which the semiconductor chip 1 and the connecting portions of the leads are protected is formed.
【０００３】[0003]
【発明が解決しようとする課題】従来の半導体装置は以
上のように、電源用、接地用バスバーリード８、９およ
び信号用リード１０、１１が絶縁テープ基材１０、１１
の一方の面側に形成されているので、半導体チップの外
部接続用電極を電源用、接地用の２列と、その２列の両
側に信号用が１列ずつの合計４列必要となり、外部接続
用電極部の占める面積が大きく、半導体チップのサイズ
が大きくなって、ウエハ１枚当たりの半導体チップ形成
数が少なくなる。さらに半導体チップのサイズが大きく
なると必然的に封止樹脂からなるパッケイジのサイズも
大きくなり実装面積効率が低下するなどの問題点があっ
た。As described above, in the conventional semiconductor device, the power supply and ground bus bar leads 8 and 9 and the signal leads 10 and 11 are the insulating tape base materials 10 and 11.
Since it is formed on one surface side, two columns for external connection electrodes of the semiconductor chip for power supply and ground and one column for signals on both sides of the two columns are required, for a total of four columns. The area occupied by the connecting electrode portion is large, the size of the semiconductor chip is large, and the number of semiconductor chips formed per wafer is small. Further, as the size of the semiconductor chip increases, the size of the package made of the sealing resin inevitably increases, and the mounting area efficiency decreases.
【０００４】この発明は上記のような問題点を解消する
ためになされたもので、半導体チップを小型化し、生産
性および信頼性、実装面積効率の高い半導体装置を得る
ことを目的とする。The present invention has been made in order to solve the above problems, and an object thereof is to obtain a semiconductor device having a small semiconductor chip and high productivity, reliability, and mounting area efficiency.
【０００５】[0005]
【課題を解決するための手段】この発明に係る半導体装
置は半導体チップの外面に信号用、電源用および接地用
の外部接続用電極を混在させて配列すると共に、その外
部接続用電極を挟みその両側に配設された第１と第２の
絶縁テープ基材の第１の絶縁テープ基材の表裏面の一方
の面に信号用リードを、他方の面に電源バスバーリード
を形成し、第２の絶縁テープ基材の表裏面の一方の面に
信号用リードを他方の面に接地バスバーリードを形成し
たものである。In a semiconductor device according to the present invention, external connection electrodes for signal, power supply and ground are mixedly arranged on the outer surface of a semiconductor chip, and the external connection electrodes are sandwiched between them. A signal lead is formed on one of the front and back surfaces of the first insulating tape base material of the first and second insulating tape base materials arranged on both sides, and a power supply bus bar lead is formed on the other surface of the first insulating tape base material. The signal lead is formed on one of the front and back surfaces of the insulating tape base material, and the ground bus bar lead is formed on the other surface.
【０００６】[0006]
【作用】この発明における半導体装置は電源用バスバー
リードおよび接地用バスバーリードと信号用リードの構
成が立体的となり、半導体チップの信号用の外部接続用
電極の配列中に電源用および接地用の外部接続用電極が
混在していても上記各リードと接続することができる。In the semiconductor device according to the present invention, the busbar lead for power supply, the busbar lead for grounding, and the signal lead have a three-dimensional structure. Even if the connecting electrodes are mixed, the leads can be connected to each of the above leads.
【０００７】[0007]
【実施例】実施例１．図１、図２はこの発明の一実施例
による半導体装置を示し、図１はその内部平面図、図２
はその断面図であり、これらの図において、１４はＩＣ
チップ等の半導体チップであり、その外面のほぼ中央部
に電源用と接地用および信号用の外部接続用電極（図示
せず）を混在させ１列に配列されている。１５は半導体
チップの内部回路を保護するためその外面に形成され
た、例えばポリイミド系樹脂よりなるバッファコート、
２は上記電源用の外部接続用電極面にスパッタ法、写真
製版技術、メッキ技術などを用いて形成された例えば金
Ａｕよりなる電源用突子電極、３は上記接地用の外部接
続用電極面に上記電源用突子電極２と同様にして形成さ
れた例えば金Ａｕよりなる接地用突子電極、４は上記接
地用の外部接続用電極面に上記電源用突子電極２と同様
にして形成された例えば金Ａｕよりなる信号用突子電
極、１６、１７は半導体チップ１４の外面に１列に配列
された外部接続用電極（図示せず）の両側に配設されポ
リイミド等によって形成された絶縁テープ基材であり、
この絶縁テープ基材１６、１７はその長手方向の両端部
において一体に形成されている。EXAMPLES Example 1. 1 and 2 show a semiconductor device according to an embodiment of the present invention. FIG.
Is a cross-sectional view thereof, and in these drawings, 14 is an IC
This is a semiconductor chip such as a chip, and external connection electrodes (not shown) for power supply, grounding, and signals are mixedly arranged in a central portion of the outer surface of the semiconductor chip. Reference numeral 15 denotes a buffer coat made of, for example, a polyimide resin formed on the outer surface of the semiconductor chip to protect the internal circuit of the semiconductor chip.
Reference numeral 2 is a power supply projection electrode made of, for example, gold Au, which is formed on the external connection electrode surface for the power supply by using a sputtering method, a photoengraving technique, a plating technology, or the like, and 3 is an external connection electrode surface for the grounding. Are formed in the same manner as the power supply pole electrode 2 and grounding pole electrodes 4 made of, for example, gold Au are formed on the grounding external connection electrode surface in the same manner as the power supply pole electrode 2. The signal protrusion electrodes 16 and 17 made of, for example, gold Au are disposed on both sides of external connection electrodes (not shown) arranged in a line on the outer surface of the semiconductor chip 14, and are made of polyimide or the like. Insulating tape base material,
The insulating tape substrates 16 and 17 are integrally formed at both ends in the longitudinal direction.
【０００８】１８は電源バスバーリードであり、絶縁テ
ープ基材１６の裏面に銅Ｃｕメッキや接着剤を介して張
り付けられた銅Ｃｕ箔等を写真製版技術等を用いて上記
裏面のほぼ全面に形成され一端部に複数個の電源用突子
電極２と接合される複数個の接続子１９ａを有するイン
ナリード部１９と、上記インナリード部１９と同様にし
て写真製版技術等を用い絶縁テープ基材１６の表面に形
成され絶縁テープ基材１６に設けられたスルーホール１
６ａによって上記インナリード部１９と電気的に接続さ
れたアウタリード部２０とによって構成されている。２
１は接地用リードであり、絶縁テープ基材１７の裏面の
ほぼ全面に上記インナリード部１９と同様に形成され、
一端部に複数個の接地用突子電極３と接合される複数個
の接続子２２ａを有するインナリード部２２と、上記イ
ンナリード部１９と同様にして絶縁テープ基材１６の表
面に形成され絶縁テープ基材１６に設けられたスルーホ
ール１６ａによって上記インナリード部１９と電気的に
接続されたアウタリード部２０とによって構成されてい
る。２４、２５は絶縁テープ基材１６、１７の表面に銅
Ｃｕメッキや接着剤を介して張り付けられた銅Ｃｕ箔等
を写真製版技術等を用いて形成され信号用突子電極４に
接続されるインナリード部２４ａ、２５ａと、リードフ
レーム１２に接続されるアウタリード部２４ａ、２５ａ
とにより構成された信号用リードである。Reference numeral 18 denotes a power supply bus bar lead, and a copper Cu foil or the like adhered to the back surface of the insulating tape base material 16 via copper Cu plating or an adhesive is formed on almost the entire back surface by photolithography or the like. An inner lead portion 19 having a plurality of connectors 19a joined to a plurality of power source protrusion electrodes 2 at one end, and an insulating tape base material similar to the inner lead portion 19 using photoengraving technology or the like. Through hole 1 formed on the surface of 16 and provided on insulating tape substrate 16
The outer lead portion 20 is electrically connected to the inner lead portion 6 by 6a. Two
Reference numeral 1 is a grounding lead, which is formed on almost the entire back surface of the insulating tape base material 17 in the same manner as the inner lead portion 19,
An inner lead portion 22 having a plurality of connectors 22a joined to a plurality of grounding protrusion electrodes 3 at one end, and an insulating tape base 16 formed in the same manner as the inner lead portion 19 and insulated. It is composed of the inner lead portion 19 and the outer lead portion 20 electrically connected to the inner lead portion 19 by a through hole 16 a provided in the tape base material 16. Numerals 24 and 25 are copper Cu foils or the like adhered to the surfaces of the insulating tape base materials 16 and 17 via copper Cu plating or an adhesive using a photoengraving technique or the like, and are connected to the signal protrusion electrodes 4. Inner lead portions 24a and 25a and outer lead portions 24a and 25a connected to the lead frame 12.
It is a signal lead constituted by and.
【０００９】信号用リード２４、２５のインナリード部
２４ａ、２５ａと信号用突子電極４との接続、電源バス
バーリード２１のインナリード部１９の接続子１９ａと
電源用突子電極２および接地バスバーリード２１のイン
ナリード部２２の接続子２２ａと接地用突子電極３との
接合は加熱圧着法等によって接合される。次いで、電
源、接地バスバーリード１８、２１のアウタリード部２
０、２３および信号用リード２４、２５のアウタリード
部２４ｂ、２５ｂとリードフレーム１２とが加熱圧着法
等によって接合される。そして、半導体チップ１４と各
リード１８、２１、２４、２５および各リード１８、２
１、２４、２５とリードフレーム１２との接合部がトラ
ンスファモールド法などにより樹脂部材１３にて封止さ
れ、封止樹脂により外界から保護された半導体装置が形
成される。The connection between the inner lead portions 24a, 25a of the signal leads 24, 25 and the signal projection electrode 4, the connection 19a of the inner lead portion 19 of the power supply bus bar lead 21, the power supply projection electrode 2, and the ground bus bar. The connector 22a of the inner lead portion 22 of the lead 21 and the grounding pole electrode 3 are joined by a thermocompression bonding method or the like. Next, the outer lead portion 2 of the power supply / ground bus bar lead 18, 21
The outer lead portions 24b and 25b of the lead wires 0 and 23 and the signal leads 24 and 25 are joined to the lead frame 12 by a thermocompression bonding method or the like. The semiconductor chip 14 and the leads 18, 21, 24, 25 and the leads 18, 2
The joints between the lead frames 12, 24 and 25 and the lead frame 12 are sealed with a resin member 13 by a transfer molding method or the like, and a semiconductor device protected from the outside by the sealing resin is formed.
【００１０】上記のように構成された半導体装置におい
ては、以上のように半導体チップ１４の外面に信号用、
電源用および接地用の外部接続用電極を混在させて１列
に配列することができ、これによって、半導体チップ１
４のサイズに約１０％の縮小が可能となり、半導体チッ
プの小型化によってウエハ１枚当たりの半導体チップの
形成個数が多くなり生産性が向上し、かつ、封止樹脂か
らなるパッケージのサイズに占める半導体チップの割合
が小さくなって、外界からの湿気等による影響が小さく
なり信頼性の高い小型の半導体装置が得られる。さら
に、電源バスバーリード１８および接地バスバーリード
２１が絶縁テープ基材１６、１７の一方の面のほぼ全面
に形成されているので、上記外部接続用電極の配列中に
多数の電源用、接地用の外部接続用電極を設けても、そ
のアウタリード部の数が少数で済み、かつ、半導体チッ
プ上のどの位置でも同電位が得られ電気的安定が保たれ
る。In the semiconductor device configured as described above, as described above, for the signal on the outer surface of the semiconductor chip 14,
External connection electrodes for power supply and ground can be mixed and arranged in one row, whereby the semiconductor chip 1
4 can be reduced by about 10%, the number of semiconductor chips formed per wafer is increased due to the miniaturization of semiconductor chips, and the productivity is improved, and the size of the package made of sealing resin is occupied. The proportion of semiconductor chips is reduced, the influence of moisture from the outside is reduced, and a highly reliable small semiconductor device can be obtained. Further, since the power supply bus bar lead 18 and the ground bus bar lead 21 are formed on almost the entire one surface of the insulating tape base materials 16 and 17, a large number of power supply and ground electrodes are arranged in the array of the external connection electrodes. Even if the external connection electrode is provided, the number of outer lead portions is small, and the same potential can be obtained at any position on the semiconductor chip to maintain electrical stability.
【００１１】実施例２．上記実施例では絶縁テープ基材
１６、１７にスルーホール１６ａ、１７ａを設けて電気
的導通をとり、各リード１８、２１、２４、２５のアウ
タリード部２０、２３、２４ｂ、２５ｂを絶縁テープ基
材１６、１７の一方の面からのみ突出させ、リードフレ
ーム１２と接合しているが、図３に示されるように、絶
縁テープ基材１６、１７にスルーホール１６ａ、１７ａ
を設けず絶縁テープ基材１６の一方の面に信号用リード
２４を、他方の面に電源バスバーリード１８を設けると
共に絶縁テープ基材１７の一方の面に信号用リード２５
を、他方の面に接地バスバーリード２１を設け、絶縁テ
ープ基材１６、１７の両面から各リード１８、２１、２
４、２５のアウタリード部２０、２３、２４ｂ、２５ｂ
を突出させリードフレーム１２表裏両面に係合させ、加
熱圧着法などによりその両面に接合しても良く、上記実
施例と同様の効果を奏する。Embodiment 2. In the above embodiment, the insulating tape bases 16, 17 are provided with through holes 16a, 17a for electrical conduction, and the outer lead portions 20, 23, 24b, 25b of the leads 18, 21, 24, 25 are connected to the insulating tape bases. Although it is made to project from only one surface of 16 and 17 and joined to the lead frame 12, through holes 16a and 17a are formed in the insulating tape base materials 16 and 17 as shown in FIG.
The signal lead 24 is provided on one surface of the insulating tape base material 16 and the power supply bus bar lead 18 is provided on the other surface of the insulating tape base material 16, and the signal lead 25 is provided on one surface of the insulating tape base material 17.
The ground busbar lead 21 is provided on the other surface, and the leads 18, 21, 2 are formed on both sides of the insulating tape base materials 16, 17, respectively.
4, 25 outer lead portions 20, 23, 24b, 25b
May be projected and engaged with both the front and back surfaces of the lead frame 12 and joined to both surfaces by a thermocompression bonding method or the like, and the same effect as the above-mentioned embodiment is obtained.
【００１２】実施例３．図４はこの発明の実施例３によ
る半導体装置を示す断面図であり、図２と異なるところ
は、リードフレーム１２の厚みを絶縁テープ基材１６、
１７の厚みよりも厚くし、エッチング技術等によりアウ
トリード部２４ｂ、２０、２３、２５ｂとの接合部は薄
くなるようにエッチングしその両面にアウトリード部２
４ｂ、２０、２３、２５ｂを接合し、封止樹脂１３の外
部に露出する部分を厚くし機械的強度を大きくした点で
あり、上記実施例と同様の効果を奏する。Embodiment 3. 4 is a sectional view showing a semiconductor device according to a third embodiment of the present invention. The difference from FIG. 2 is that the thickness of the lead frame 12 is the insulating tape base material 16,
It is made thicker than 17 and is etched by an etching technique or the like so that the joints with the outlead portions 24b, 20, 23, 25b are thinned, and the outlead portions 2 are formed on both sides thereof.
4b, 20, 23, and 25b are joined, and the portion exposed to the outside of the sealing resin 13 is made thicker to increase the mechanical strength, and the same effect as the above-mentioned embodiment is obtained.
【００１３】実施例４．図５はこの発明の実施例４によ
る半導体装置を示す断面図であり、図２と異なるところ
は、電源バスバーリード１８のアウタリード部２０およ
び接地バスバーリード２１のアウタリード部２３を信号
用リード２４、２５のアウタリード部２４ｂ、２５ｂの
形成面側に折り曲げリードフレーム１２の一方の面に接
合した点であり、上記実施例と同様の効果を奏する。Embodiment 4. 5 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention. The difference from FIG. 2 is that the outer lead portion 20 of the power supply bus bar lead 18 and the outer lead portion 23 of the ground bus bar lead 21 are connected to the signal leads 24, 25. The outer lead portions 24b and 25b are bent and joined to one surface of the lead frame 12, and the same effect as that of the above embodiment is obtained.
【００１４】実施例５．図６はこの発明の実施例５によ
る半導体装置を示す断面図であり、図２と異なるところ
は、信号用リード２４、２５のアウタリード部２４ｂ、
２５ｂをリードフレーム１２に接続せず、アウタリード
部２４ｂ、２５ｂを封止樹脂１３から突出させると共に
その突出部の厚みを厚くし機械的強度を大きくした点で
あり、上記実施例と同様の効果を奏する。Example 5. 6 is a sectional view showing a semiconductor device according to Embodiment 5 of the present invention. The difference from FIG. 2 is that the outer leads 24b of the signal leads 24, 25 are
25b is not connected to the lead frame 12, the outer lead portions 24b, 25b are projected from the sealing resin 13, and the thickness of the protruding portions is increased to increase the mechanical strength. Play.
【００１５】実施例６．図７、図８はこの発明の実施例
６による半導体装置を示し、図７はその内部平面図、図
８は断面図であり、図１、図２と異なるところは、半導
体チップ１の外面に外部接続用電極を２列に配列し、電
源バスバーリード１９側の１列に信号用と電源用の外部
接続用電極を混在させて配列し、その外部接続用電極上
に電源用および信号用突子電極２、４を形成すると共
に、接地バスバーリード２１側の１列に信号用と接地用
の外部接続用電極を混在させて配列し、その外部接続用
電極上に電源用および信号用突子電極３、４を形成した
点であり、上記実施例と同様の効果を奏する。Embodiment 6. 7 and 8 show a semiconductor device according to a sixth embodiment of the present invention, FIG. 7 is an internal plan view thereof, and FIG. 8 is a sectional view thereof. The difference from FIG. 1 and FIG. The electrodes for external connection are arranged in two rows, and the electrodes for external connection for signal and power are mixedly arranged in one row on the side of the power supply bus bar lead 19, and the electrodes for power supply and signal are arranged on the electrodes for external connection. The child electrodes 2 and 4 are formed, and the external connection electrodes for signal and ground are mixed and arranged in one row on the ground bus bar lead 21 side, and the power supply and signal projections are arranged on the external connection electrodes. This is a point that the electrodes 3 and 4 are formed, and the same effect as that of the above-described embodiment is obtained.
【００１６】[0016]
【発明の効果】以上のように、この発明によれば、信号
用、電源用および接地用の外部接続用電極を混在させて
配列した半導体チップの外部接続用電極に、電源用、接
地用、信号用の各リードが接続できるように構成したの
で、上記外部接続用電極の配列数が少なくなり半導体チ
ップのサイズが縮小され、ウエハ１枚当たりの半導体チ
ップの形成個数が多くなり生産性が向上し、かつ、上記
半導体チップを封止する封止樹脂からなるパッケージサ
イズに占める半導体チップの占める割合が小さくなって
外界からの湿気などによる影響が小さくなり信頼性が向
上する。As described above, according to the present invention, the external connection electrodes of the semiconductor chip in which the external connection electrodes for signal, power supply and ground are mixed and arranged, Since the leads for signals can be connected, the number of the electrodes for external connection is reduced, the size of the semiconductor chip is reduced, the number of semiconductor chips formed per wafer is increased, and the productivity is improved. In addition, the ratio of the semiconductor chip to the package size of the encapsulating resin for encapsulating the semiconductor chip is reduced, the influence of moisture from the outside is reduced, and the reliability is improved.
【図１】この発明の一実施例による半導体装置を示す内
部平面図である。FIG. 1 is an internal plan view showing a semiconductor device according to an embodiment of the present invention.
【図２】図１に示される半導体装置の断面図である。FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG.
【図３】この発明の実施例２による半導体装置の断面図
である。FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
【図４】この発明の実施例３による半導体装置の断面図
である。FIG. 4 is a sectional view of a semiconductor device according to a third embodiment of the present invention.
【図５】この発明の実施例４による半導体装置の断面図
である。FIG. 5 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.
【図６】この発明の実施例５による半導体装置の断面図
である。FIG. 6 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.
【図７】この発明の実施例６による半導体装置を示す内
部平面図である。FIG. 7 is an internal plan view showing a semiconductor device according to Embodiment 6 of the present invention.
【図８】図７に示される半導体装置の断面図である。8 is a cross-sectional view of the semiconductor device shown in FIG.
【図９】従来の半導体装置を示す内部平面図である。FIG. 9 is an internal plan view showing a conventional semiconductor device.
【図１０】図９のＸ−Ｘ断面図である。10 is a sectional view taken along line XX of FIG.
１ 半導体チップ ２ 電源用突子電源 ３ 接地用突子電極 ４ 信号用突子電極 １３ 封止樹脂 １６ 絶縁テープ基材 １７ 絶縁テープ基材 １８ 電源バスバーリード １９ インナリード部 ２０ アウタリード部 ２１ 接地バスバーリード ２２ インナリード部 ２３ アウタリード部 DESCRIPTION OF SYMBOLS 1 semiconductor chip 2 power supply for power supply 3 grounding electrode 4 for signal electrode 13 sealing resin 16 insulating tape base material 17 insulating tape base material 18 power supply bus bar lead 19 inner lead part 20 outer lead part 21 ground bus bar lead 22 Inner lead part 23 Outer lead part
【手続補正書】[Procedure amendment]
【提出日】平成６年３月３日[Submission date] March 3, 1994
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】請求項１[Name of item to be corrected] Claim 1
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】請求項３[Name of item to be corrected] Claim 3
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【手続補正３】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００２[Name of item to be corrected] 0002
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００２】[0002]
【従来の技術】図９、１０は従来のこの種の半導体装置
を示し、図９はその平面図、図１０は図９のＸ−Ｘ断面
図であり、これらの図において、１はＩＣチップ等の半
導体チップであり、その外面のほぼ中央部に電源用と接
地用の外部接続用電極１ａ、１ｂの２列と、その両側に
信号用の外部接続用電極１ｃ、１ｄが１列ずつ合計４列
に配列されいる。２は電源用の外部接続用電極１ａの電
極面に形成された電源用突起電極、３は接地用の外部接
続用電極１ｂの電極面に形成された例えば金（Ａｕ）よ
りなる接地用突起電極、４、５は信号用の外部接続用電
極１ｃ、１ｄの電極面に形成された例えば金（Ａｕ）よ
りなる信号用突起電極、６，７は外部接続用電極１ａ、
１ｂ、１ｃ、１ｄを挟みその両側に配設されたポリイミ
ド等により形成された絶縁テープ基材であり、この絶縁
テープ基材６、７はその長手方向の中央部と両端部にお
いて一体に形成されている。８は絶縁テープ基材６上に
銅（Ｃｕ）メッキや接着剤を介して張りつけられた銅
（Ｃｕ）箔をエッチングして形成し、錫めっきを施した
電源バスバーリード、９は上記電源バスバーリード８と
同様にして絶縁テープ基材７上に形成された接地バスバ
ーリード、１０、１１は上記電源バスバーリード８と同
様にして絶縁テープ基材６、７上に形成された信号用リ
ードである。電源用突起電極２と電源用バスバーリード
８、接地用突起電極３と接地用バスバーリード９および
信号用突起電極４、５と信号用リード１０、１１のイン
ナリード部１０ａ、１１ａとはＴＡＢ法を用いたインナ
リードボンディングによって接合される。１２は４２ア
ロイによって形成されたリードフレームであり、電源
用、接地用バスバーリード８、９および信号用リード１
０、１１のアウターリード部１０ｂ、１１ｂと接続され
る。よって、リードフレーム１２が電源用、接地用バス
バーリード８、９および信号用リード１０、１１のアウ
ターリード部となる。そして、リードフレーム１２の端
部を残して樹脂部材１３にて封止することによって半導
体チップ１および上記各リードの接続部等が保護された
半導体装置が形成される。2. Description of the Related Art FIGS. 9 and 10 show a conventional semiconductor device of this type, FIG. 9 is a plan view thereof, and FIG. 10 is a sectional view taken along line X--X of FIG. And the like, and two rows of external connection electrodes 1a and 1b for power supply and grounding, and one row of external connection electrodes 1c and 1d for signals on both sides of the semiconductor chip in the approximate center of the outer surface. They are arranged in 4 columns. 2 the external connection electrodes 1a collision force electrode power supply that is formed on the electrode surface of the power supply, 3 ground collision made of, for example, gold is formed on the electrode surface of the external connection electrodes 1b for grounding (Au) electromotive electrodes, 4 and 5 for external connection electrode 1c, signal collision caused electrode made of the electrode surface formed for example of gold 1d (Au) of the signal, 6 and 7 the external connection electrodes 1a,
1b, 1c, 1d is an insulating tape base material formed of polyimide or the like disposed on both sides of the insulating tape base material 6 and 7. The insulating tape base materials 6 and 7 are integrally formed at the longitudinal center and both ends thereof. ing. Reference numeral 8 denotes copper adhered to the insulating tape base material 6 via copper (Cu) plating or an adhesive.
A power supply bus bar lead formed by etching a (Cu) foil and plated with tin, 9 is a ground bus bar lead formed on an insulating tape base material 7 in the same manner as the power supply bus bar lead 8, and 10 and 11 are the above. This is a signal lead formed on the insulating tape base materials 6 and 7 in the same manner as the power supply bus bar lead 8. Power for collision force electrode 2 and the power supply bus bar leads 8, the inner lead portion 10a of the ground collision force electrode 3 and the ground bus bar lead 9 and the signal collision caused electrode 4,5 and the signal leads 10, 11, 11a and the It is joined by inner lead bonding using the TAB method. Reference numeral 12 is a lead frame formed of 42 alloy, which includes bus bar leads 8 and 9 for power supply and ground and lead 1 for signal.
It is connected to the outer lead portions 10b and 11b of 0 and 11. Therefore, the lead frame 12 serves as outer lead portions of the power supply and ground bus bar leads 8 and 9 and the signal leads 10 and 11. Then, by sealing the lead frame 12 with the resin member 13 except for the end portions, a semiconductor device in which the semiconductor chip 1 and the connecting portions of the leads are protected is formed.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００３[Name of item to be corrected] 0003
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００３】[0003]
【発明が解決しようとする課題】従来の半導体装置は以
上のように、電源用、接地用バスバーリード８、９およ
び信号用リード１０、１１が絶縁テープ基材６、７の一
方の面側に形成されているので、半導体チップの外部接
続用電極を電源用、接地用の２列と、その２列の両側に
信号用が１列ずつの合計４列必要となり、外部接続用電
極部の占める面積が大きく、半導体チップのサイズが大
きくなって、ウエハ１枚当たりの半導体チップ形成数が
少なくなる。さらに半導体チップのサイズが大きくなる
と必然的に封止樹脂からなるパッケージのサイズも大き
くなり実装面積効率が低下するなどの問題点があった。As described above, in the conventional semiconductor device, the power supply and ground bus bar leads 8 and 9 and the signal leads 10 and 11 are provided on one surface side of the insulating tape substrates 6 and 7. Since the external connection electrodes of the semiconductor chip are formed, two columns for power supply and ground, and one column for signals on both sides of the two columns are required for a total of four columns, which is occupied by the external connection electrode portion. The area is large, the size of the semiconductor chip is large, and the number of semiconductor chips formed per wafer is small. Inevitably size package consisting of the sealing resin becomes large mounting area efficiency has a problem such as decrease further increases the size of the semiconductor chip.
【手続補正５】[Procedure Amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００７[Correction target item name] 0007
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００７】[0007]
【実施例】実施例１．図１、図２はこの発明の一実施例
による半導体装置を示し、図１はその内部平面図、図２
はその断面図であり、これらの図において、１４はＩＣ
チップ等の半導体チップであり、その外面のほぼ中央部
に電源用と接地用および信号用の外部接続用電極（図示
せず）を混在させ１列に配列されている。１５は半導体
チップの内部回路を保護するためその外面に形成され
た、例えばポリイミド系樹脂よりなるバッファコート、
２は上記電源用の外部接続用電極面にスパッタ法、写真
製版技術、メッキ技術などを用いて形成された例えば金
（Ａｕ）よりなる電源用突起電極、３は上記接地用の外
部接続用電極面に上記電源用突起電極２と同様にして形
成された例えば金（Ａｕ）よりなる接地用突起電極、４
は上記接地用の外部接続用電極面に上記電源用突起電極
２と同様にして形成された例えば金（Ａｕ）よりなる信
号用突起電極、１６、１７は半導体チップ１４の外面に
１列に配列された外部接続用電極（図示せず）の両側に
配設されポリイミド等によって形成された絶縁テープ基
材であり、この絶縁テープ基材１６、１７はその長手方
向の両端部において一体に形成されている。EXAMPLES Example 1. 1 and 2 show a semiconductor device according to an embodiment of the present invention. FIG.
Is a cross-sectional view thereof, and in these drawings, 14 is an IC
This is a semiconductor chip such as a chip, and external connection electrodes (not shown) for power supply, grounding, and signals are mixedly arranged in a central portion of the outer surface of the semiconductor chip. Reference numeral 15 denotes a buffer coat made of, for example, a polyimide resin formed on the outer surface of the semiconductor chip to protect the internal circuit of the semiconductor chip.
2 is, for example, gold formed on the surface of the external connection electrode for the power source by using a sputtering method, a photoengraving technique, a plating technique, or the like.
(Au) power for collision force electrode made of, 3 ground collision force electrodes to the external connection electrode surface made of the power supply collision force electrode 2 for instance is formed in the same manner as gold (Au) for the ground, Four
One column of electrodes for external connection surface is formed in the same manner as the power for collision force electrode 2 were, for example, gold (Au) signal collision caused electrode made for the ground, 16 and 17 on the outer surface of the semiconductor chip 14 Is an insulating tape base material formed of polyimide or the like disposed on both sides of an external connection electrode (not shown) arranged in a row. The insulating tape base materials 16 and 17 are integrally formed at both longitudinal end portions thereof. Has been formed.
【手続補正６】[Procedure correction 6]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００８[Correction target item name] 0008
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００８】１８は電源バスバーリードであり、絶縁テ
ープ基材１６の裏面に銅（Ｃｕ）メッキや接着剤を介し
て張り付けられた銅（Ｃｕ）箔等を写真製版技術等を用
いて上記裏面のほぼ全面に形成され一端部に複数個の電
源用突起電極２と接合される複数個の接続子１９ａを有
するインナリード部１９と、上記インナリード部１９と
同様にして写真製版技術等を用い絶縁テープ基材１６の
表面に形成され絶縁テープ基材１６に設けられたスルー
ホール１６ａによって上記インナリード部１９と電気的
に接続されたアウタリード部２０とによって構成されて
いる。２１は接地用リードであり、絶縁テープ基材１７
の裏面のほぼ全面に上記インナリード部１９と同様に形
成され、一端部に複数個の接地用突起電極３と接合され
る複数個の接続子２２ａを有するインナリード部２２
と、上記インナリード部２２と同様にして絶縁テープ基
材１７の表面に形成され絶縁テープ基材１７に設けられ
たスルーホール１７ａによって上記インナリード部２２
と電気的に接続されたアウタリード部２３とによって構
成されている。２４、２５は絶縁テープ基材１６、１７
の表面に銅（Ｃｕ）メッキや接着剤を介して張り付けら
れた銅（Ｃｕ）箔等を写真製版技術等を用いて形成され
信号用突起電極４に接続されるインナリード部２４ａ、
２５ａと、リードフレーム１２に接続されるアウタリー
ド部２４ｂ、２５ｂとにより構成された信号用リードで
ある。Reference numeral 18 denotes a power supply bus bar lead, which is a copper (Cu) foil adhered to the back surface of the insulating tape base material 16 via copper (Cu) plating or an adhesive by using a photoengraving technique or the like. an inner lead portion 19 having a plurality of connectors 19a that are substantially joined to one end portion is formed on the entire surface a plurality of power supply for collision force electrode 2, by photolithography or the like in the same manner as the inner lead portions 19 The insulating tape base material 16 is composed of an inner lead portion 19 and an outer lead portion 20 electrically connected to the inner lead portion 19 by a through hole 16a formed in the surface of the insulating tape base material 16. 21 is a grounding lead, which is an insulating tape base material 17
Substantially the entire surface is formed similarly to the inner lead portion 19 of the rear surface, the inner lead portion 22 having a plurality of connectors 22a to be joined with the plurality of ground collision force electrode 3 on one end
If, the inner lead portion 22 above the through hole 17a formed in the insulating formed on the surface of the tape base 17 insulating tape base material 17 in the same manner as the inner lead portions 22
And the outer lead portion 23 electrically connected to the outer lead portion 23 . 24 and 25 are insulating tape substrates 16 and 17
Surface copper (Cu) plated and affixed via an adhesive a copper (Cu) inner lead portion 24a is connected to the foil or the like are formed by photolithography or the like to the signal collision caused electrode 4,
25a and outer leads 24b and 25b connected to the lead frame 12 are signal leads.
【手続補正７】[Procedure Amendment 7]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００９[Correction target item name] 0009
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００９】信号用リード２４、２５のインナリード部
２４ａ、２５ａと信号用突起電極４との接続、電源バス
バーリード２１のインナリード部１９の接続子１９ａと
電源用突起電極２および接地バスバーリード２１のイン
ナリード部２２の接続子２２ａと接地用突起電極３との
接合は加熱圧着法等によって接合される。次いで、電
源、接地バスバーリード１８、２１のアウタリード部２
０、２３および信号用リード２４、２５のアウタリード
部２４ｂ、２５ｂとリードフレーム１２とが加熱圧着法
等によって接合される。そして、半導体チップ１４と各
リード１８、２１、２４、２５および各リード１８、２
１、２４、２５とリードフレーム１２との接合部がトラ
ンスファモールド法などにより樹脂部材１３にて封止さ
れ、封止樹脂により外界から保護された半導体装置が形
成される。[0009] the inner lead portion 24a of the signal leads 24, 25, 25a and connected to the signal collision caused electrode 4, connectors 19a and power supply collision force electrode 2 and the ground bus bar of the inner lead portion 19 of the power bus bar lead 21 bonding between connectors 22a of the inner lead portion 22 of the lead 21 and the ground collision force electrode 3 are joined by thermocompression bonding method or the like. Next, the outer lead portion 2 of the power supply / ground bus bar lead 18, 21
The outer lead portions 24b and 25b of the lead wires 0 and 23 and the signal leads 24 and 25 are joined to the lead frame 12 by a thermocompression bonding method or the like. The semiconductor chip 14 and the leads 18, 21, 24, 25 and the leads 18, 2
The joints between the lead frames 12, 24 and 25 and the lead frame 12 are sealed with a resin member 13 by a transfer molding method or the like, and a semiconductor device protected from the outside by the sealing resin is formed.
【手続補正８】[Procedure Amendment 8]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１２[Correction target item name] 0012
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１２】実施例３．図４はこの発明の実施例３によ
る半導体装置を示す断面図であり、図２と異なるところ
は、リードフレーム１２の厚みを絶縁テープ基材１６、
１７の厚みよりも厚くし、エッチング技術等によりアウ
タリード部２４ｂ、２０、２３、２５ｂとの接合部は薄
くなるようにエッチングしその両面にアウタリード部２
４ｂ、２０、２３、２５ｂを接合し、封止樹脂１３の外
部に露出する部分を厚くし機械的強度を大きくした点で
あり、上記実施例と同様の効果を奏する。Embodiment 3. 4 is a sectional view showing a semiconductor device according to a third embodiment of the present invention. The difference from FIG. 2 is that the thickness of the lead frame 12 is the insulating tape base material 16,
It should be thicker than 17 and made
Data read section 24b, the junction of the 20,23,25b is etched to be thinner Au data read section 2 on both sides thereof
4b, 20, 23, and 25b are joined together, and the portion exposed to the outside of the sealing resin 13 is made thicker to increase the mechanical strength, and the same effect as the above-mentioned embodiment is obtained.
【手続補正９】[Procedure Amendment 9]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１５[Name of item to be corrected] 0015
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１５】実施例６．図７、図８はこの発明の実施例
６による半導体装置を示し、図７はその内部平面図、図
８は断面図であり、図１、図２と異なるところは、半導
体チップ１の外面に外部接続用電極を２列に配列し、電
源バスバーリード１９側の１列に信号用と電源用の外部
接続用電極を混在させて配列し、その外部接続用電極上
に電源用および信号用突起電極２、４を形成すると共
に、接地バスバーリード２１側の１列に信号用と接地用
の外部接続用電極を混在させて配列し、その外部接続用
電極上に電源用および信号用突起電極３、４を形成した
点であり、上記実施例と同様の効果を奏する。Embodiment 6. 7 and 8 show a semiconductor device according to a sixth embodiment of the present invention, FIG. 7 is an internal plan view thereof, and FIG. 8 is a sectional view thereof. The difference from FIG. 1 and FIG. The electrodes for external connection are arranged in two rows, and the electrodes for external connection for signal and power are mixedly arranged in one row on the side of the power supply bus bar lead 19, and the electrodes for power supply and signal are arranged on the electrodes for external connection. and forming a raised electrode 2,4, a ground bus bar lead 21 side of a mix of external connection electrodes for grounding is arranged with a signal in a line, power supply and signal collision caused to the external connection on the electrode This is a point that the electrodes 3 and 4 are formed, and the same effect as that of the above-described embodiment is obtained.
【手続補正１０】[Procedure Amendment 10]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】符号の説明[Correction target item name] Explanation of code
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【符号の説明】 １ 半導体チップ ２ 電源用突起電源 ３ 接地用突起電極 ４ 信号用突起電極 １３ 封止樹脂 １６ 絶縁テープ基材 １７ 絶縁テープ基材 １８ 電源バスバーリード １９ インナリード部 ２０ アウタリード部 ２１ 接地バスバーリード ２２ インナリード部 ２３ アウタリード部[EXPLANATION OF SYMBOLS] 1 semiconductor chip 2 power for collision force supply 3 butt for ground collision force electrode 4 signal force electrodes 13 sealing resin 16 insulating tape base material 17 insulating tape base material 18 power bus bar leads 19 the inner lead portion 20 outer leads Part 21 Ground busbar lead 22 Inner lead part 23 Outer lead part
【手続補正１１】[Procedure Amendment 11]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図１[Name of item to be corrected] Figure 1
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図１】 [Figure 1]
Claims (3)
用電極が外面に混在して配列された半導体チップと、上
記外部接続用電極面上に形成された信号用、電源用およ
び接地用突子電極と、上記外部接続用電極を挟みその両
側に配設された第１と第２の絶縁テープ基材と、上記第
１の絶縁テープ基材の表裏の何れか一方の面に形成され
上記信号用突子電極に接続されるインナリード部と外部
回路に接続されるアウタリード部とを有する第１の信号
用リードと、他方の面に形成され上記電源用突子電極に
接続されるインナリード部と外部回路に接続されるアウ
タリード部とを有する電源バスバーリードと、上記第２
の絶縁テープ基材の表裏の何れか一方の面に形成され上
記信号用突子電極に接続されるインナリード部と外部回
路に接続されるアウタリード部とを有する第２の信号用
リードと、他方の面に形成され上記接地用突子電極に接
続されるインナリード部と外部回路に接続されるアウタ
リード部とを有する接地バスバーリードとを備え、上記
半導体チップを上記各リードと共に樹脂封止したことを
特徴とする半導体装置。1. A semiconductor chip in which external connection electrodes for signals, power supplies, and grounds are mixedly arranged on the outer surface, and signals, power supplies, and grounds formed on the external connection electrode surface. A protrusion electrode, first and second insulating tape base materials arranged on both sides of the external connection electrode, and formed on one of the front and back surfaces of the first insulating tape base material. A first signal lead having an inner lead portion connected to the signal projection electrode and an outer lead portion connected to an external circuit, and an inner formed on the other surface and connected to the power supply projection electrode. A power supply bus bar lead having a lead portion and an outer lead portion connected to an external circuit;
A second signal lead having an inner lead portion formed on either one of the front and back surfaces of the insulating tape base material and connected to the signal projection electrode, and an outer lead portion connected to an external circuit; and the other. A ground bus bar lead having an inner lead portion formed on the surface of the above and connected to the grounding pole electrode and an outer lead portion connected to an external circuit, and the semiconductor chip is resin-sealed together with each of the leads. A semiconductor device characterized by:
リードのインナリード部の一端部が第１の絶縁テープ基
材の端部から突出するよう上記第１の信号用リードを上
記第１の絶縁テープ基材の表裏の何れか一方の面に形成
し他方の面に上記電源バスバーリードを形成すると共
に、第２の信号用リードおよび接地バスバーリードのイ
ンナリード部の一端部が第２の絶縁テープ基材の端部か
ら突出するよう上記第２の信号用リードを上記第１の絶
縁テープ基材の表裏の何れか一方の面に形成し他方の面
に上記接地用リードを形成したことを特徴とする請求項
１に記載の半導体装置。2. The first signal lead and the first insulating lead are insulated so that one end portions of inner lead portions of the power signal bus bar lead project from an end portion of the first insulating tape base material. The power supply bus bar lead is formed on either one of the front and back surfaces of the tape base material, and the power bus bar lead is formed on the other surface, and one end of the inner lead portion of the second signal lead and the ground bus bar lead is the second insulating tape. The second signal lead is formed on one of the front and back surfaces of the first insulating tape base material so as to project from the end of the base material, and the grounding lead is formed on the other surface. The semiconductor device according to claim 1.
用電極が外面に混在して配列された半導体チップと、上
記外部接続用電極面上に形成された信号用、電源用およ
び接地用突子電極と、上記外部接続用電極を挟みその両
側に配設された第１と第２の絶縁テープ基材と、上記信
号用突子電極に接続されるインナリード部と外部回路に
接続されるアウタリード部とを有する第１と第２の信号
用リードと、上記電源用突子電極に接続されるインナリ
ード部と外部回路に接続されるアウタリード部とを有す
る電源バスバーリードと、上記接地用突子電極に接続さ
れるインナリード部と外部回路に接続されるアウタリー
ド部とを有する接地バスバーリードとを備え、上記第１
の絶縁テープ基材の表裏の何れか一方の面に上記第１の
信号用リードと上記電源バスバーリードのアウタリード
部を、他方の面に上記電源バスバーリードのインナリー
ドを形成し、上記第１の絶縁テープ基材に形成されたス
ルーホールによって上記電源バスバーリードのアウタリ
ード部とインナリード部とを接続すると共に上記第２の
絶縁テープ基材の表裏の何れか一方の面に上記第２の信
号用リードと上記接地バスバーリードのアウタリード部
を、他方の面に上記接地バスバーリードのインナリード
を形成し、上記第２の絶縁テープ基材に形成されたスル
ーホールによって上記電源バスバーリードのアウタリー
ド部とインナリード部とを接続し、上記半導体チップを
上記各リードと共に樹脂封止したことを特徴とする半導
体装置。3. A semiconductor chip in which external connection electrodes for signals, power supplies, and grounds are mixedly arranged on the outer surface, and signals, power supplies, and grounds formed on the external connection electrode surface. A protrusion electrode, first and second insulating tape base materials provided on both sides of the electrode for external connection, and inner lead portions connected to the signal protrusion electrode and external circuits. A power supply bus bar lead having first and second signal leads each having an outer lead portion, an inner lead portion connected to the power supply electrode, and an outer lead portion connected to an external circuit; A ground busbar lead having an inner lead portion connected to the salient electrode and an outer lead portion connected to an external circuit;
The first signal lead and the outer lead portion of the power supply busbar lead are formed on one of the front and back surfaces of the insulating tape base material, and the inner lead of the power supply busbar lead is formed on the other surface. The outer lead portion and the inner lead portion of the power supply bus bar lead are connected by a through hole formed in the insulating tape base material, and the second signal for signal is provided on either one of the front and back surfaces of the second insulating tape base material. The lead and the outer lead portion of the ground busbar lead are formed, and the inner lead of the ground busbar lead is formed on the other surface, and the outer lead portion and the inner lead portion of the power supply busbar lead are formed by the through holes formed in the second insulating tape base material. A semiconductor device characterized in that it is connected to a lead portion, and the semiconductor chip is resin-sealed together with the leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP43A JPH06177202A (en) | 1992-12-07 | 1992-12-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP43A JPH06177202A (en) | 1992-12-07 | 1992-12-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06177202A true JPH06177202A (en) | 1994-06-24 |
Family
ID=18188094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP43A Pending JPH06177202A (en) | 1992-12-07 | 1992-12-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06177202A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007095977A (en) * | 2005-09-29 | 2007-04-12 | Elpida Memory Inc | Semiconductor device |
-
1992
- 1992-12-07 JP JP43A patent/JPH06177202A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007095977A (en) * | 2005-09-29 | 2007-04-12 | Elpida Memory Inc | Semiconductor device |
| JP4577690B2 (en) * | 2005-09-29 | 2010-11-10 | エルピーダメモリ株式会社 | Semiconductor device |
| US7847377B2 (en) | 2005-09-29 | 2010-12-07 | Elpida Memory Inc | Semiconductor device including semiconductor chip with two pad rows |
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