JPH06165272A - Exchange signal control system against input fault - Google Patents

Abstract

PURPOSE:To insert a bit pattern to an exchange signal of a telephone line leaked from a 2M signal having an input fault to the other 2M signal in a transmitter having two interfaces. CONSTITUTION:When a fault takes place in a telephone line, DET3a, 3b detect a fault of reception signals 1, 8 from an opposite station through ports A, B. A bit pattern of an exchange signal in response to each telephone line on the occurrence of the fault is stored in REG 6a, 6b and the bit pattern set in the REG6a, 6b is inserted to an exchange signal bit of the telephone line leaked from one 2M signal to other 2M signal by INS5a, 5b when the DET3a, 3b detect the fault and transmission signals 2, 7 are sent from the ports A, B to the opposite station.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch signal control system in the case of an input failure, and more particularly to a switch signal in the case of an input failure of a transmission device having two 2 Mbps interfaces and having a through function from one 2M signal to the other 2M signal. Regarding control method.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional exchange signal control system in the case of an input failure.

As shown in FIG. 2, this example comprises a speech path board 10 for encoding voice signals and exchange signals, and a common control unit (hereinafter, CCE) 20, the CCE 20 being the speech path board 10.
And a 2M signal, a drop / insert circuit 21 is provided for performing a drop or insert.

Further, the switch signal is sent from the 2M port as it is without controlling the switch signal to the telephone line passing through from the 2M signal having the input failure to the other 2M signal.

[0005]

In the conventional switching signal control system for input failure, a transmission device having two 2 Mbps interfaces has only a drop or insert function for a 2M signal and a speech path board.

Therefore, since it is not possible to control the exchange signal for the telephone line passing through from the 2M signal in which the input failure has occurred to the other 2M signal, there is a problem that a service abnormality such as a malfunction of the exchange signal is caused. It was

[0007]

SUMMARY OF THE INVENTION An exchange signal control system for an input failure according to the present invention has two 2M ports each having an interface of 2 Mbps, a 2M signal and a drop or insert function of a communication path board and one 2M signal. In a transmission device having a through function from one to the other 2M signal, the bit pattern of the exchange signal is stored when an input failure occurs in each telephone line that passes from the one 2M signal to the other 2M signal. This bit pattern is inserted in the exchange signal.

A fault detection circuit for detecting an input fault of each of the 2M ports, a time slot exchange circuit having the drop or insert function and the through function, and the exchanges corresponding to the telephone lines at the time of fault. A switch signal register that stores a bit pattern of a signal for each of the 2M ports, and a switch signal bit of a telephone line that passes through from the one 2M signal to the other 2M signal by the failure detection of the failure detection circuit. And a switch signal inserting circuit for inserting the bit pattern set in the signal register.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an exchange signal control system for an input failure according to the present invention.

Each of the embodiments shown in FIG. 1 is 2 Mbps.
CC with two 2M ports with different interfaces
It is a transmission device provided with E9 and having a 2M signal, a drop or insert function of the communication path board 10, and a through function from one 2M signal to the other 2M signal.

The CCE 9 is a time slot exchange circuit having a failure detection circuit (hereinafter referred to as DET) 3a, 3b for detecting an input failure of each 2M port, and a drop or insert function and a through function from one 2M signal to the other 2M. (Hereinafter referred to as TSSW) 4, and switch signal registers (hereinafter referred to as REG) 6a and 6b for storing bit patterns of a switch signal corresponding to each telephone line at the time of failure for each 2M port,
An exchange signal insertion circuit (hereinafter INS) 5a, which inserts the bit pattern set in the REGs 6a, 6b into the exchange signal bit of the telephone line that passes through from one 2M signal to the other 2M signal by detecting the failure of the DETs 3a, 3b,
5b and.

Next, the circuit operation of this embodiment will be described.

In FIG. 1, when a failure occurs in the telephone line, the DETs 3a and 3b detect the failure of the received signals 1 and 8 from the game at the ports A and B, respectively.

The bit patterns of the exchange signal corresponding to each telephone line at the time of failure are stored in REGs 6a and 6b, and D
When the ETs 3a, 3b detect a failure, the bit patterns set in the REGs 6a, 6b are inserted by INSs 5a, 5b into the exchange signal bits of the telephone line which passes through from one 2M signal to the other 2M signal, and the port A, respectively. B
Sends the transmission signals 2 and 7 to the game.

[0016]

As described above, the exchange signal control system according to the present invention for the input failure of the 2M signal is performed when the input failure occurs in each telephone line passing through from one 2M signal to the other 2M signal. By storing the bit pattern of the exchange signal, it is possible to prevent malfunction of the exchange on the opposite side.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an exchange signal control system according to an input failure of the present invention.

FIG. 2 is a block diagram showing an example of a conventional exchange signal control system in the case of an input failure.

[Explanation of symbols]

 1 Received signal from port A to station 2 Transmitted signal from port A to station 3a, 3b Fault detection circuit (DET) 4 Time slot exchange circuit (TSSW) 5a, 5b Exchange signal insertion circuit (INS) 6a, 6b Exchange Signal register (REG) 7 Received signal from port B to game station 8 Transmitted signal from port B to game station 9, 20 Common control unit (CCE) 10 Call path board 21 Drop insert circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazutoshi Tsuchiya 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Tomokazu Kato 1-4-28 Mita, Minato-ku, Tokyo NEC Transmission Engineering Co., Ltd. In-house (72) Inventor Kiyoji Utsumi 2 Raijin, Yoshioka, Yamato-cho, Kurokawa-gun, Miyagi Miyagi NEC Corporation

Claims (2)

[Claims] 1. A transmission device having two 2M ports each having an interface of 2 Mbps, and having a 2M signal, a drop or insert function of a speech path board, and a through function from one 2M signal to the other 2M signal, A bit pattern of the exchange signal may be stored and inserted into the exchange signal when an input failure occurs in each telephone line passing through from the one 2M signal to the other 2M signal. Switch signal control method for characteristic input disturbances. 2. A fault detection circuit for detecting an input fault of each of the 2M ports, a time slot exchange circuit having the drop or insert function and the through function, and the exchange corresponding to each telephone line at the time of fault. A switch signal register that stores a bit pattern of a signal for each of the 2M ports, and a switch signal bit of a telephone line that passes through from the one 2M signal to the other 2M signal by the failure detection of the failure detection circuit. 2. An exchange signal control system for an input fault according to claim 1, further comprising an exchange signal insertion circuit for inserting a bit pattern set in a signal register.