JPH06165143A - High efficiency encoding device and decoding device - Google Patents

Abstract

PURPOSE:To reduce the number of samples for image data propagated by an error flag. CONSTITUTION:The compressed data (a dynamic range DR, a minimum value MIN and n code signals DT) of each block obtained after ADRC coding are packed in a sync block in each 8 bits (1 byte). The dynamic range DR and the minimum value MIN constituting additional data are arranged at first and the n code signals DT (3 bits) constituting a bit plane are successively packed so as to be crowded in the byte direction. Even when an error flag is set up in the packed part of the bit plane, an error flag consisting of 8 bits is propagated only to the image data of 4 samples or less.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency coding apparatus and a decoding apparatus for packing coded data after ADRC coding in a sync block and then adding parity for transmission.

[0002]

2. Description of the Related Art FIG. 2 shows a system configuration example of a digital VTR.

In the figure, the video signal SVi supplied to the input terminal is converted into a digital signal by the A / D converter 12 and supplied to the blocking circuit 13. The blocking circuit 13 is provided for an ADRC encoder 14 to be described later, and the blocking circuit 13 divides the screen to form a large number of unit blocks.

The data of each block output from the block formation circuit 13 is supplied to the ADRC encoder 14 and is supplied to the ARC encoder 14.
DRC encoding processing is performed. FIG. 3 shows an example of the ADRC encoder.

In the figure, the data DI of each block output from the blocking circuit 13 is the maximum value detection circuit 141.
And the minimum value detection circuit 142 are sequentially supplied. The maximum value detection circuit 141 detects the maximum value MAX for each block, and this maximum value MAX is supplied to the subtraction circuit 143. Further, the minimum value detection circuit 142 detects the minimum value MIN for each block, and the minimum value MIN is supplied to the subtraction circuits 143 and 144. In the subtraction circuit 143, the minimum value MIN is subtracted from the maximum value MAX, and (MA
The dynamic range DR of the block represented by (X-MIN) is obtained.

Further, the data DI is supplied to the subtraction circuit 144 via the delay circuit 145. The delay circuit 145 delays the data DI of each block by the time required to detect the maximum value MAX and the minimum value MIN. In the subtraction circuit 144, the minimum value MIN
Is subtracted to form the data PDI after removal of the minimum value.

The data PDI after the removal of the minimum value, which is output from the subtraction circuit 144, is supplied to the quantization circuit 146. The dynamic range DR from the subtraction circuit 143 is supplied to the quantization circuit 146, and the quantization that is adapted to the dynamic range DR is performed. As the quantization bit number, a bit number smaller than the original bit number (for example, 8 bits), for example, 4 bits is used. For simplification, if the quantization bit number is 2 bits, a level range in which the dynamic range DR is divided into four is set, and a 2-bit code signal is assigned depending on which level range the data PDI belongs to.

Returning to FIG. 2, the minimum value MIN and dynamic range DR for each block output from the ADRC encoder 14 and the code signal DT for each pixel are supplied to the packing circuit 15 as compressed data. In Figure 4, A
The data per block after the DRC encoding process is shown.

Here, 1 block (1 sync block)
The compressed data per hit is dynamic range DR = L1 bit, minimum value MIN = L2 bit, bit plane = k
Bits × n (k is the number of quantization bits, and n is the number of pixels forming one block). In the packing circuit 15, the compressed data for each block is, for example, 8 bits (1 byte).
Packed in units.

FIG. 5 shows a conventional packing process. However, this is an example in which L1 = L2 = 8. First, the dynamic range DR and the minimum value MI that compose the additional data
N are arranged, and subsequently, n code signals DT forming a bit plane are sequentially packed. In this case, the direction of each code signal DT is orthogonal to the bite direction.

The compressed data packed by the packing circuit 15 is supplied to a parity adding circuit 16 to add a parity in byte units, and a modulation circuit 17 performs a modulation process, and then a recording head 18 through a recording amplifier 18. 19
And is recorded on a magnetic tape (not shown).

Next, the signal reproduced from the magnetic tape by the reproducing head 20 is supplied to the demodulation circuit 22 through the reproduction amplifier 21 and demodulated, and then supplied to the error correction circuit 23 and added in the recording system. Error correction processing is performed using the parity.

The compressed data output from the error correction circuit 23 is depacked by the depacking circuit 24, which is the reverse of the packing processing in the packing circuit 15 of the recording system, and then recorded by the ADRC decoder 25. In the ADRC encoder 14 of the system
ADRC decoding processing that is the reverse of the encoding processing is performed.

The data output from the ADRC decoder 25 is supplied to the block decomposing circuit 26 and subjected to a block decomposing process which is the reverse of that of the block circuit 13 of the recording system.
The video signal SVo is output to the output terminal 28 after being converted into an analog signal by the D / A converter 27.

[0015]

In the packing circuit 15 of the recording system of the digital VTR shown in FIG. 2, when packing the bit planes as described above, the direction of each code signal DT is perpendicular to the byte direction. Therefore, if an error flag is set in the part where the bit planes are packed (see FIG. 5), one error flag in 8-bit units propagates to the image data of 8 samples after ADRC decoding processing. was there.

Therefore, an object of the present invention is to reduce the number of image data samples in which one error flag propagates.

[0017]

The present invention has packing means for rearranging a code signal for each pixel after being coded by a quantization adapted to a dynamic range for each block in a sync block, In a high-efficiency encoder that adds a parity in byte units of a sync block and transmits it, the packing means packs a code signal sequentially in the byte direction after the additional code.

[0018]

According to the present invention, the code signals forming the bit planes are sequentially packed and packed in the byte direction, so that it is possible to reduce the number of image data samples in which one error flag propagates.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

The digital VTR of this example is also basically constructed as shown in FIG. Then, in the packing circuit 15 of the recording system, the compressed data (dynamic range DR, minimum value MIN and n code signals DT) for each block are packed in units of 8 bits (1 byte). Packing processing different from the example is performed.

FIG. 1 shows the packing process of this example. Here, the number of bits L1 of the dynamic range DR
And the number of bits L2 of the minimum value MIN is 8 bits, and the number of bits k of the code signal DT is 3 bits.

In the present example, the dynamic range DR and the minimum value MIN forming the additional data are arranged first, and subsequently the n code signals DT forming the bit plane are sequentially packed. In this case, the code signals DT are sequentially packed and arranged in the byte direction.

Since the packing circuit 15 performs the above-described packing process, the depacking circuit 24 (see FIG. 2) of the reproducing system performs the reverse depacking process.

The present example is constructed as described above, and the others are constructed similarly to the example of FIG.

In this example, the n number of code signals DT forming the bit plane during the packing process in the packing circuit 15 are packed in the byte direction sequentially. In this case, the number of code signals DT included in 8 bits forming each byte is 4 or less. Therefore, even if an error flag is set in a portion where the bit planes are packed (see FIG. 1), one error flag in 8-bit units can be propagated to image data of 4 samples or less after ADRC decoding processing. is there. Therefore, according to this example, it is possible to reduce the number of samples of image data in which one error flag propagates, as compared with the conventional example.

In the above embodiment, the case where the number k of bits of the code signal DT is 3 is shown, but the present invention is the same when the fixed length ADRC encoding process with other number of bits is performed. Can be applied to. Further, it is needless to say that the present invention can be similarly applied to the case of performing the variable length ADRC encoding process of quantizing with the number of bits different according to the range of the dynamic range DR.

[0027]

According to the present invention, since the code signals forming the bit planes are sequentially packed in the byte direction and packed, the number of image data samples in which one error flag propagates can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a packing process in an embodiment of the present invention.

FIG. 2 is a block diagram showing a system configuration example of a digital VTR.

FIG. 3 is a block diagram showing a configuration of an ADRC encoder.

FIG. 4 is a diagram showing data per block after ADRC encoding processing.

FIG. 5 is a diagram for explaining a conventional packing process.

[Explanation of symbols]

 11 Input Terminal 13 Blocking Circuit 14 ADRC Encoder 15 Packing Circuit 16 Parity Addition Circuit 17 Modulation Circuit 22 Demodulation Circuit 23 Error Correction Circuit 24 Depacking Circuit 25 ADRC Decoder 26 Block Decomposition Circuit 28 Output Terminal

Claims (2)

[Claims] 1. A packing unit for rearranging a code signal for each pixel after being coded by quantization adapted to the dynamic range of each block in a sync block, and parity for each byte of the sync block. In the high-efficiency encoding device for adding and transmitting, the packing means sequentially packs the additional code and the code signal in the byte direction to pack the code signal. 2. The data transmitted from the high-efficiency coding apparatus according to claim 1, wherein error correction is performed with the added parity, depacking processing is performed, and then decoding processing is performed. Decryption device.