JPH06164985A - Digital signal processor - Google Patents

Abstract

PURPOSE:To efficiently utilize a digital signal processor for processing high- speed digital signals for the processing of low-speed digital signals by dividing a transmission clock period into plural stages and changeover controlling the connection state of a network part at the respective stages. CONSTITUTION:The network part 11 of an NTSC system takes in control instructions from a host computer through a sequencer 20 to a network control part 111, switches the corresponding connection state and leads optional channel input to optional channel output. The digial video signals Sin1-Sin6 of the NTSC system are supplied to input terminals IN11-IN16. ALU 141-144 are capable of a high-speed processing for HDTV, the transmission clock period is divided into the plural stages and the connection state of the network part 11 is changeover controlled at the respective stages. Further, variable delays DL 181 and 182 are used as a latch circuit for one stage and respective high-speed computing elements are used in multiplex.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device for realizing low speed signal processing of, for example, NTSC digital video signals using a high speed signal processor of HDTV digital video signals.

[0002]

2. Description of the Related Art Generally, a digital video signal processing device used in a broadcasting station is composed of individual dedicated processing units according to the purpose of processing a video signal. Therefore, as the number of processing items increases, the number of units also increases, and the size of the entire apparatus becomes large. Along with this, a great deal of labor is required for construction work for realizing a desired processing function, such as device design, maintenance, and unit combination.

Therefore, recently, a digital image processing apparatus has been put into practical use, which can realize a desired processing function by software and does not require physical connection work. This device is equipped with a plurality of arithmetic processing units and a network unit, and each arithmetic processing unit is externally provided with a program corresponding to a processing item of a video signal to realize a target processing function, and the network unit externally receives an entire image. A program is provided according to the purpose of signal processing to realize a connection line that connects the functions obtained in each arithmetic processing unit.

On the other hand, in television broadcasting, an HDTV system has been developed for the purpose of improving the quality of broadcast video. The HDTV system has a much higher sampling frequency than the conventional NTSC system and requires various processing functions. Therefore, the digital image processing apparatus described above is also being put to practical use for HDTV by further developing the conventional apparatus.

However, broadcasting stations and the like tend to handle both the HDTV system video signal and the conventional system video signal, and it is necessary to handle the conventional system video signal when introducing the HDTV system digital video signal processing device in the future. There is.

As described above, the use of the signal processor for high-speed digital signals in the signal processing of low-speed digital signals is
Not only in the field of broadcasting equipment but also in the field of other electronic equipment, there is a strong demand for improvement in versatility.

[0007]

As described above, conventionally, it has been strongly demanded that a signal processor for high-speed digital signals can be easily used for signal processing of low-speed digital signals to enhance versatility. ing.

The present invention has been made in order to solve the above problems, and a digital signal processing device having higher versatility that can be easily used for signal processing of low speed digital signals even for high speed digital signals is provided. The purpose is to provide.

[0009]

In order to achieve the above object, the present invention is directed to a network portion having input / output terminals of a plurality of channels and capable of connecting arbitrary input / output terminals in accordance with an external control signal. Section is assigned to a digital signal input / output channel, and it is configured by connecting multiple high-speed arithmetic units and multiple variable delays between the input / output terminals of other channels, and switching the connection state in the network section according to an external control signal. Thus, in a digital signal processing device forming an arbitrary digital signal processing circuit using a high-speed arithmetic unit, the transmission rate of a low-speed digital signal sufficiently slower than the arithmetic speed of the high-speed arithmetic unit is replaced with a transmission rate suitable for the high-speed arithmetic unit. When signal processing is performed on high-speed digital signals, the transmission clock cycle is divided into multiple stages and A network control means for switching and controlling the connection state of the work part is provided, the plurality of variable delays are used as a latch circuit for one stage, and each high-speed arithmetic unit is multiplexed by appropriately intervening in the connection path of the network part. It is characterized in that it can be used.

[0010]

In the digital signal processing device having the above structure, when the digital signal processing device for high speed digital signal processing is used for signal processing of the low speed digital signal, the transmission clock cycle is divided into a plurality of stages, and the network is provided at each stage. Switching control of the connection state of the part. Further, a plurality of variable delays are used as a latch circuit for one stage, and appropriately intervened in the connection path of the network section, so that individual high-speed arithmetic units are used in multiple. This enhances the usage efficiency of the high-speed arithmetic unit.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIG.

FIG. 1 shows a configuration in which the present invention is applied to an NTSC digital video signal processing apparatus.
Reference numeral 11 is a network unit. This network part 11
Has a network control unit 111 inside, and this network control unit 111 switches to a connection state corresponding to a control command given from the outside, whereby an arbitrary channel input can be derived to an arbitrary channel output.

The input terminal IN11 of the network unit 11
To IN16 through NTSC digital video signals Sin1 to Sin6 via latch circuits 121 to 126, respectively.
Is supplied to IN21 to IN210, and a constant R
in1 to Rin10 are supplied. Further, the output terminals OUT11 to OUT11
The signals derived to OUT16 are latch circuits 131 to 13
6 through the channel outputs Sout1 to Sout6 of the device.
Becomes

The output terminal OUT3 of the network section 11
1a and 31b, 32a and 32b, 33a and 33b, 34
The signals derived to a and 34b are respectively subjected to arithmetic processing by ALUs (arithmetic logic operation units) 141 to 144 and then supplied to the input terminals IN31 to IN34 of the network unit 11 via the latch circuits 151 to 154. .

Similarly, the output terminal OU of the network unit 11
T41a and 41b, 42a and 42b, 43a and 43b,
The signals derived to 44a and 44b are respectively MPY
After being arithmetically processed by (multiplication unit) 161 to 164, it is supplied to the input terminals IN31 to IN34 of the network unit 11 via the latch circuits 171 to 174.

The signals output to the output terminals OUT51 and OUT52 are respectively variable delay (DL) 18 signals.
1, 182 through the input terminal IN5 of the network unit 11
1, IN52.

Each of the ALUs 141 to 144 fetches the output data of the channel 2 system selected by the network unit 11 and performs the arithmetic processing designated by the given control command. Here, an HDTV capable of high-speed processing is used.

The MPYs 161 to 164 respectively take in the output data of the channel 2 system selected by the network unit 11 and perform a multiplication process on both. HD here too
A TV capable of high-speed processing is used.

The variable delays 181 and 182 respectively take in the output data of the channel 1 system selected by the network section 11 and delay the output data by the number of clocks designated by a given control command. In this case as well, an HDTV capable of high-speed processing is used.

This digital signal processor is managed by a host computer (not shown). In particular,
The host interface (HIF) 19 is connected to a host bus (not shown) to receive a control command from the host computer and send it to the sequencer 20. Sequencer 2
0 indicates from the control command that the network unit 11 and the ALU 14
1 to 144 and control commands for the variable delays 181 and 182 are generated. Further, the sequencer 20 receives the monitor command from the host computer side and sends back the control status of each unit.

The timing control of each circuit section in the apparatus is performed by the clock CK generated by the clock generation section 21. The clock generation unit 21 generates a clock for each circuit unit based on the clock CLK sent together with the data of the input signal. The network control unit 111 of the network unit 11 will be described more specifically.

First, the control command given from the sequencer 20 to the network control unit 111 is, as shown in FIG. 2A, an input code for designating the connection state and an instruction for instructing to go down or to return to address 0. Bit (CONT:
It goes down at 0 and returns to address 0 at JUNP: 1), and the network control unit 111 has a memory for storing, for example, 4 words of this control command.

Control commands are stored in this network control memory, for example, as shown in FIG. The network control unit 111 executes processing from address 0 of this memory, and controls switching to the connection state corresponding to the code of each command at the clock rate. Here, if the instruction bit of the control command is 1, the process proceeds to address 0 next. Therefore, the network unit 11 is, for example, as shown in FIG.
As shown in (c), the connection state can be cyclically switched in clock units. The switching control of the network is started at the timing when the video blanking period (VBL) comes to the video valid period. The above circuit configuration is integrated into one IC, and the DSP (digital
Signal processor). The operation of the digital video signal processing device having the above configuration will be described below. Now, consider the following conditions when setting the model of the video signal processing DSP capable of supporting both HDTV and NTSC.

(1) Having a plurality of high-speed arithmetic units. Figure 1
In this embodiment, four ALUs and MPYs are provided, respectively. With the recent improvement in device technology, H
It is easy to have a plurality of arithmetic units that perform high-speed arithmetic corresponding to DTV signals in one IC. Here, the calculation speed corresponding to HDTV is half the sampling frequency, for example, 37.
Set to 125 MHz.

(2) Connection between arithmetic units can be arbitrarily established. Even if there are multiple computing units, they cannot be effectively used unless there is a degree of freedom in their connection. In the embodiment shown in FIG. 1, the network unit 11 for arbitrarily connecting the arithmetic units is provided.

(3) The connection between arithmetic units is programmable in real time. The processing efficiency is improved by enabling the connection between a plurality of arithmetic units to be switched in real time at the same speed as the arithmetic speed by a program. In the embodiment of FIG. 1, the network control unit 111 is provided in the network unit 11 so that the connection state is sequentially switched in clock units.

Here, in the embodiment of FIG. 1, the number of switching cycles of the network control unit 111 is set to, for example, 4 clocks at maximum, but there are cases where NW control is required only every 2 clocks. In this case, the clock rate of the clock generation unit 21 is specified to be 1/2 so that the control can be performed four times every two clocks.

According to the above conditions, 37.125M
Some usage forms will be considered in the case of applying a DSP arithmetic IC operating at Hz to various video signals of HDTV and NTSC as a key component. First, regarding the multiple use of the high-speed arithmetic unit, the definition of terms necessary for the processing form will be described. (1) Multiplicity m, transmission rate r1, sampling rate r2

When the high-speed video signal (HDTV) transmission rate (which is the clock rate of the arithmetic IC and also the high-speed arithmetic rate) is r1 and the sampling rate of the low-speed video signal (NTSC) is r2, the multiplicity m is (1 ) Is given by the formula. m = r1 / r2 (1)

Normally, m = 2, but this setting is r2 = 13.5 MHz during component signal processing, so r
1 = 40 MHz, which can be realized with current technology.
Further, since the C signal has a half band of the Y signal, if m = 2 for the Y signal, m = 4 for the C signal.
Therefore, it is assumed here that m = 4 is the maximum. (2) Number of computing units n

The numbers of multipliers (MPY) and ALUs do not necessarily have to be the same, but here, four MPYs and ALUs are used.
Four are installed in one IC. However, for generalization, it is defined as the number of arithmetic units n. (3) Stage No

When there are m clocks in one sample period, the m clocks are numbered and the i-th (1 <i≤m) time slot is called the i-th stage.

Based on the above definition, the processing form of the NTSC signal will be described below. There are various NTSC signal transmission formats, but here, as an example, consider the case where the transmission rate is an integral multiple of the video sampling rate. Assuming a case of m times the sampling rate, since m is a constant, only dummy data is inserted and a memory for speed conversion is not particularly required. In this case, the transmission format is as follows. V1, *, ..., *, V2, *, ..., *, to * are dummy data, and when the multiplicity is m, only one input data is valid for m, and the remaining (m-1) Is dummy data.

FIG. 3 shows a simple example. Here, as a simplified model, a case in which the number of arithmetic units in the DSP is as small as 1 to 2 as shown in FIG. 4A will be described. still,
The MPY and ALU arithmetic units originally have two inputs, but for simplicity, assume a case of arithmetic with a constant and write as one input. The part delimited by "|" in FIG. 3 represents a latch circuit.

Assume that the DSP implements a circuit configuration for sequentially performing multiplication, addition, multiplication, and addition by MPY1, MPY2, ALU1, and ALU2 for NTSC signals, as shown in FIG. 3 (a). The calculation in this case can take data in two stages. However, if the stages are allocated as they are, different MPYs 161 and 162 and ALUs 141 and 142 are respectively provided as shown in FIG.
Therefore, both MPY and ALU cannot be assigned to the first and second stages.

Therefore, the variable delay 181 is shown in FIG.
If the variable delay 181 has a latch function by dynamically connecting as shown in FIG.
Both LUs can be distributed to the first and second stages. This can be expected to improve the efficiency of use of computing units.
This is shown in FIGS. 4 (b) and 4 (c). FIG. 4B shows the DSP connection state of the first stage, and FIG. 4C shows the DSP connection state of the second stage. Next, a method of inserting the variable delay 181 will be described.

Now, in the directed graph GP excluding the feedback loop, when it is desired to distribute the arithmetic unit mi and the arithmetic unit mj to different stages, and mi and mj are on the same stage, either one of mi and mj is in front. Stage insertion can be advanced by one stage by inserting one latch.

At this time, the number of latches in the directed graph GP is only related to the system delay unless it affects the stage distribution completed up to that point, so that it will be completed someday. In order not to affect the stage distribution completed so far,
The path length may be adjusted after inserting (the number of stages-1) latches immediately after the arithmetic unit in which the latches are inserted. Finally, the m consecutive latches in one branch are carefully removed to preserve the path length difference.

Since the number of stages to be distributed is determined by the number of latches to be inserted, it is possible to distribute to any stage. Here, the path length is the total number of latches in the network path having the arithmetic unit as a node, and the path length matching is to make the difference between the path lengths entering one node constant. Consider the case where the butterfly circuit shown in FIG. 5A is realized by the DSP of FIG. 1 by applying the above method.

In FIG. 5A, Sin1 and Sin2 are NTSC signals. Sin1 is a multiplier MPY1,
After being multiplied by a predetermined coefficient in MPY2, adder ALU
1, sent to ALU2. Sin2 is a multiplier MPY
1 and MPY2 are multiplied by a predetermined coefficient, and then the adder AL
It is sent to U1 and ALU2. Adders ALU1 and ALU2
The result of each addition of ALU3 and ALU4 is a constant α,
β is added to form output signals Sout1 and Sout2.

In the above circuit, m = 2, n = 2 (MP
If Y and ALU are each two and the multiplicity is 2, for example, distribution as shown in FIGS. 5B and 5C can be considered.

In FIG. 5B, 1 is set to MPY1 and MPY2.
61, 162 for MPY3, MPY4, AL
U1 and ALU2 are 141, ALU3 and ALU4 are 142, and the variable DLs 181 and 182 are MPY2 and MPY4 as one-stage latch circuits.
Multiple input is realized by interposing it on the input line of.
6 (a) to 6 (d) show connection states at each stage of the network unit 11.

In FIG. 5C, 1 is set in MPY1 and MPY3.
61, 162 for MPY2 and MPY4, AL
U1 and ALU3 are 141, ALU2 and ALU4 are 142, and variable DLs 181 and 182 are MPY3 and MPY4 as latch circuits for one stage, respectively.
The input line and the output lines of MPY1 and MPY2 intervene to realize multiple use. Fig.7 (a)-
(D) shows a connection state at each stage of the network unit 11.

As is clear from the above example, the variable DL
By appropriately inserting the latch by the real time, it becomes possible to effectively use the high speed arithmetic unit during low speed digital signal processing.

In the above embodiment, the DSP for HDTV is used.
I explained the case of using for NTSC,
The present invention is not limited to such television signal processing, and can be similarly realized if a device for high-speed digital signal processing is used for low-speed digital signal processing. Needless to say, various modifications can be made without departing from the scope of the present invention.

[0046]

As described above, according to the present invention, it is possible to provide a more versatile digital signal processing device that can be easily used for signal processing of low speed digital signals even for high speed digital signals. it can.

[Brief description of drawings]

FIG. 1 is an overall block configuration diagram showing configurations of a digital signal processing device according to the present invention and a digital video signal processing device as one embodiment.

FIG. 2 is a diagram for explaining a control method of a network control unit of the embodiment.

FIG. 3 is a circuit diagram for explaining a simple usage pattern of the embodiment.

FIG. 4 is a diagram showing a connection state of each stage in the circuit configuration of FIG.

FIG. 5 is a circuit diagram illustrating distribution of high-speed arithmetic units when the present invention is applied to a butterfly circuit.

FIG. 6 is a diagram showing a connection state of each stage in the circuit configuration of FIG.

7 is a diagram showing a connection state of each stage in the circuit configuration of FIG. 5 (c).

[Explanation of symbols]

11 ... Network unit, 111 ... Network control unit,
121-126 ... Latch circuit, 131-136 ... Latch circuit, 141, 144 ... Arithmetic unit (ALU), 151-1
54 ... Latch circuit, 161-164 ... Multiplier (MP
Y), 171 to 174 ... Latch circuit, 181 to 182 ...
Variable delay circuit (DL), 19 ... Host interface (HIF), 20 ... Sequencer (SEQ), 21 ...
Clock generator.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Kazuo Fukui 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the broadcasting technology research institute of Japan Broadcasting Corporation (72) Inventor Nobuyuki Sasaki Komukai Toshiba Town, Kawasaki City, Kanagawa Prefecture No. 1 Stock Company Toshiba Komukai Factory

Claims (2)

[Claims] 1. A digital signal input / output channel is partly allocated to a part of a network section which has input / output terminals of a plurality of channels and enables connection between arbitrary input / output terminals according to an external control signal. It is configured by connecting multiple high-speed arithmetic units and multiple variable delays between output terminals, and by switching the connection state in the network section according to the external control signal, an arbitrary digital signal processing circuit using the high-speed arithmetic unit can be realized. In the digital signal processing device to be formed, when performing signal processing on a high-speed digital signal in which the transmission rate of a low-speed digital signal that is sufficiently slower than the operation speed of the high-speed arithmetic unit is replaced with a transmission rate suitable for the high-speed arithmetic unit, its transmission clock A network controller that divides the cycle into multiple stages and controls switching of the connection state of the network unit at each stage. A digital signal having a plurality of stages, each of the variable delays being used as a latch circuit for one stage, and being appropriately interposed in a connection path of the network unit so that individual high-speed arithmetic units can be used in a multiple manner. Processing equipment. 2. The high-speed arithmetic unit is for HDTV signals,
The digital signal processing apparatus according to claim 1, wherein the low-speed digital signal is an NTSC signal.