JPH06164620A - Cell flow rate measuring circuit for atm system - Google Patents

Abstract

PURPOSE:To reduce the memory scale by storing the frequency of the same cell flow rate at each measuring time interval when the cell flow rate is measured in an ATM system. CONSTITUTION:A frequency distribution storing memory 6 inputs a cell flow rate signal S6 and stores the frequency of the same cell flow rate at each measuring time interval. A frequency latch circuit 7 latches the frequency from the memory 6 at each measuring time interval. Then a frequency adder circuit 8 increases the latches frequency. In such a constitution, the frequency of the same cell flow rate is stored in the memory 6 at each measuring time interval with the cell flow rate define as a memory address. Thus the scale of the memory 6 can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell flow rate measuring circuit for an ATM system, and more particularly to a cell measuring circuit for measuring a cell flow rate with a frequency distribution for each cell.

[0002]

2. Description of the Related Art Generally, a cell flow measuring circuit of this type is
The cell flow count value for the number of measurements is stored in the memory at each measurement time interval. FIG. 2 shows a block diagram of a conventional example.

A VPI latch circuit 9 latches a virtual pulse signal (hereinafter referred to as VPI) for identifying all cells of the input data S12, and a VPI comparison circuit 10 compares it with a designated VPIS14. The cell flow counter 12 counts the number of cells for which the VPI matches,
The value of the cell flow counter 12 is read and reset by the measurement interval pulse S16 of the measurement time interval counter 11. The cell flow rate storage memory stores the cell flow rate S17 with the number of measurements S18 as an address value. The measurement number counter 13 counts the measurement interval pulse and outputs the measurement number signal S18.
Is output. The cell flow rate storage memory 14 outputs the frequency distribution data S19 for each designated number of measurements.

[0004]

The above-mentioned conventional cell flow rate measuring circuit stores the cell flow rate count value for each address corresponding to the number of times of measurement, so that it has a memory address corresponding to the number of times of measurement of, for example, 10 ⁷ order. There is a problem that the memory capacity becomes large.

[0005]

A cell flow measuring circuit of an ATM system according to the present invention includes a partial path signal latch circuit for latching a partial path signal attached to a reception cell of input data, and a partial path signal and a specified partial path signal. , A measurement time interval counter that generates a specified measurement time interval pulse, a cell flow rate counter that counts the output pulse of the virtual path signal comparison circuit with the measurement time interval pulse, and this cell flow rate counter The flow rate value to be output is used as a memory address, the frequency of the same flow rate value is stored, and the frequency distribution storage memory for outputting the frequency distribution data of the flow rate value stored by the write inhibit pulse and the measurement time interval pulse are stored. Count the specified number of times and generate the write inhibit pulse. And a number of times counter.

[0006]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The VPI latch circuit 1 latches the VPI of all the cells of the input data S1, and the VPI comparison circuit 2 specifies the specified VPI.
Compare with PIS3. The cell flow counter 4 counts the number of cells having the same VPI, and the value of the cell flow counter 4 is read and reset by the measurement interval pulse of the measurement time interval counter 3. The frequency distribution storage memory 6 stores the frequency of the same cell flow rate using the cell flow rate signal S6 as a memory address.

The frequency latch circuit uses the cell flow rate value signal S6 of the cell flow rate counter 4 as a memory address at each measurement time interval to access the frequency distribution storage memory 6 and latch the frequency data. The frequency addition circuit 8 adds 1 to this frequency data and stores it again in the memory. In addition, the measurement number counter 5 counts the measurement interval pulse S5 and generates a write inhibit pulse S7 that inhibits writing to the memory at a specified number of measurements. As a result, the frequency distribution storage memory 6
Outputs frequency distribution data S11. The memory of the frequency distribution memory 6 has a memory address corresponding to a cell flow rate of the order of 10 ³ and has a small memory scale.

[0009]

As described above, the present invention has the effect of reducing the memory scale by storing the frequency of the same cell flow rate in the memory at each measurement time interval using the cell flow rate as a memory address.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

[Explanation of symbols]

 1 VPI latch circuit 2 VPI comparison circuit 3 Measurement time interval counter 4 Cell flow rate counter 5 Measurement number counter 6 Frequency distribution storage memory 7 Frequency latch circuit 8 Frequency addition circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiro Okatsu 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (2)

[Claims] 1. A partial pass signal latch circuit for latching a partial pass signal attached to a reception cell of input data, a partial pass signal comparison circuit for comparing the partial pass signal with a preset specified pass signal, and a specified measurement. A measurement time interval counter that generates a pulse of a time interval, a cell flow rate counter that counts the output pulse of the partial path signal comparison circuit with the pulse of the measurement time interval counter, and a flow rate value output by this cell flow rate counter as a memory address. The frequency distribution storage memory that stores the frequency of the same flow rate value and outputs the frequency distribution data of the flow rate value stored by the write-inhibit pulse, and the pulse of the measurement time interval counter is counted a specified number of times. Of the number of measurements that generate the lock pulse And A
Cell flow measurement circuit of TM system. 2. The frequency distribution memory receives a flow rate value from the flow rate counter, uses the flow rate value as a memory address and stores the frequency, and a frequency latch circuit that accesses the memory and latches the frequency data. 2. A cell flow rate measuring circuit for an ATM system according to claim 1, further comprising a frequency adding circuit for adding 1 to the frequency data output from the frequency latch circuit and storing it again in the memory.