JPH06164423A - Viterbi decoder - Google Patents

Abstract

PURPOSE:To provide a Viterbi decoder which prevents overflow in the storage of path metric values and reflects the past condition on path metric values. CONSTITUTION:In steps S11 and S12, branch metrics DAA and DCA are added to path metric values MA<n> and MC<n>. In a step S13, new path metric values are compared with each other; and in a step S14, one path whose sum of humming distances is shorter is selected as a surviving path. In a step S15, overflow processing is performed; and in the case of excess over a maximum storage value of path metric values, an extent alpha of excess is subtracted from path metric values to store a value MA<n-1> made relative. In the overflow processing in a step S25, path metric values surviving in the same manner are subjected to alpha subtraction processing to perform the required overflow processing furthermore. Consequently, path metric values do not overflow.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a Viterbi decoder suitable for decoding a code expressed as a shift register process, such as a convolutional code.

[0002]

2. Description of the Related Art The basis of Viterbi decoding is maximum likelihood decoding. Maximum likelihood decoding determines and decodes the most probable encoded data sequence by calculating the Hamming distance of each of these possible encoded data sequences and the received data sequence received over the channel. It is a decoding method.

When determining and decoding the maximum likelihood path of maximum likelihood decoding, as the number of received data increases, the number of coded data strings to be processed increases exponentially, and all Hamming is performed. There is a problem that the decoder for calculating the distance becomes huge. In the Viterbi decoding method, the number of calculations required to select a coded data string is determined by the convolutional encoder configuration based on the correlation between the data in the data sequence, which is the repeating structure of the convolutional code. It is a decoding method that maximizes the likelihood while suppressing the above.

The convolutional code can be illustrated by the trellis diagram of FIG. States A, B, C,
In the four states of D, in the states of A and C,
If the input data is "0", it transits to A, and if it is "1", it transits to B. Further, in the states of B and D, if the input data is "0", it transits to C, and if it is "1", it transits to D.
Therefore, in each state after step 3, the number of paths that transit from the previous state is limited to two. The Viterbi decoding method is a method in which a path having a smaller Hamming distance to a received data string is selected from the two paths reaching each state, and this path is stored as a surviving path.

Since the path metric (path likelihood) in the surviving path is accumulated every time, the storage capacity of the register of each path metric value may overflow. Conventionally, a method of clearing after calculating a path metric value a certain number of times has been adopted.

However, in this method, the path for the time from the start of reception to the present should be taken into consideration, but the path metric value is in a certain limited time range. There is a problem that it cannot be decrypted.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and it is possible to prevent the storage of the path metric value from overflowing and to perform decoding in which the path metric value can reflect the past situation. It is an object of the present invention to provide a simple Viterbi decoder.

[0008]

According to a first aspect of the present invention, in a Viterbi decoder, a storage unit for storing a path metric value for performing maximum likelihood processing, and a storage unit A comparison unit that compares the stored path metric value with a predetermined value and a subtraction unit that subtracts all path metric values by a desired value, and causes the subtraction unit to perform the subtraction based on the comparison result of the comparison unit. It is characterized by that.

According to the second aspect of the present invention, in the Viterbi decoder, a storage unit for storing a path metric value for performing maximum likelihood processing and a minimum value of all path metric values are detected. It is characterized in that it has a minimum value detection unit and a subtraction unit that subtracts all path metric values by a desired value, and that subtraction is performed by the subtraction unit based on the output data of the minimum value detection unit. is there.

[0010]

According to the present invention, since the path metric value can be stored relative to each other, the path metric value reflecting the past situation can be obtained, and the storage of the path metric value overflows. It is possible to realize a Viterbi decoder that does not have any.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory diagram of an operation flow of an embodiment of a Viterbi decoder of the present invention. In this description, four states of A, B, C, and D are considered corresponding to FIG. The path metric values of the surviving paths in the four states of A, B, C, and D in step n are MA ⁿ , MB ⁿ , MC ⁿ ,
^Let MD ⁿ . In each state A, B, C, D of step (n + 1) where the next reception point data is obtained, only two transitions exist from step n, respectively,
The Hamming distances between the reception points of the two branches and the signal points in each state that arrive from step n are calculated to obtain the branch metric.

In FIG. 1, only the transitions from state A and state C are shown. The transitions from state A and state C are only from state A and state B. In S11, the path metric value M
The branch metric D _AA is added to A ⁿ , and in S12, the branch metric D _CA is added to the path metric value MC ^n.
Is added. The sum of both path metric values and the branch metric is compared in S13, and the smaller sum of the Hamming distances is selected as the surviving path in S14. S1
At 5, overflow processing is performed. In this embodiment, the path metric value is compared with the maximum storage value in the storage area, and if it does not exceed the maximum storage value, the path metric value MA ^{n + 1} of the selected path is stored in S16. The processing of the path transiting to the state A is ended. Next, the transition process to the state B is performed. In S21, the branch metric D _AB is added to the path metric value MA ⁿ , and in S22, the branch metric D _CB is added to the path metric value MC ⁿ . The sum of both path metric values and the branch metric is compared in S23, and the smaller sum of the Hamming distances is selected as the surviving path in S24. At S25, overflow processing is performed. Similarly, the path metric value is compared with the maximum storage value in the storage area, and if it does not exceed this, S2
6, the path metric value MB of the selected path
^{Although n + 1} is stored and the processing of the path transiting to the state B is terminated, if the path metric value exceeds the maximum storage value in the overflow processing of S25, the excess amount α is set to the path metric value. Subtracting and further recalling the previously stored path metric value MA ^{n + 1} , subtracting the same excess α, updates the stored value of MA ^{n + 1} . Then, the excess α
Is stored and the path metric value MB ^{n + 1} obtained by subtraction is stored and the processing of the state B is ended.

In the overflow process of S15, if the path metric value exceeds the maximum storage value, the excess α
Only the path metric value is subtracted, and the relativized path metric value MA ^{n + 1} is stored. Further, in the overflow processing of S25, for the surviving path metric value,
The subtraction process is performed by the excess amount α, the subtraction result is compared with the maximum storage value, and the overflow process described above is further performed. Similarly, after the processing of all the states is completed, the path having the smallest path metric value is selected and the value of the reception point before the predetermined number of steps is determined.

The overflow process may be performed after the surviving paths of all the states are determined. However, in such a case, a work area for temporarily storing all path metric values is required, and an area that does not overflow must be secured.

Further, the subtraction processing when overflow occurs is not limited to the subtraction of the excess α. Before moving to the next step, or
When all surviving paths have been determined, such as when that step is completed, the minimum path metric value is detected, and a value that does not exceed this is determined as the subtraction amount β, and this is subtracted from the subtraction amount α described above. May be used instead of.

In the above-described embodiment, the relativization process is performed so that the subtraction process is performed when an overflow occurs. However, the subtraction process may be performed even in a state where overflow does not occur. Relativization may be performed by subtracting from all the path metric values by the above-described subtraction amount β in each step or in each of a plurality of steps.

In the above embodiment, the Hamming distance was used as the path metric value, but the Euclidean distance between the receiving point and the signal point may be used to calculate the path metric value.

FIG. 3 is a block diagram of an embodiment in which the automatic equalizer of the present invention is applied to a facsimile machine. This facsimile machine is based on CCITT Recommendation V.6. It is based on 17. In the figure, 1 is an AGC circuit, 2 is an A / D converter, 3
Is a feedback circuit, 4 is a demodulation unit, 5 is an automatic equalization unit, 6 is a reference signal unit, 7 and 8 are control units, 9 is a phase correction unit, 10 is a Viterbi decoding unit, 11 is a tentative determination unit, 12 is etc. Error detector, 13
Is a phase error detector, 14 is an input terminal, and 15 is an output terminal. The phase modulation signal is input to the input terminal 14 and
The gain is adjusted in the GC circuit 1, and the A / D converter 2
Is converted into a digital signal by. The feedback circuit 3 controls the AGC circuit 1 based on the amplitude value of the digital signal. The demodulation unit 4 uses the signal from the reference signal unit 6 to discriminate the digital signal into an I component and a Q component. The automatic equalization unit 5 removes the signal distortion generated on the line from each of the discriminated output signals. The signal equalized by the automatic equalization unit 5 is decoded by the Viterbi decoding unit 10, but the Viterbi decoding unit 1
At 0, the signal point is output to the output terminal 15 as the determination result. In the Viterbi decoding, the above-described overflow processing is performed, and the step where the overflow processing is performed and the subtraction value thereof are stored. Therefore,
An absolute value is calculated from the relativized path metric value and output to the control unit 7. The signal output to the output terminal 15 is
The differential code is decoded, the descrambler is performed, and the original data string is restored.

The tentative decision section 11 decides a point closest to the reception point, which is the output value of the automatic equalization section 5, as a signal point. The difference between the reception point and the signal point is detected by the equalization error detection unit 12 and given to the control unit 7 to control the variable multiplication coefficient of the automatic equalization unit 5. At the same time, the control unit 7 is controlled by the path metric value from the Viterbi decoding unit 10, and when the path metric value is large, the change amount of the variable multiplication coefficient by the error signal is increased, and when the path metric value is small, , The amount of change in the variable multiplication coefficient due to the error signal is reduced.

The control of the variable multiplication coefficient coefficient by the path metric value may be performed by multiplying the error signal by the path metric value, or by giving the change amount of the variable multiplication coefficient as a step value, the step determined by the error signal. The value may be increased or decreased according to the path metric value.

The phase error detection unit 13 detects a phase error between the reception point in the output of the automatic equalization unit 5 and the signal point by the temporary determination unit 11, and controls the phase correction unit 9 via the control unit 8. And compensate for phase jitter. The output of the phase error detection unit 13 is also given to the reference signal unit 6 to adjust the phase of the reference signal.

The change in updating the variable multiplication coefficient is performed in the controller 7 according to the path metric value. However, the path metric value from the Viterbi decoder 10 is also added to the controller 8 to change the phase. The correction data of the correction unit may also be provided with a correction coefficient according to the path metric value.
Phase compensation when an instantaneous error occurs can be performed more stably.

In the modem including the automatic equalizer described in this embodiment, two DSPs are formed on one chip, and the Viterbi decoding unit 10 and the tentative determination unit 11 are connected to the first DS.
P, and other functions such as modulation / demodulation, scrambler / descrambler, automatic equalization, etc.
It is possible to process with P.

[0024]

As is apparent from the above description, according to the present invention, since the path metric values can be stored relative to each other, the path metric value reflecting the past situation can be obtained. Further, there is an effect that it is possible to realize a Viterbi decoder in which the storage of the path metric value does not overflow.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an operation of an embodiment of a Viterbi decoder of the present invention.

FIG. 2 is an explanatory diagram of a trellis diagram.

FIG. 3 is a block diagram of an embodiment in which the Viterbi decoder of the present invention is applied to a facsimile device.

[Explanation of symbols]

 4 demodulation unit 5 automatic equalization unit 6 reference signal unit 7, 8 control unit 9 phase correction unit 10 Viterbi decoding unit 11 temporary determination unit 12 equalization error detection unit 13 phase error detection unit

Claims (2)

[Claims] 1. A Viterbi decoder, a storage unit for storing a path metric value for performing maximum likelihood processing, a comparison unit for comparing a path metric value stored in the storage unit with a predetermined value, and all paths. A subtraction unit for subtracting a desired value from the metric value, based on the comparison result of the comparison unit,
A Viterbi decoder characterized in that subtraction is performed by a subtraction unit. 2. A Viterbi decoder, a storage unit for storing a path metric value for performing maximum likelihood processing, a minimum value detection unit for detecting a minimum value of all path metric values, and A Viterbi decoder having a subtraction unit for subtracting a desired value of a path metric value, and performing subtraction by the subtraction unit based on output data of the minimum value detection unit.