JPH06163714A - Semiconductor device having multilayer interconnection structure and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having a remarkable reliability in a via structure and the manufacturing method thereof. CONSTITUTION:A layer insulating film 40 is formed on a ground insulating film 20 including a lower wiring layer 30 at the upper side of a substrate main body 10 in the first step. A via hole 50 is formed in the layer insulating film 40 in the second step. A via film 51a is formed on the layer insulating film 40, wherein the via hole 50 is formed in the third step. These steps are provided. The via film 51a formed at the bottom surface of the via hole 50 is removed in the fourth step. Al or Al alloy is deposited on the via hole 50 and a via plug 52a is formed in the fifth step. These steps are further provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a via plug (embedded plug) used in a semiconductor device, and particularly, to manufacture a via structure having high reliability even when miniaturization progresses. The present invention relates to a method for forming a via plug which is effective for achieving the above.

[0002]

2. Description of the Related Art Conventionally, a via plug using Al or an Al alloy is formed by a selective CVD method using dimethylaluminum hydride (DMAH) and hydrogen as raw materials, as disclosed in, for example, JP-A-4-51525. , Was formed by depositing Al or Al alloy only from the bottom surface of the via hole.

This method will be described in detail with reference to FIG. FIG. 6A shows a step after forming the via hole 50. A base insulating film 20 and a patterned lower layer metal wiring 30 are formed on a Si substrate 10, and an interlayer insulating film 40 which is a first insulating film is formed so as to cover these. Figure 6
In the step (b), a CVD-Al via plug 52 is selectively grown in the via hole 50.

[0004]

However, in reality, the via plug 52 cannot be ideally formed as described above, and the following problem may occur.

That is, as shown in FIG. 7A, after the mask 70 is set, the material 80 of the lower layer metal wiring 30 is sputtered by RIE when opening the via hole 50, and the inside of the via hole 50 is sputtered. It adheres to the peripheral surface. Then, when the via plug 52 is formed by the selective CVD method, the selectivity of the selective CVD method is deteriorated by the material 80 of the metal wiring attached to the inner peripheral surface of the via hole 50. Al or Al alloy is also deposited on the inner peripheral surface of the hole 50. As a result,
As shown in FIG. 7B, there is a problem that the via plug 52 is deformed and a void 90 is generated, so that the reliability of the via structure or the upper metal wiring formed on the via plug 52 is lowered. is there.

Further, when the upper layer metal wiring 60 is formed after forming the via plug 52, the alignment of the mask 70 may be misaligned. As a result, as shown in FIG. 8, the edge of the mask 70 enters the inside of the via hole 50 to etch the Al or Al alloy forming the via plug 52 to generate the void 100 in the via hole 50. There is. This void 100 causes a decrease in reliability of the via structure, and also causes chlorine corrosion used for Al etching when forming the upper layer metal wiring 70, and moisture corrosion during cleaning to cause Al corrosion. There are also problems.

Therefore, an object of the present invention is to provide a method for solving the above problems.

[0008]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention has a lower-layer metal wiring formed on a substrate and a first-layer formed on a surface including the lower-layer metal wiring. An insulating film, an opening formed by etching away a predetermined position of the first insulating film to expose the lower metal wiring, and a second insulating film formed around the inner peripheral surface of the opening. When,
It is characterized in that it is provided with a via plug formed in an opening around which a second insulating film is formed by growing Al or an Al alloy from the exposed lower metal wiring.

Further, it is desirable that the lower metal wiring is made of a conductive material containing Al or Al alloy.

In order to solve the above problems, the manufacturing method according to the present invention includes a first step of forming a first insulating film on a surface of a substrate including a lower layer metal wiring, and a first insulating film. Second step of forming an opening by exposing a lower layer metal wiring by etching away a predetermined position of the second step, and forming a second insulating film on the first insulating film having the opening formed therein. And a fourth step of removing the second insulating film formed on the bottom surface of the opening, and Al or Al by the CVD method in the opening.
A fifth step of depositing an alloy to form a via plug.

[0011]

According to the above construction, since the second insulating film is further formed on the inner peripheral surface of the opening, the deposit containing metal adhered to the inner peripheral surface is not exposed. For this reason, it is possible to prevent the metal from being deposited from the inner peripheral surface, so that the shape of the via plug in the multilayer wiring structure is not deformed.

Further, according to the above manufacturing method, after forming the opening in the first insulating film, the second insulating film is formed on the inner peripheral surface of the opening.
Since the second insulating film is formed by forming the insulating film as the via hole, the deposit adhered to the inner peripheral surface of the opening when forming the opening in the first insulating film can be covered with the second insulating film. For this reason, it is possible to prevent metal from being deposited from the inner peripheral surface, so that the shape of the via plug in the multilayer wiring structure is not deformed. Further, if the second insulating film is formed on the inner peripheral surface of the opening, the mask edge does not enter the inside of the via hole even if the mask for forming the upper metal wiring is slightly displaced. As a result, the Al or Al alloy forming the via plug is not etched.

[0013]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. In the semiconductor device according to the first example, the base insulating film 20 is formed on the Si substrate 10, and the lower metal wiring 30 made of the Al alloy film 31 is formed on the base insulating film 20. An interlayer insulating film 40, which is a first insulating film, is formed on the underlying insulating film 20 on which the lower layer metal wiring 30 is formed. A via hole 50 is formed in the interlayer insulating film 40, and a via film 51, which is a second insulating film made of SiO ₂ , is formed around the inner peripheral surface of the via hole 50. Further, a via plug 52 made of Al is provided inside the via film 51. Then, an upper metal wiring 60 is formed on the upper surface of the interlayer insulating film 40. The upper layer metal wiring 60 and the lower layer metal wiring 30 are electrically connected by a via plug 52. Like the lower layer metal wiring 30, the upper layer metal wiring 60 is formed of an Al alloy film. The Al alloy used at this time is Cu
0.5% by weight, but regardless of this, those used for the upper layer metal wiring 60 and the lower layer metal wiring 30
It may be an alloy having the same composition as that used for the above, or an alloy having a different composition.

Incidentally, structures necessary for a semiconductor device such as a diffusion layer and a gate electrode are formed in and on the surface of the Si substrate 10. A contact hole exists at a required position of the base insulating film 20, and a contact structure for connecting the lower metal wiring 30 and the diffusion layer or the gate electrode or other structure is formed. Further, a new interlayer insulating film 40 and a new metal wiring are formed on the upper metal wiring 60, respectively.
Layers or more can be laminated. A method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to the flowchart of FIG. 2 and FIGS. First, as shown in FIG. 3A, a base insulating film 20 is formed on the surface of a Si substrate 10, and an Al alloy is deposited on the base insulating film 20 to a thickness of 300 to 800 nm by a sputtering method. The alloy film 31 is formed (step 201). Next, the Al alloy film 31 is processed into a predetermined wiring pattern to form the lower layer metal wiring 3
0 is formed (step 202). To form the wiring pattern, after forming a resist pattern using an exposure device,
It is performed by RIE using a chlorine-based gas. At this time, if the line width is 1.0 μm or less, it is a metal film.
Since the precise formation of the resist pattern becomes difficult due to the influence of the exposure light reflected from the Al alloy surface, Si is further deposited on the lower metal wiring 30 by the sputtering method to a thickness of 20 to 80 nm to form a Si film. However, it is desirable to adopt a method of reducing the reflectance with respect to the exposure light. This Si film may be removed by, for example, plasma etching using a fluorine-based gas after etching the metal film and removing the resist.

Next, as shown in FIG. 3B, the interlayer insulating film 4 is formed on the base insulating film 20 on which the lower metal wiring 30 is formed.
0 is formed (step 203). This interlayer insulating film 40
Is formed by depositing SiO ₂ with a film thickness of 300 nm by the plasma CVD method to form a SiO ₂ film, and SOG in the flat portion.
It is formed by applying it to a thickness of 300 nm to form an SOG film and performing heat treatment at a necessary temperature. After that, SiO ₂ is deposited again to a film thickness of 200 nm by the plasma CVD method to form a SiO ₂ film. The method for forming the interlayer insulating film 40 on a finer LSI having a line width of about 0.6 μm or less is as follows. That is, tetraethoxysilane (hereinafter referred to as TEOS) and oxygen to form a SiO ₂ film having a film thickness of 100nm is deposited SiO ₂ by plasma CVD using a raw material, further on this SiO ₂ film, TEOS and ozone SiO ₂ is deposited by the atmospheric pressure CVD method using and as raw materials to form a 1.6 μm thick SiO ₂ film. Then, etch back is performed until the thickness of the SiO ₂ film of the flat portion after a resist is applied to the SiO ₂ film is 700 nm, SiO film thickness 100nm again by the plasma CVD method
₂ is deposited.

Next, a photomask is set on the interlayer insulating film 40, a resist pattern is formed using an exposure device, and then RIE using a fluorine-based gas is performed, as shown in FIG.
As shown in (c), a via hole 50 is formed at a predetermined position in the interlayer insulating film 40 (step 204). Next, FIG.
As shown in (a), SiO ₂ is deposited by a plasma CVD method using TEOS and oxygen as raw materials to form an insulating film having a film thickness of 50 nm (step 205). Further, at this time, as the film thickness of the insulating film 51a on the inner peripheral surface increases, the diameter of the portion where the via plug 52 is embedded decreases.
It is desirable that the insulating film 51a be as thin as possible.

Next, the insulating film 51a on the surface of the interlayer insulating film 40 and at the bottom of the via hole 50 is removed by RIE, leaving the insulating film 51a only on the inner peripheral surface as shown in FIG. 4B, and the via film 51b. Are formed (step 206). This via film covers particularly metallic deposits such as Al attached to the inner peripheral surface.

Although the insulating film formed on the surface of the interlayer insulating film is removed in this embodiment, it is not always necessary to remove this insulating film.

Next, the lower metal wiring 3 exposed at the bottom of the via hole 50 by plasma etching using a chlorine-based gas.
0 (Al alloy film) cleaning treatment (step 20)
7). This process is performed because contaminants, an alumina film, or the like adheres to the surface of the lower-layer metal wiring 30 exposed at the bottom of the via hole 50 when the insulating film is RIEed and when exposed to the air after the RIE. , These contaminants and alumina film are CVD
This is because it needs to be removed because it inhibits Al deposition in the method.

Next, CV using DMAH and hydrogen as raw materials
By selectively depositing Al only in the via hole 50 by the D method, the via plug 52 is formed as shown in FIG. 4C (step 208). At this time, Al is deposited only from the surface of the upper metal wiring 60 (Al alloy film) exposed on the bottom surface of the via hole 50, and is not deposited from the via film surface on the inner peripheral surface of the via hole 50. This is step 20
This is because the via film formed in 6 covers the contaminants and the inner peripheral surface has no contaminants. Therefore, the shape does not change when the via plug is formed.

It is also possible to use a selective deposition other than the CVD method, for example, a plating method for forming the plug.

Next, Al is sputtered to 400 to 1000 nm.
4 is formed by depositing an Al alloy film having a thickness of 10 μm and forming the Al alloy film, and using the same method as that for forming the lower layer metal wiring 30 described above.
As shown in (d), an upper metal wiring 60 is formed to manufacture a semiconductor device having a multilayer wiring structure (step 209).
Here, even if the mask used for forming the upper-layer metal wiring 60 is slightly displaced, the via plugs are corroded to generate voids, and chlorine used for Al etching and Al corrosion due to residual water such as water during cleaning. It does not cause this is,
This is because the insulating film is formed on the inner peripheral surface, so that the via plug is not etched even if the mask is slightly displaced as shown in FIG.

When the upper metal wiring 60 is formed, when an Al alloy film is deposited by using an apparatus different from that used for forming the via plug 52, Ar ions or the like are added immediately before the deposition. It is necessary to remove the alumina film formed on the surface of the via plug 52 by performing the sputter etching used to obtain good electrical contact.

After forming the via plug 52, if the upper layer metal wiring 60 is formed by depositing an Al alloy film without taking it out into the atmosphere, in this case, the via plug 5 is formed.
Since no alumina film is formed on the surface 2, better electrical contact can be obtained.

[0026]

As described in detail above, the present invention is
After forming the via hole in the first insulating film, the second insulating film is further formed on the inner peripheral surface of the via hole, so that the adhered matter such as metal particles adhered to the inner peripheral surface is covered and hidden. Never exposed to. Therefore, it is possible to prevent metal deposition from the inner peripheral surface. Therefore, since Al or Al alloy is deposited only from the bottom surface of the via hole, the shape of the via plug is not deformed, and the reliability of the via metal structure or the upper layer metal wiring formed on the upper surface of the via plug can be maintained. Further, the second insulating film formed on the inner peripheral surface prevents the mask edge from entering the inside of the via hole even if the mask for forming the upper layer metal wiring is slightly displaced. Therefore, the Al or Al alloy forming the via plug is not etched, and no void is formed in the via hole. Further, it is possible to prevent chlorine used for Al etching when forming the upper-layer metal wiring and Al corrosion of the via plug due to water content during cleaning.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment.

FIG. 2 is a flowchart showing a manufacturing process of the semiconductor device according to the present embodiment.

FIG. 3 is a diagram showing each manufacturing process of the semiconductor device according to the embodiment.

FIG. 4 is a diagram showing each manufacturing process of the semiconductor device according to the embodiment.

FIG. 5 is an explanatory diagram of a semiconductor device according to this embodiment.

FIG. 6 is a diagram showing each manufacturing process of a conventional semiconductor device.

FIG. 7 is a diagram showing each manufacturing process of a conventional semiconductor device.

FIG. 8 is an explanatory diagram of a conventional semiconductor device.

[Explanation of symbols]

10 ... Si substrate, 20 ... Base insulating film, 30 ... Lower layer metal wiring, 40 ... Interlayer insulating film, 50 ... Via hole, 51 ... Via film, 52 ... Via plug, 60 ... Upper layer metal wiring.

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location // H01L 21/28 A 9055-4M

Claims (3)

[Claims] 1. A lower-layer metal wiring formed on a substrate, a first insulating film formed on a surface including the lower-layer metal wiring, and a predetermined position of the first insulating film is removed by etching. An opening formed by exposing the lower metal wiring, a second insulating film provided around the inner peripheral surface of the opening, and Al or an Al alloy grown from the exposed lower metal wiring. Thus, the semiconductor device having a multilayer wiring structure is provided with a via plug formed in the opening around which the second insulating film is provided. 2. The semiconductor device having a multilayer wiring structure according to claim 1, wherein the lower layer metal wiring is made of a conductive material containing Al or an Al alloy. 3. A first step of forming a first insulating film on a surface including a lower metal wiring on a substrate, and a predetermined position of the first insulating film is removed by etching to expose the lower metal wiring. A second step of forming an opening by doing so, a third step of forming a second insulating film on the first insulating film in which the opening is formed, and a bottom surface of the opening. It has a fourth step of removing the formed second insulating film and a fifth step of forming a via plug by depositing Al or an Al alloy in the opening by a CVD method. A method of manufacturing a semiconductor device having a multilayer wiring structure.