JPH06163659A - Integrated circuit chip i/o circuit - Google Patents

Abstract

PURPOSE:To enable probe test even in an integrated circuit chip where the pitch becomes narrow by the increase of the number of bonding pads. CONSTITUTION:A bonding pad 14 and an input buffer 16a are provided in the integrated circuit chip region on a semiconductor wafer. A boundary scan resistor 12a is provided in a scribe line region, corresponding to the bonding pad 14. As against a total of four boundary scan resistors 12a, a probe pad 10 used for an shift data input Sli and a probe bad 10 used for the input of a clock signal CK are provided in the scribe line region. Access becomes possible with fewer probe pads 10 by operating a plurality of boundary scan resistors 12a as shift resistors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a probe test of an integrated circuit chip, and more particularly to the probe test even for an integrated circuit chip having a narrow bonding pad due to an increase in the number of bonding pads. Integrated circuit chip input / output circuit capable of enabling

[0002]

2. Description of the Related Art Integrating an electronic device into an integrated circuit has many advantages such as miniaturization of the entire device, improvement of reliability and reduction of power consumption. Also, integrated circuits based on various design techniques are provided. For example, there are integrated circuits based on various design techniques designed to reduce the design man-hours and design costs associated with the design of integrated circuits. For example, there is an integrated circuit in which at least a part of the design process or the manufacturing process is shared and prepared in advance, and the other processes are customized.

Conventionally, there are various types of package forms of integrated circuits provided to users. First, as a mounting type package, QFP (quad flat package)
) Package and PLCC (plastic leaded chip car)
carrier package and PGA (pin grid array) package. Also, as an insert type package, DI
There are P (dual in line package) packages and PGA packages. Also, there are various pin counts of integrated circuit packages. For example, the number of pins of the DIP package of the insertion type package is about several tens of pins. On the other hand, some integrated circuits of the PGA package have a pin number of several hundred pins.

On the other hand, in order to reduce the manufacturing cost of the integrated circuit, it is practiced to test the integrated circuit of the product at a relatively early stage of the manufacturing process and remove the defective product. By removing defective products at an early stage of the manufacturing process, unnecessary work in subsequent processes can be reduced. For example, the operation of each integrated circuit chip is tested by a probe test before the dicing process of dividing a large number of integrated circuit chips on a semiconductor wafer along a predetermined scribe line using a dicing saw or the like. Has been done.

In this probe test, a large number of probe pins provided on a probe card are brought into contact with a bonding pad used for connection with the outside of the integrated circuit chip, and the inside of the integrated circuit chip is passed through these probe pins. The operation of the circuit is tested. In such a probe test, the probe card is positioned for each of a large number of integrated circuit chips on a semiconductor wafer, and each probe pin is positioned so as to come into contact with the corresponding bonding pad.

[0006]

However, in the probe card used for the probe test as described above, there is a limit to the narrowing of the pitch of the probe pins. As described above, the number of pins of the package of the integrated circuit has increased significantly as the electronic devices have been integrated into a circuit, and the number of pins of hundreds of pins, like the integrated circuit of the PGA package described above. There is also. Thus, as the number of pins on the package increases, the bonding pads on the integrated circuit chip also have a narrower pitch. For this reason, it becomes difficult for the probe pins to contact the bonding pads having a narrow pitch. Therefore, there is a problem that it becomes difficult to perform a probe test, which has many advantages such as a reduction in manufacturing cost of an integrated circuit.

The present invention has been made to solve the above-mentioned conventional problems, and the probe test is performed even on an integrated circuit chip having a narrow pitch of bonding pads due to an increase in the number of bonding pads. It is an object to provide an integrated circuit chip input / output circuit that can be enabled.

[0008]

SUMMARY OF THE INVENTION The present invention is a wafer
Provided in the scribe line area between integrated circuit chips,
Among the bonding pads on the integrated circuit chip, a plurality of boundary scan registers provided corresponding to those used for inputting / outputting signals and a plurality of the boundary scan registers are operated as a shift register for accessing. By providing the probe pads having a pitch wider than that of the bonding pads, the above-mentioned object is achieved.

In the integrated circuit chip input / output circuit, at least one of the boundary scan register and the probe pad is shared with respect to the integrated circuit chip input / output circuit of each adjacent integrated circuit chip. As a result, the above-mentioned problems can be achieved, the integration degree of the integrated circuit chip input / output circuit on the wafer can be improved, and the present invention can be applied to the relatively narrow scribe line region.

In the integrated circuit chip input / output circuit, the integrated circuit chip is a semi-custom integrated circuit chip, wiring to the bonding pad for input and bonding to the bonding pad for output are provided. Wiring is provided together with the semi-custom integrated circuit chip side, and in the design of the customized circuit portion in the semi-custom integrated circuit chip, the boundary scan register is used for input or output. By being able to determine whether to use or not, the above-mentioned problems can be achieved and the present invention can be applied to a semi-custom integrated circuit chip.

[0011]

It is more difficult to narrow the pitch of the probe pins used for the probe test, as compared with the narrowing of the pitch of the bonding pad when connecting to the outside of the integrated circuit such as wire bonding. For example, the wire used for wire bonding may have a certain degree of tensile strength. In comparison with this, the probe pin must have a predetermined rigidity in order to bring its tip into contact with a desired bonding pad and to maintain this contact state,
There is an inevitable limit to reducing the thickness. or,
Even when a large number of such probe pins are attached to the probe card, there is a limit to narrowing the pitch.

In view of the above points, the present invention makes effective use of the scribe line region cut out during the dicing as described above, and provides the probe pad dedicated to the probe test in the scribe line region. It was made based on the viewpoint.

Further, the present invention has been made to find out a structure capable of further expanding the pitch of the probe pads. In particular, during the probe test through the probe pad, compared to the bonding pad,
The present invention was made by finding a configuration that enables input / output access using the probe pads of which the number is small.

That is, according to the present invention, the scribe line region is provided with a plurality of boundary scan registers used when accessing through the probe pad. When accessing the plurality of boundary scan registers via the probe pad, the plurality of boundary scan registers are operated as shift registers. That is, the access from the probe pad is a serial access to the boundary scan register which is a shift register.

Therefore, it is possible to access a plurality of the boundary scan registers more than the number of the probe pads provided, and as a result, it is possible to access more than the number of the probe pads corresponding to the plurality of boundary scan registers. Input / output from the bonding pad can be accessed.

As described above, according to the present invention, by effectively utilizing the scribe line region, it is possible to avoid a decrease in the degree of integration on the integrated circuit chip. or,
It is possible to further expand the pitch of the probe pins used for the probe test, and to make the probe test possible even for an integrated circuit chip that has been difficult to perform the probe test in the past because the bonding pad has a narrow pitch. You can

[0017]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of the vicinity of a bonding pad on a semiconductor wafer according to the first embodiment of the present invention.

In FIG. 1, an input / output buffer 16a and a bonding pad 14 connected to the input of the input / output buffer are formed in the integrated circuit chip area on the semiconductor wafer. The integrated circuit chip area is an area in which a desired circuit to be incorporated in the integrated circuit is formed, and is almost the same as a conventional one.

On the other hand, a boundary scan register 12a and a probe pad 10 are provided in the scribe line area on the left side of the bonding pad 14.
The boundary scan register 12a is provided corresponding to each of the bonding pads 14. Also, each output Q of the boundary scan register 12a
Are connected to the bonding pad 14.

Further, the boundary scan register 12
Four a's are cascade-connected with respect to each input D and output Q, and are also configured as shift registers. The input D of the uppermost one of these four boundary scan registers 12a
The probe pad 10 is connected to. The probe pad 10 connected to the input D receives the shift data input SIi (i = 1, 2, ...) When accessing from the outside of the integrated circuit chip in the probe test.
・ ・)

Further, the boundary scan register 12
a is a unit of four, and all the clock inputs CK thereof are connected in parallel and are connected to one probe pad 10. The probe pad 10 connected to the clock input CK is used as the clock signal CKi when accessing the integrated circuit chip in the probe test.

As described above, the probe pad 10 is
Two pieces are provided for each of the four boundary scan registers 12a arranged adjacent to each other. As described above, one of the two probe pads 10 is used as the shift data input SIi as described above, and the other is used as the clock signal CKi as described above.

Therefore, in this embodiment, the boundary scan register 1 is provided for each of the bonding pads 14 of the integrated circuit chip which is the subject of the probe test.
By arranging 2a one by one and providing two probe pads 10 for every four adjacent boundary scan registers 12a, the probe to be contacted and accessed by the probe pin during the probe test. The pad pitch can be expanded. That is, compared to the pitch of the bonding pads 14, the probe pads 1 contacted and accessed by the probe pins
The pitch of 0 is expanded to almost twice the interval.

FIG. 2 is a circuit diagram of the boundary scan register used in the first embodiment.

As shown in FIG. 2, the boundary scan register 12a shown in FIG. 1 is composed of a flip-flop FF, a transfer gate 44, and a bus holder 46.

The flip-flop FF is a general master-slave type D-type flip-flop.
The flip-flop FF takes in and holds the input to the input D at the rising edge of the clock CK, and outputs this to the output Q.
Is output as.

The transfer gate 44 has a gate input and a negative logic gate input, and performs an on / off operation. In FIG. 2, when the gate signal E input to the gate input is in the H state and the gate signal E bar input to the negative logic gate input is in the L state, the output Q of the flip-flop FF outputs the boundary. It is output as the output of the scan register 12a.

In the bus holder 46, when the transfer gate 44 is turned off, the output of the boundary scan register 12a is in a high impedance state, so that the input of the input buffer 16a of the integrated circuit chip is changed. It is provided to prevent instability. The bus holder 46 holds the input of the input buffer 16a in the logic state when the transfer gate 44 is turned off when the transfer gate 44 is turned off.

FIG. 3 is a time chart showing the operation of the integrated circuit chip input / output circuit used in the first embodiment.

In the time chart of FIG. 3, the shift data input SI1 described above with reference to FIG. 1 is used.
And a time chart of the clock signal CK1 and respective outputs Wa to Wd of the four input buffers 16a in total. In addition, in FIG. 3, Ba to B
f is bit data sequentially input from the shift data input SI1.

In the following description, the boundary scan register 12a whose input D is directly connected to the shift data input SI1 will be referred to as a first boundary scan register. The boundary scan register 12a in which the input D is connected to the output Q of the first boundary scan register is called a second boundary scan register. Further, the output Q of the second boundary scan register is connected to the input D of the boundary scan register 12a.
Is referred to as a third boundary scan register. Similarly, the one connected to this is referred to as a fourth boundary scan register.

In the time chart of FIG. 3, first, at time t ₁ , the bit data Ba input as the first data from the shift data input SI1 at the rising edge of the clock signal CK1 First
Capture in boundary scan register. Output Wa of the input buffer 16a which is connected to the output Q of the first boundary scan registers, by the time t _2, the outputs of the bit data Ba.

Next, at time t ₃ , at the next rise of the clock signal CK1, the second bit data Bb input to the shift data input SI1 is taken into the first boundary scan register. Be done.
Further, at the time t _3, the output Q of the first boundary scan register, i.e. the bit data Ba is taken to the second boundary scan register. After this, by time t ₄ , the output Wa and the output W
b becomes the bit data Bb and the bit data Ba, respectively.

Next, at time t ₅ , at the next rising edge of the clock signal CK1, the third bit data Bc input to the shift data input SI1 changes to the first bit data Bc.
It is taken into the boundary scan register. The time t
_{In 5} , the output Q of the first boundary scan register, that is, the bit data Bb is taken into the second boundary scan register. Also, the time
At t ₅ , the output Q of the second boundary scan register, that is, the bit data Ba is taken into the third boundary scan register. Thereafter, until the time t _6, the output Wa ～Wd, respectively, serving as the bit data Bc ~Ba.

Next, at time t ₇ , at the next rise of the clock signal CK1, the fourth bit data Bd input from the shift data input SI1 is taken into the first boundary scan register. . Further, at the time t ₇ , the output Q of the first boundary scan register, that is, the bit data Bc is taken into the second boundary scan register. The output of the second boundary scan register, that is, the bit data Bb is taken into the third boundary scan register. In the time t _7, the output Q of the third boundary scan register, i.e. the bit data Ba is incorporated into the fourth boundary scan register. After this, by the time t _8, the output W
a to Wd become the bit data Bd to Ba, respectively.

At the time t ₈ , the first boundary scan register to the fourth boundary scan register are respectively set to the bit data Bd to Ba.
Is held and the outputs Wa to Wd are determined correspondingly, the actual probe test can be performed based on this.

As described above, according to the first embodiment, the bonding pad 1 on the integrated circuit chip is used.
It is possible to arrange the probe pad 10 having a pitch larger than that of No. 4 and perform the probe test using the probe pad 10. Therefore, it is possible to use a relatively thick probe pin. Also, the pin pitch of the probe pins on the probe card can be increased. Therefore, the probe test can be performed more easily.

FIG. 4 is a circuit diagram in the vicinity of the bonding pad of the semiconductor wafer of the second embodiment to which the present invention is applied.

In FIG. 4, the output buffer 16b and the bonding pad 14 are provided in the integrated circuit chip area. On the other hand, the flip-flop FF, the boundary scan register 12b, and the probe pad 10 are provided in the scribe line region.

The flip-flop FF and the boundary scan register 12b are the output buffer 16
It is provided for each one of b and each of the bonding pads 14.

Also, three boundary scan registers 12b are used in combination with one flip-flop FF. That is, the flip-flop F
The output Q of F is connected to the shift input SI of the boundary scan register 12b of the next stage. Or later,
The boundary scan register 12b is referred to as a second boundary scan register. Further, the flip-flop FF is hereinafter referred to as a first boundary scan register. The output Q of the second boundary scan register 12b is connected to the shift input SI of the boundary scan register 12b of the next stage.
Hereinafter, the boundary scan register 12b will be referred to as a third boundary scan register. Similarly, the boundary scan register 12b at the next stage is connected to the third boundary scan register. Hereinafter, the boundary scan register 12b will be referred to as a fourth boundary scan register.

Further, one of the flip-flops FF and 3 is provided.
For each of the boundary scan registers 12b,
A total of two probe pads 10 are provided. To one probe pad 10, all the respective clock inputs CK of the one flip-flop FF and the three boundary scan registers 12b are connected in parallel. The probe pad 10 is used to input the clock signal CK1. The other probe pad 10 is connected to the output Q of the fourth boundary scan register. The probe pad 10 is used as a shift data output SO1.

FIG. 5 is a circuit diagram of the boundary scan register used in the second embodiment.

In FIG. 5, there is shown a circuit diagram of the boundary scan register 12b shown in FIG. The boundary scan register 12b is composed of a multiplexer 30 and a flip-flop FF.

The multiplexer 30 is connected to the outputs Q of the preceding first to third boundary scan registers. Meanwhile, the other input of the multiplexer is
The corresponding bonding pad 14 and the corresponding output buffer 16b are connected. The multiplexer 30 connects the input SI to the input D of the flip-flop FF when the shift selection signal SS is in the H state. Also, the multiplexer 30 connects the input D to the input D of the flip-flop FF when the shift selection signal SS is in the L state.

The flip-flop FF takes in what is input to its input D at the rising edge of its clock input CK, holds it, and outputs it as an output Q. The flip-flop FF is a general master-slave type D-type flip-flop.

FIG. 6 is a time chart showing the operation of the integrated circuit chip input / output circuit used in this embodiment.

In FIG. 6, the clock signal C
A time chart of K1 and the shift data output SO1 is shown. Further, in describing the time chart of FIG. 6, it is assumed that bit data Ba to Bd are recorded in the first boundary scan register to the fourth boundary scan register, respectively.

In FIG. 6, first, before the time t ₁ , as the shift data output SO1,
The bit data Bd stored in the fourth boundary scan register is output.

At the time t ₁ , when the clock signal CK1 rises, the bit data Bc stored in the third boundary scan register is changed to the fourth bit data Bc.
It is taken into the boundary scan register. After this,
By the time t _2, the said shift data output SO1 is determined in the bit data Bc. At the time t ₁ , the bit data Ba stored in the first boundary scan register is taken in the second boundary scan register. The bit data Bb stored in the second boundary scan register 12b is taken into the third boundary scan register.

[0052] Thereafter, likewise, in the time t ₃ ~ time t _6, in accordance with the rise of the clock signal CK1, the bit data Bb and Ba is the shift data output SO
It is output from 1. Further, at the time instant t _6, so that the finally all the bit data Ba ～Bd is read.

As described above, according to the second embodiment particularly applied to the output buffer, the bonding pad 14 on the integrated circuit chip area is formed in the same manner as the first embodiment applied to the input buffer. The probe pad 10 having a pitch larger than the pitch can be provided in the scribe line region, and the probe test can be performed more easily.

FIG. 7 shows a third embodiment to which the present invention is applied.
It is a partially expanded top view of the semiconductor wafer of 5th Example.

FIG. 7 shows a partially enlarged plan view of a semiconductor wafer in which a large number of semi-custom type (gate array type) integrated circuit chips are formed. In particular, in FIG. 7, one integrated circuit chip 1 out of many integrated circuit chips provided on the semiconductor wafer.
A plan view near a is shown. Further, in FIG. 7, a part of the integrated circuit chips 1b to 1i is also shown.
A scribe line region is provided between the integrated circuit chips 1a-1i. In the scribe line region, an integrated circuit chip input / output circuit to which the present invention is applied is built in a hatched portion. Particularly, in the third embodiment and the fourth embodiment, the integrated circuit chip input / output circuit for the integrated circuit chip 1a is provided in the upper right diagonal line portion. On the other hand, the integrated circuit chip input / output circuits for the other integrated circuit chips 1b to 1i are provided in the diagonally right downward line.

FIG. 8 is an enlarged plan view of the vicinity of the bonding pads and probe pads of the third and fourth embodiments.

In FIG. 8, 13 bonding pads 14 and 7 probe pads 10 are shown. As shown by the broken lines in FIG. 8, a total of six bonding pads 14 and a total of three probe pads 10 are combined. These total 3
The probe pads are used for inputting and outputting a signal from the probe pin to the clock signal CK, the shift input SI, and the shift output SO.

The alternate long and short dash line in FIG. 8 is the boundary between the integrated circuit chip area and the scribe line area on the semiconductor wafer. That is, the left side of the one-dot chain line is the integrated circuit chip area. On the other hand, the right side of the one-dot chain line is the scribe line area. In the scribe line region, an integrated circuit chip input / output circuit to which the present invention is applied is built in a layer lower than the probe pad 10.

FIG. 9 is a circuit diagram of an integrated circuit chip input / output circuit used in the third embodiment.

In FIG. 9, a total of 6 pairs are set.
A set of integrated circuit chip input / output circuits corresponding to one of the bonding pads 14 is shown. The integrated circuit chip input / output circuit has a total of six chip input / output circuit portions separated by broken lines in the range shown in FIG. The alternate long and short dash line in FIG. 9 is the boundary between the integrated circuit chip area on the left side and the scribe line area on the right side. The same chip input / output circuit portion is provided in the scribe line region for each of the bonding pads 14. In this embodiment, a total of six chip input / output circuit portions are connected as a set and are cascade-connected to operate as a shift register as needed.

Each of the chip input / output circuit parts is composed of a multiplexer 30 and a flip-flop FF. The chip input / output circuit portion includes the bonding pad 14 connected to the input buffer, the bonding pad 14 connected to the output buffer, and further the bonding pad 14 connected to the bidirectional buffer. Can respond.

The connection between the chip input / output circuit portion and the bonding pad 14 is via the terminal TO or the terminal TI. When the bonding pad 14 is connected to the input buffer, the bonding pad 14 is connected to the chip input / output circuit portion at the terminal TI. When the bonding pad 14 is connected to the output buffer, the bonding pad 14 is connected to the chip input / output circuit portion at the terminal TO. If the bonding pad 14 is connected to a bidirectional buffer, the bonding pad 14
Is connected to the chip input / output circuit portion using both the terminal TI and the terminal TO.

The above-mentioned bonding buffer 1 can be used for the input buffer, the output buffer and the bidirectional buffer.
4 and the chip input / output circuit portion are changed by changing the circuit formed on the integrated circuit chip area side. When the bonding pad 14 is connected to the input buffer, the transfer gate 4 is provided between the bonding pad 14 and the terminal TI.
4 and a bus holder 46 are provided. When the bonding pad 14 is connected to the output buffer, the bonding pad 14 and the terminal TO are connected. When the bonding pad 14 is connected to the bidirectional buffer, the connection to the terminal TI is made as in the case of the input buffer as described above, and further the output buffer described above is further connected. Similar to the case of, the connection to the terminal TO is also made.

Such a total of six chip input / output circuit portions are each provided with one input of the multiplexer provided therein and the flip-flop FF provided therein.
The output Q of is connected in cascade. Therefore, the shift selection signal SS is set to the H state, and the multiplexers 30 included in the respective chip input / output circuit parts are provided.
By switching, every time the clock signal CK rises,
Bit data to a total of six flip-flops FF can be sequentially input and taken in sequentially from the shift input SI. Also, the bit data captured in this way is
The bonding pad 14 connected to the input buffer or the bidirectional buffer can be output from the corresponding output Q of the flip-flop FF.
The timing of this output is the gate signals E and E to be input to the transfer gates 44 provided for each.
The bars can be synchronized with each other.

On the other hand, by setting the shift selection signal SS to the L state, the logic state of the bonding pad 14 connected to the output buffer or the bidirectional buffer is changed to the logical state of the bonding pad 14 via the terminal TO and the multiplexer 30. It can be taken into the flip-flop FF.
In addition, the shift selection signal SS is brought into the L state, and the logical state taken in the flip-flop FF in this manner shifts the shift selection signal SS into the H state to shift a total of six flip-flops FF. It can be operated as a register and can be sequentially output as the shift output SO at each rising of the clock signal CK.

FIG. 10 is a circuit diagram of the chip input / output circuit portion used in the third embodiment.

As shown in FIG. 10, one input of the multiplexer 30 is connected to the output Q of the preceding flip-flop FF. This input of the multiplexer 30 is connected to the input D of the flip-flop FF when the shift selection signal SS goes high. On the other hand, the other input of the multiplexer 30 is
Via the terminal TO, the bonding pad 14
Are connected. This input of the multiplexer 30 is connected to the input D of the flip-flop FF when the shift selection signal SS is in the L state. The bonding pad 1 to this input of the multiplexer 30
The connection from 4 is only when an output buffer or a bidirectional buffer is connected to the bonding pad 14.

In the chip input / output circuit portion shown in FIG. 10, the output of the multiplexer 30 is connected to the input D of the flip-flop FF. The output Q of the flip-flop FF is connected to one input of the multiplexer 30 in the chip input / output circuit portion of the next stage. Also, the flip-flop FF
Output Q is connected to the bonding pad 14 via the terminal TI, the transfer gate 44, and the bus holder 46. The connection to the bonding pad 14 is made when the bonding pad 14 is connected to the input buffer or the bidirectional buffer.

The transfer gate 44 and the bus holder 46 are formed on the base of the integrated circuit chip area, and when the bonding pad 14 is connected to the input buffer or the bidirectional buffer as described above, The wiring from the terminal TI to the bonding pad 14 is set.

As described above, according to the third embodiment, the pitch of the probe pads 10 can be increased even in the integrated circuit chip having the bonding pads 14 having a narrow pitch, which is easier to perform. In addition, the probe test can be enabled. Further, in the integrated circuit chip input / output circuit of the third embodiment, each of the chip input / output circuit portions has the bonding pad connected to the output buffer as well as the bonding pad 14 connected to the input buffer. 14 and the bonding pad 14 connected to the bidirectional buffer are the same.

Therefore, in the case where the integrated circuit chip of this embodiment is of the gate array type as described above, such an integrated circuit chip input / output circuit is built in the base thereof and a plurality of types of integrated circuits are integrated. It can be shared with the circuit chip. In other words, according to whether each of the bonding pads 14 is connected to the input buffer, the output buffer, or the bidirectional buffer, the wiring is customized only. The bonding pad 14 and the terminal TO or the terminal TI can be connected.

FIG. 11 is a circuit diagram of a chip input / output circuit portion used in the fourth embodiment.

The chip input / output circuit portion of the fourth embodiment shown in FIG. 11 is a modification of the third embodiment shown in FIGS. 9 and 10.

That is, in the fourth embodiment, the transfer gate 44 and the bus holder 46 built in the integrated circuit chip area in the third embodiment are located on the right side of the one-dot chain line, that is, the scribe line area. It is built in.

Therefore, also in the fourth embodiment, the chip input / output circuit portion formed in the scribe line region is connected to the output buffer also to the bonding pad connected to the input buffer. The same can be applied to the bonding pad 14 and also to the bonding pad 14 connected to the bidirectional buffer. In the fourth embodiment,
When the bonding pad 14 is connected to the input buffer, the bonding pad 14 is connected to the terminal T.
I is connected to I by, for example, a customized wiring.
If it is connected to an output buffer, the bonding pad 14 is connected to the terminal TO by, for example, a customized wiring. Also, in the case of a bidirectional buffer, such wiring to the terminal TO and the terminal TI is performed together.

Also in the fourth embodiment as described above, the same effect as that of the above-mentioned third embodiment can be obtained. In particular, when the scribe line region has an area allowance, the transfer gate 44 and the bus holder 46 are formed in the scribe line region as in the fourth embodiment, so that the integrated circuit chip region is integrated. The degree can be improved.

FIG. 12 is an enlarged plan view of an integrated circuit chip input / output circuit used in the semiconductor wafer of the fifth embodiment.

In FIG. 12, the fifth main circuit formed in the scribe line region between the region of the integrated circuit chip 1a shown in FIG. 7 and the region of the integrated circuit chip 1c. An enlarged plan view of an integrated circuit chip input circuit used in the example is shown.

The integrated circuit chip input / output circuit used in this embodiment is shared by adjacent integrated circuit chips. For example, the integrated circuit chip input / output circuit built in the scribe line region shown in FIG. 12 is also used for the integrated circuit chip 1a, and
It is also used for the integrated circuit chip 1c. Such an integrated circuit chip input / output circuit is built in the lower layer of the scribe line region where the plurality of probe pads 10 of FIG. 12 are provided.

In the integrated circuit chip input / output circuit of this embodiment, one integrated circuit chip has a total of eight bonding pads and the other integrated circuit chip has a total of eight bonding pads. And the probe pads 10 are provided in total.

FIG. 13 is a circuit diagram of the chip input / output circuit portion of the integrated circuit chip input / output circuit used in the fifth embodiment.

In this embodiment, a total of eight chip input / output circuit portions 50 shown in FIG. 13 constitute one set, and a total of eight bonding pads 1 of one integrated circuit chip.
It is provided for a total of 16 bonding pads 14 of 4 and the other 8 bonding pads 14 in total.

The chip input / output circuit portion 50 of the fifth embodiment shown in FIG. 13 is different from that of the fourth embodiment shown in FIG. 11 in that it uses the multiplexer 30a and each integrated circuit. The connection portions of the chip regions to the bonding pads 14 are different. That is, the multiplexer 30 used in the fifth embodiment.
a is to select any one of the three inputs and output it. Also, the multiplexer 30a
Uses the shift selection signal SS and the chip selection signal CS. That is, when the shift selection signal SS is in the H state, the multiplexer 30a selects the input a and outputs it. When the shift selection signal SS is in the L state, the multiplexer 30a selects either the input b 1 or the input c 2 according to the chip selection signal CS and outputs it. The chip selection signal C
When S is in the H state, the input b is selected. on the other hand,
When the chip selection signal CS is in the L state, the multiplexer 30a selects the input c and outputs it.

Also, in the fifth embodiment, the input a of the multiplexer 30a is connected to the output Q of the flip-flop FF in the preceding stage. The input b of the multiplexer 30a is connected to the terminal TO on the left integrated circuit chip side. The input c of the multiplexer 30a is connected to the terminal TO on the right side integrated circuit chip side. A left terminal TI and a right terminal TI are connected to the transfer gate 44 together with the bus holder 46.

The integrated circuit chip input / output circuit of the fifth embodiment as described above outputs the shift selection signal SS when reading the logical state of the bonding pad 14 of either the left or right integrated circuit chip. Set to L state.
Further, the chip selection signal CS is input according to which of the integrated circuit chip, the left side or the right side, to read the logic state of the bonding pad 14. After that, at the rise of the clock signal CK, the logic state of the corresponding bonding pad 14 can be taken into the flip-flop FF. The reading of the logic state fetched by the flip-flop FF to the probe pin is performed in the same manner as in the first to fourth embodiments by setting the shift selection signal SS to the H state. You can

When the logic state is input from the probe pin, the shift select signal SS is set to the H state and operated as a shift register, as in the first to fourth embodiments. Thus, the bit data is set in each of the flip-flops FF. When the bit data is set in each of the flip-flops FF, the gate signal E or E bar is input to the transfer gate 44, and the signal is input in synchronization between the plurality of bonding pads 14. It is possible. At this time, the transfer gate 44
Is connected to both the terminal TI of the left integrated circuit chip and the terminal TI of the right integrated circuit chip, so that the output of the flip-flop FF is also output to the bonding pad 14 of any integrated circuit chip. It is possible.

Also in the fifth embodiment, whether the bonding pad 14 in the integrated circuit chip area is connected to the input buffer, the output buffer, or the bidirectional buffer. Wiring is performed for the bonding pad 14 and the terminals TO and TI corresponding to the bonding pad 14 depending on whether they are connected or not. This wiring may be, for example, a customized wiring as in the third embodiment and the fourth embodiment. For example, when the bonding pad 14 is connected to the input buffer, wiring with the terminal TI is performed.
On the other hand, for example, when the bonding pad 14 is connected to the output buffer, the bonding pad 1
4 performs wiring to the terminal TO corresponding to this.

As described above, according to this embodiment, the same effect as that of the fourth embodiment can be obtained. Furthermore,
According to the fifth embodiment, since the integrated circuit chip input / output circuit is shared between the adjacent integrated circuit chips, the area of the scribe line region in which the integrated circuit chip input / output circuit is incorporated is effective. Can be used for.

[0089]

As described above, according to the present invention, the probe test can be more easily performed even in an integrated circuit chip having a narrow pitch of bonding pads due to an increase in the number of bonding pads of the integrated circuit chip. It is possible to obtain an excellent effect that it is possible.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an integrated circuit chip input / output circuit used in a semiconductor wafer according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a boundary scan register used in the integrated circuit chip input / output circuit of the first embodiment.

FIG. 3 is a time chart showing the operation of the integrated circuit chip input / output circuit of the first embodiment.

FIG. 4 is a circuit diagram of an integrated circuit chip input / output circuit used for a semiconductor wafer according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a boundary scan register used in the integrated circuit chip input / output circuit of the second embodiment.

FIG. 6 is a time chart showing the operation of the integrated circuit chip input / output circuit of the second embodiment.

FIG. 7 is a partially enlarged plan view of a semiconductor wafer according to third to fifth embodiments of the present invention.

FIG. 8 is a partially enlarged plan view of a boundary portion between an integrated circuit chip region and a scribe line region of the third embodiment and the fourth embodiment.

FIG. 9 is a circuit diagram of an integrated circuit chip input / output circuit used in the third embodiment.

FIG. 10 is a circuit diagram of a chip input / output circuit portion of the integrated circuit chip input / output circuit of the third embodiment.

FIG. 11 is a circuit diagram of a chip input / output circuit portion of an integrated circuit chip input / output circuit used in the fourth embodiment.

FIG. 12 is a partially enlarged plan view of a scribe line region of the fifth embodiment.

FIG. 13 is a circuit diagram of a chip input / output circuit portion of the integrated circuit chip input / output circuit used in the fifth embodiment.

[Explanation of symbols]

 1a to 1i ... Integrated circuit chip 10 ... Probe pads 12a, 12b ... Boundary scan register 14 ... Bonding pad 16a ... Input buffer 16b ... Output buffer 30, 30a ... Multiplexer 44 ... Transfer gate 46 ... Bus holder SI, SI1, SI2 ... Shift data Input SO, SO1, SO2 ... Shift data output CK, CK1, CK2 ... Clock signal SS ... Shift selection signal CS ... Chip selection signal Wa-Wd ... Output buffer output Ba-Bd ... Bit data FF ... Flip-flop TO, TI ... Terminal

Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display area H01L 21/82

Claims (3)

[Claims] 1. A plurality of boundaries provided on a wafer in a scribe line region between integrated circuit chips and corresponding to bonding pads on the integrated circuit chip used for inputting / outputting signals. An integrated circuit chip input / output circuit comprising a scan register and a probe pad having a wider pitch than the bonding pad for operating and accessing the plurality of boundary scan registers as a shift register. 2. The integrated circuit chip input / output circuit of each of the adjacent integrated circuit chips according to claim 1, wherein at least one of the boundary scan register and the probe pad is shared. Integrated circuit chip I / O circuit. 3. The integrated circuit chip according to claim 1, wherein the integrated circuit chip is a semi-custom integrated circuit chip, and wiring to the bonding pad for input and wiring to the bonding pad for output are provided. Both are provided on the side of the semi-custom integrated circuit chip, and in the design of the customized circuit portion in the semi-custom integrated circuit chip, it is determined whether the boundary scan register is used for input or output. An integrated circuit chip input / output circuit characterized by being capable of