JPH06163607A - Method for die bonding semiconductor element - Google Patents
Method for die bonding semiconductor elementInfo
- Publication number
- JPH06163607A JPH06163607A JP33532792A JP33532792A JPH06163607A JP H06163607 A JPH06163607 A JP H06163607A JP 33532792 A JP33532792 A JP 33532792A JP 33532792 A JP33532792 A JP 33532792A JP H06163607 A JPH06163607 A JP H06163607A
- Authority
- JP
- Japan
- Prior art keywords
- die
- heat sink
- electrode
- semiconductor
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/83141—Guiding structures both on and outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子のダイボン
ド方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a die bonding method for semiconductor devices.
【０００２】[0002]
【従来の技術】以下、添付図面を参照して、従来の技術
を説明する。図２は、従来の半導体レ−ザ素子のダイボ
ンド方法の一例を説明するための製造工程図である。図
２において、１０は半導体レ−ザ素子であり、４は下部
電極を、５はｐ型クラッド層を、６は活性層を、７はｎ
型クラッド層を、８は上部電極を、それぞれ示す。ま
た、１はヒ−トシンクを、９はろう材を、それぞれ示
す。2. Description of the Related Art A conventional technique will be described below with reference to the accompanying drawings. FIG. 2 is a manufacturing process diagram for explaining an example of a conventional die bonding method for a semiconductor laser device. In FIG. 2, 10 is a semiconductor laser device, 4 is a lower electrode, 5 is a p-type cladding layer, 6 is an active layer, and 7 is n.
The mold clad layer and the upper electrode 8 are respectively shown. Further, 1 indicates a heat sink, and 9 indicates a brazing material.
【０００３】まず、従来の半導体レ−ザ素子のダイボン
ド方法を、図２の製造工程図に従って説明する。図２
（Ａ）には、ダイボンド直前の半導体レ−ザ素子１０と
ろう材９及びヒ−トシンク１を示す。上部電極８の形成
されたｎ型クラッド層７と下部電極４の形成されたｐ型
クラッド層５とこの２つのクラッド層間に配置された活
性層６とから構成されたＤＨ接合部をもつ半導体レ−ザ
素子１０が、ヒ−トシンク１上に形成されたろう材９上
に配置されている。半導体レ−ザ素子１０の形状は、横
４００μｍ、奥行き４００μｍ、高さ１５０μｍであ
る。ｐ型クラッド層５は、その中央部が突き出してお
り、その付きだし高さは、２μｍであり、その突き出し
部の幅は２０μｍである。上部電極８及び下部電極４
は、Ａｕ系合金膜より構成されており、その厚さは１μ
ｍである。First, a conventional die-bonding method for a semiconductor laser device will be described with reference to the manufacturing process diagram of FIG. Figure 2
1A shows the semiconductor laser element 10, the brazing material 9 and the heat sink 1 immediately before die bonding. A semiconductor laser having a DH junction composed of an n-type clad layer 7 having an upper electrode 8 formed therein, a p-type clad layer 5 having a lower electrode 4 formed therein, and an active layer 6 disposed between the two clad layers. The element 10 is arranged on the brazing material 9 formed on the heat sink 1. The shape of the semiconductor laser device 10 is 400 μm in width, 400 μm in depth, and 150 μm in height. The p-type clad layer 5 has a projecting central portion, a protrusion height of 2 μm, and a projecting portion width of 20 μm. Upper electrode 8 and lower electrode 4
Is composed of an Au-based alloy film, and its thickness is 1 μm.
m.
【０００４】ヒ−トシンク１上には、Ｉｎからなるろう
材９が、蒸着法によって形成されている。その形状は、
横４００μｍ、奥行き４００μｍ、高さ５μｍである。
次に、ヒ−トシンク９は２００℃まで加熱される。半導
体レ−ザ素子１０の上部電極８にヒ−トシンク１に向か
う一定の加圧力が印加される。加熱されたろう材９は、
軟化変形し、下部電極４と接合する。以上のように、半
導体レ−ザ素子１０のダイボンドが行われる。この後、
ヒ−トシンクは冷却されて、後処理されて、半導体レ−
ザ装置になる。図２（Ｂ）には、ヒ−トシンク１にダイ
ボンドされた半導体レ−ザ素子１０を示す。A brazing material 9 made of In is formed on the heat sink 1 by a vapor deposition method. Its shape is
The width is 400 μm, the depth is 400 μm, and the height is 5 μm.
Next, the heat sink 9 is heated to 200 ° C. A constant pressing force toward the heat sink 1 is applied to the upper electrode 8 of the semiconductor laser device 10. The heated brazing filler metal 9
It is softened and deformed and joined to the lower electrode 4. As described above, the die bonding of the semiconductor laser device 10 is performed. After this,
The heat sink is cooled, post-processed and the semiconductor laser is
It becomes the device. FIG. 2B shows the semiconductor laser device 10 die-bonded to the heat sink 1.
【０００５】次に、半導体レ−ザ装置の各部の機能を説
明する。ｐ型クラッド層５と活性層６及びｎ型クラッド
層７とからなるＤＨ接合部は、レ−ザ光放出部になる。
すなわち、ｐ型クラッド層５に接続された上部電極４
と、ｎ型クラッド層７に接続された下部電極８との間に
電圧を印加すると、ＤＨ接合部はレ−ザ発光する。レ−
ザ発光は、ＤＨ接合部を含む面に垂直方向に、ＤＨ接合
部より半導体レ−ザ装置の外部へ放射される。下部電極
４は、ろう材９を通してヒ−トシンク１に電気的に接続
されている。又、ろう材９は、半導体レ−ザ素子１０を
ヒ−トシンク１に機械的に固定する機能を持つ。さら
に、ろう材９はレ−ザ発光によりＤＨ接合部に発生した
熱をヒ−トシンク１に放散させる機能も持つ。Next, the function of each part of the semiconductor laser device will be described. The DH junction consisting of the p-type cladding layer 5, the active layer 6 and the n-type cladding layer 7 becomes a laser light emitting portion.
That is, the upper electrode 4 connected to the p-type cladding layer 5
And a lower electrode 8 connected to the n-type cladding layer 7, a DH junction emits laser light. Ray
The emitted light is emitted from the DH junction to the outside of the semiconductor laser device in the direction perpendicular to the surface including the DH junction. The lower electrode 4 is electrically connected to the heat sink 1 through the brazing material 9. The brazing material 9 also has a function of mechanically fixing the semiconductor laser element 10 to the heat sink 1. Further, the brazing filler metal 9 also has a function of dissipating the heat generated in the DH joint portion by the laser emission to the heat sink 1.
【０００６】[0006]
【発明が解決しようとする課題】ところで、上述の半導
体素子のダイボンド方法において、ろう材により半導体
素子をヒ−トシンクにダイボンドする際に、一定量のろ
う材を一定温度で一定の加圧力の下でダイボンドを行っ
ているが、半導体素子は、その形状が微小であるため、
常に一定温度でダイボンドすることが困難であった。そ
のため、ろう材が半導体素子の側面に這い上がり、ＤＨ
接合部にまで達し、ＤＨ接合部を電気的に短絡したり、
ろう材が下部電極のＡｕ系合金膜と反応を起こし、Ａｕ
系合金膜に吸収されてしまい、下部電極とヒ−トシンク
の接合が不十分となり、この接合部は機械的にも弱く電
気抵抗も増加し、ＤＨ接合部で発生する熱の放熱効果も
悪くなったりしていた。In the die-bonding method for a semiconductor element described above, when a semiconductor element is die-bonded to a heat sink with a brazing material, a certain amount of brazing material is applied at a constant temperature and under a constant pressure. Although the die-bonding is done in, the shape of the semiconductor element is very small.
It was always difficult to die bond at a constant temperature. Therefore, the brazing material creeps up on the side surface of the semiconductor element, causing DH
Reaching the junction and electrically shorting the DH junction,
The brazing material reacts with the Au-based alloy film of the lower electrode,
The lower electrode and the heat sink are not sufficiently joined to each other because they are absorbed by the system alloy film, and this joint is mechanically weak and electric resistance increases, and the heat dissipation effect of heat generated at the DH joint also deteriorates. It was.
【０００７】一方、ｐ型クラッド層の下部電極側の中央
部は突起となっており、その上に下部電極が形成されて
いる。半導体素子をヒ−トシンクにダイボンドする際に
は、下部電極を先端部にして、半導体素子はヒ−トシン
クに加圧しながら押し付けられる。この時、下部電極面
が、ヒ−トシンク面に平行にならないことがあり、この
場合には、ｐ型クラッド層の一部に加圧力が集中するた
め、ｐ型クラッド層が、破壊されることがあった。そこ
で、本発明は半導体素子をヒ−トシンクにダイボンドす
る時、ろう材の厚さを一定にできるようにし、それによ
り、半導体素子の側面へのろう材の這い上がりによるＤ
Ｈ接合部の電気的短絡を防止し、ダイボンドの際に半導
体素子を破壊しない、放熱効果の良いろう材層を形成で
きる、半導体素子のダイボンド方法を提供する事を目的
とする。On the other hand, the central portion of the p-type cladding layer on the lower electrode side is a protrusion, and the lower electrode is formed on the protrusion. When the semiconductor element is die-bonded to the heat sink, the semiconductor element is pressed against the heat sink while applying pressure to the heat sink, with the lower electrode as the tip. At this time, the lower electrode surface may not be parallel to the heat sink surface. In this case, the pressing force is concentrated on a part of the p-type cladding layer, so that the p-type cladding layer is destroyed. was there. Therefore, the present invention allows the thickness of the brazing material to be constant when the semiconductor element is die-bonded to the heat sink, so that the brazing material creeps up to the side surface of the semiconductor element.
An object of the present invention is to provide a die-bonding method for a semiconductor element, which can prevent an electrical short circuit at the H-junction, prevent a semiconductor element from being destroyed during die-bonding, and can form a brazing material layer having a good heat dissipation effect.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体素子のダ
イボンド方法は、ダイボンド面側の半導体層の突起部に
形成された一つの電極を持つ半導体素子をろう材を介し
てヒ−トシンクに取り付けるダイボンド方法において、
このヒ−トシンクのダイボンド面上にスペ−サを配置
し、深さが前記半導体層の突起部と前記一つの電極との
合計の高さより深く、且つ幅が前記一つの電極の幅より
大きくしかも前記半導体素子の素子幅より小さい溝をこ
のスペ−サに設け、この溝にろう材を充填する工程を有
することにより、上述の目的を達成するものである。According to the method of die-bonding a semiconductor element of the present invention, a semiconductor element having one electrode formed on a protrusion of a semiconductor layer on the die-bonding surface side is attached to a heat sink via a brazing material. In the die-bonding method,
A spacer is arranged on the die bond surface of the heat sink, the depth is deeper than the total height of the protrusions of the semiconductor layer and the one electrode, and the width is larger than the width of the one electrode. The above object is achieved by providing a groove smaller than the element width of the semiconductor element in the spacer and filling the groove with a brazing material.
【０００９】[0009]
【実施例】以下、添付図面を参照して本発明の一実施例
を説明する。図１は、本発明の半導体素子のダイボンド
方法の一実施例である半導体レ−ザ素子のダイボンド方
法を説明するための製造工程図である。符号は、前述の
従来例の場合と共通のものは、同一符号を付けてその説
明を省略する。図１において、２はろう材を、３はスペ
−サを示す。図１（Ａ）には、ダイボンド直前の半導体
レ−ザ素子１０を示す。上部電極８の形成されたｎ型ク
ラッド層７と下部電極４の形成されたｐ型クラッド層５
とこの２つのクラッド層間に配置された活性層６とから
構成されたＤＨ接合部をもつ半導体レ−ザ素子１０が、
ヒ−トシンク上１に形成されたろう材２上に配置されて
いる。半導体レ−ザ素子１０の形状は、横４００μｍ、
奥行き４００μｍ、高さ１５０μｍである。ｐ型クラッ
ド層５は、その中央部が突き出しており、その突き出し
高さは、２μｍであり、その突き出し部の幅は２０μｍ
である。上部電極８及び下部電極４は、Ａｕ系合金膜よ
り構成されており、その厚さは１μｍである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a manufacturing process diagram for explaining a die bonding method for a semiconductor laser device, which is an embodiment of the die bonding method for a semiconductor device of the present invention. The reference numerals common to those in the above-mentioned conventional example are given the same reference numerals and the description thereof will be omitted. In FIG. 1, 2 is a brazing filler metal and 3 is a spacer. FIG. 1A shows a semiconductor laser device 10 immediately before die bonding. The n-type cladding layer 7 having the upper electrode 8 formed thereon and the p-type cladding layer 5 having the lower electrode 4 formed thereon
And a semiconductor laser device 10 having a DH junction composed of an active layer 6 disposed between the two clad layers,
It is arranged on the brazing material 2 formed on the heat sink 1. The shape of the semiconductor laser device 10 is 400 μm in width,
The depth is 400 μm and the height is 150 μm. The central portion of the p-type clad layer 5 projects, the projection height is 2 μm, and the width of the projection is 20 μm.
Is. The upper electrode 8 and the lower electrode 4 are made of an Au-based alloy film and have a thickness of 1 μm.
【００１０】一方、ヒ−トシンク１上には、スペ−サ３
となる厚さ４μｍのＳｉＮ薄膜が、ＣＶＤ法により形成
された後、ダイボンド位置にある３４０μｍ×３４０μ
ｍの領域のＳｉＮ薄膜が除去される。次に、ろう材２と
なる厚さ４μｍのＩｎ薄膜が蒸着法によって形成され、
さらに、ダイボンド位置にある３４０μｍ×３４０μｍ
の領域に埋め込まれたＩｎ薄膜を残して、他のＩｎ薄膜
は除去される。On the other hand, on the heat sink 1, there is a spacer 3
After the SiN thin film having a thickness of 4 μm is formed by the CVD method, 340 μm × 340 μ at the die bond position.
The SiN thin film in the region m is removed. Next, an In thin film having a thickness of 4 μm to be the brazing material 2 is formed by the vapor deposition method,
Furthermore, 340 μm × 340 μm at the die bond position
Other In thin films are removed, leaving the In thin film buried in the region of.
【００１１】次に、ヒ−トシンク１は２００℃まで加熱
される。半導体レ−ザ素子１０の上部電極８にヒ−トシ
ンクに向かう一定の加圧力が印加される。加熱されたろ
う材２は、軟化変形し、下部電極４と接合する。この
時、突き出し部の容積相当分のろう材２がｐ型クラッド
層５の周囲にわずかにはみ出すが問題ない。以上のよう
に、半導体レ−ザ素子１０のダイボンドが行われる。こ
の後、ヒ−トシンク１は冷却されて、後処理されて、半
導体レ−ザ装置になる。図２（Ｂ）には、ヒ−トシンク
１にダイボンドされた半導体レ−ザ素子１０を示す。Next, the heat sink 1 is heated to 200.degree. A constant pressing force toward the heat sink is applied to the upper electrode 8 of the semiconductor laser device 10. The heated brazing material 2 is softened and deformed, and is joined to the lower electrode 4. At this time, there is no problem that the brazing material 2 corresponding to the volume of the protruding portion slightly protrudes around the p-type cladding layer 5. As described above, the die bonding of the semiconductor laser device 10 is performed. After that, the heat sink 1 is cooled and post-processed to be a semiconductor laser device. FIG. 2B shows the semiconductor laser device 10 die-bonded to the heat sink 1.
【００１２】上述のようにダイボンドされた半導体レ−
ザ装置を調べた結果、ろう材２が半導体レ−ザ素子１０
の側面に盛り上がっていなかった。電気特性を測定した
ところ、電気的な短絡がない事が確認された。この半導
体レ−ザ装置の側面を研磨してダイボンド部の断面を調
べた結果、ヒ−トシンク１面と下部電極４面との間隔は
１μｍ一定で、平行でありろう材２の脱落もみられなか
った。A semiconductor laser die-bonded as described above.
As a result of investigating the laser device, the brazing material 2 is the semiconductor laser element 10.
Wasn't raised on the side of. When the electrical characteristics were measured, it was confirmed that there was no electrical short circuit. As a result of polishing the side surface of this semiconductor laser device and examining the cross section of the die-bonded portion, the distance between the heat sink 1 surface and the lower electrode 4 surface was constant at 1 μm, and the brazing material 2 did not fall off. It was
【００１３】なお、上述の本発明の実施例では、ヒ−ト
シンクのダイボンド面上にスペ−サを配置し、深さが半
導体層の突起部と一つの電極との合計の高さより深く、
且つ幅が一つの電極の幅より大きくしかも半導体素子の
素子幅より小さい溝をこのスペ−サに設け、この溝にろ
う材を充填する工程を有する時の結果について述べた
が、深さが半導体層の突起部と一つの電極との合計の高
さより深く、且つ幅が一つの電極の幅より大きくしかも
半導体素子の素子幅より小さい溝をヒ−トシンクのダイ
ボンド面に設け、この溝にろう材を充填する工程を有す
る場合にも、良好な結果が得られる事は、言うまでもな
い。In the above-described embodiment of the present invention, the spacer is arranged on the die-bonding surface of the heat sink, and the depth is deeper than the total height of the protrusion of the semiconductor layer and one electrode.
The result of the step of providing a groove having a width larger than the width of one electrode and smaller than the element width of the semiconductor element in this spacer and filling the groove with a brazing material is described. A groove deeper than the total height of the protrusions of the layer and one electrode and having a width larger than the width of one electrode and smaller than the element width of the semiconductor element is formed on the die-bonding surface of the heat sink, and the brazing material is provided in this groove. Needless to say, good results can be obtained even when there is a step of filling.
【００１４】[0014]
【発明の効果】以上説明したように本発明の半導体素子
のダイボンド方法は、ダイボンド面側の半導体層の突起
部に形成された一つの電極を持つ半導体素子をろう材を
介してヒ−トシンクに取り付けるダイボンド方法におい
て、このヒ−トシンクのダイボンド面上にスペ−サを配
置し、深さが前記半導体層の突起部と前記一つの電極と
の合計の高さより深く、且つ幅が前記一つの電極の幅よ
り大きくしかも前記半導体素子の素子幅より小さい溝を
このスペ−サに設け、この溝にろう材を充填する工程を
有することにより、ダイボンドする時、ろう材の厚さを
一定にできるようにし、それにより、半導体素子の側面
へのろう材の這い上がりによるＤＨ接合部の電気的短絡
を防止し、ダイボンドの際に半導体素子を破壊しない、
放熱効果の良いろう材層を形成できる、半導体素子のダ
イボンド方法を提供する事が出来る。As described above, according to the method for die-bonding a semiconductor element of the present invention, a semiconductor element having one electrode formed on the protrusion of the semiconductor layer on the die-bonding surface side is used as a heat sink via a brazing material. In the die-bonding method for mounting, a spacer is arranged on the die-bonding surface of the heat sink, and the depth is deeper than the total height of the protrusion of the semiconductor layer and the one electrode, and the width is the one electrode. By providing a groove larger than the width of the semiconductor element and smaller than the element width of the semiconductor element in this spacer and filling the groove with a brazing filler metal, the thickness of the brazing filler metal can be made constant during die bonding. In this way, it is possible to prevent an electrical short circuit of the DH junction due to the brazing material creeping up to the side surface of the semiconductor element, and to prevent the semiconductor element from being broken during die bonding.
It is possible to provide a die-bonding method for a semiconductor element, which can form a brazing material layer having a good heat dissipation effect.
【図１】本発明の光半導体素子のダイボンド方法の一実
施例である半導体レ−ザ素子のダイボンド方法を説明す
るための製造工程図である。FIG. 1 is a manufacturing process diagram for explaining a die bonding method for a semiconductor laser device which is an embodiment of the die bonding method for an optical semiconductor device according to the present invention.
【図２】従来の半導体レ−ザ素子のダイボンド方法の一
例を説明するための製造工程図である。FIG. 2 is a manufacturing process diagram for explaining an example of a conventional die-bonding method for a semiconductor laser device.
１ ヒ−トシンク ２ ろう材 ３ スペ−サ ４ 下部電極 ５ ｐ型クラッド層 １０ 半導体レ−ザ素子（半導体素子） DESCRIPTION OF SYMBOLS 1 Heat sink 2 Brazing material 3 Spacer 4 Lower electrode 5 p-type clad layer 10 Semiconductor laser element (semiconductor element)
Claims (2)
成された一つの電極を持つ半導体素子をろう材を介して
ヒ−トシンクに取り付けるダイボンド方法において、こ
のヒ−トシンクのダイボンド面上にスペ−サを配置し、
深さが前記半導体層の突起部と前記一つの電極との合計
の高さより深く、且つ幅が前記一つの電極の幅より大き
くしかも前記半導体素子の素子幅より小さい溝をこのス
ペ−サに設け、この溝にろう材を充填する工程を有する
ことを特徴とする半導体素子のダイボンド方法。1. A die-bonding method in which a semiconductor element having one electrode formed on a protrusion of a semiconductor layer on the die-bonding surface side is attached to a heat sink via a brazing material, and a space is formed on the die-bonding surface of the heat sink. -Place the
This spacer is provided with a groove having a depth deeper than the total height of the protrusion of the semiconductor layer and the one electrode, and a width larger than the width of the one electrode and smaller than the element width of the semiconductor element. A die-bonding method for a semiconductor device, which comprises a step of filling the groove with a brazing material.
成された一つの電極を持つ半導体素子をろう材を介して
ヒ−トシンクに取り付けるダイボンド方法において、深
さが前記半導体層の突起部と前記一つの電極との合計の
高さより深く、且つ幅が前記一つの電極の幅より大きく
しかも前記半導体素子の素子幅より小さい溝をこのヒ−
トシンクのダイボンド面に設け、この溝にろう材を充填
する工程を有することを特徴とする半導体素子のダイボ
ンド方法。2. A die-bonding method for mounting a semiconductor element having one electrode formed on a protrusion of a semiconductor layer on the die-bonding surface side to a heat sink via a brazing material, wherein the depth of the semiconductor layer is equal to that of the protrusion. A groove deeper than the total height of the one electrode and having a width larger than the width of the one electrode and smaller than the element width of the semiconductor element is formed in this heater.
A die-bonding method for a semiconductor device, comprising the step of providing the die-bonding surface of a tosink and filling the groove with a brazing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33532792A JPH06163607A (en) | 1992-11-20 | 1992-11-20 | Method for die bonding semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33532792A JPH06163607A (en) | 1992-11-20 | 1992-11-20 | Method for die bonding semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06163607A true JPH06163607A (en) | 1994-06-10 |
Family
ID=18287285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33532792A Pending JPH06163607A (en) | 1992-11-20 | 1992-11-20 | Method for die bonding semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06163607A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005203519A (en) * | 2004-01-14 | 2005-07-28 | Sumitomo Electric Ind Ltd | Semiconductor light emitting device |
| WO2008031345A1 (en) * | 2006-09-12 | 2008-03-20 | Hong Kong Applied Science and Technology Research Institute Co. Ltd | Semiconductor light emitting device |
| US7446412B2 (en) * | 2006-03-28 | 2008-11-04 | Intel Corporation | Heat sink design using clad metal |
| JP2009043806A (en) * | 2007-08-07 | 2009-02-26 | Mitsubishi Electric Corp | Semiconductor light emitting device |
-
1992
- 1992-11-20 JP JP33532792A patent/JPH06163607A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005203519A (en) * | 2004-01-14 | 2005-07-28 | Sumitomo Electric Ind Ltd | Semiconductor light emitting device |
| US7446412B2 (en) * | 2006-03-28 | 2008-11-04 | Intel Corporation | Heat sink design using clad metal |
| US7882634B2 (en) | 2006-03-28 | 2011-02-08 | Intel Corporation | Method of manufacturing heat sink using clad metal |
| WO2008031345A1 (en) * | 2006-09-12 | 2008-03-20 | Hong Kong Applied Science and Technology Research Institute Co. Ltd | Semiconductor light emitting device |
| JP2009043806A (en) * | 2007-08-07 | 2009-02-26 | Mitsubishi Electric Corp | Semiconductor light emitting device |
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