JPH06163561A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06163561A JPH06163561A JP4314483A JP31448392A JPH06163561A JP H06163561 A JPH06163561 A JP H06163561A JP 4314483 A JP4314483 A JP 4314483A JP 31448392 A JP31448392 A JP 31448392A JP H06163561 A JPH06163561 A JP H06163561A
- Authority
- JP
- Japan
- Prior art keywords
- base
- region
- collector
- emitter
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
バイポーラトランジスタを有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a bipolar transistor.
【０００２】[0002]
【従来の技術】図４（ａ）に示すＥＣＬ回路において、
出力から出た信号が次段の入力に伝わる信号伝搬時間
は、回路をつなぐ配線の容量ＣL に充放電する時間で決
まり、そして充電時間はＥＣＬ回路の出力トランジスタ
Ｑ4 に流れる電流の量に関係している。このため配線が
長く容量ＣL が大きい場合、充電時間を短かくするため
には、出力トランジスタＱ4 に流す電流を多くする必要
があり、出力トランジスタＱ4 はエミッタ面積を大きく
する必要がある。しかし、配線が短かく容量ＣL が小さ
い場合、エミッタ面積の大きいトランジスタを用いると
トランジスタ内の寄生容量の影響によりエミッタ面積の
小さいトランジスタを用いた場合にくらべ、信号伝搬時
間は大きくなってしまう。2. Description of the Related Art In the ECL circuit shown in FIG.
The signal propagation time in which the signal from the output is transmitted to the input of the next stage is determined by the time for charging / discharging the capacitance C L of the wiring connecting the circuits, and the charging time is determined by the amount of current flowing in the output transistor Q 4 of the ECL circuit. Involved. Therefore, when the wiring is long and the capacitance C L is large, it is necessary to increase the current flowing through the output transistor Q 4 in order to shorten the charging time, and it is necessary to increase the emitter area of the output transistor Q 4 . However, if the wiring is short and the capacitance C L is small, the signal propagation time becomes longer when a transistor having a large emitter area is used than when a transistor having a small emitter area is used due to the influence of parasitic capacitance in the transistor.
【０００３】これを解決する手段としては、エミッタ面
積の小さいトランジスタを複数個用意し、負荷の小さい
場合は１個使用し、負荷の大きい時は、図４（ｂ）に示
すように、複数個並列に接続する方法があるが、この方
法でトランジスタを複数個必要とするため高集積化が困
難である。As a means for solving this, a plurality of transistors having a small emitter area are prepared, one transistor is used when the load is small, and a plurality of transistors are used when the load is large as shown in FIG. There is a method of connecting in parallel, but this method requires a plurality of transistors, and thus high integration is difficult.
【０００４】このため、従来の方法では１つのコレクタ
領域内に複数個のエミッタ領域を配置し、ベース電極を
共通とし、負荷の小さいときは１つのエミッタを用い、
負荷の大きい時は複数個のエミッタを用いることで電流
の量を調整してことで素子の面積を縮小し高集積化を実
現している。Therefore, according to the conventional method, a plurality of emitter regions are arranged in one collector region, a common base electrode is used, and when the load is small, one emitter is used.
When the load is large, the amount of current is adjusted by using a plurality of emitters to reduce the area of the device and achieve high integration.
【０００５】図５は従来の半導体装置の一例を示す平面
図、図６は図５の拡大断面図である。FIG. 5 is a plan view showing an example of a conventional semiconductor device, and FIG. 6 is an enlarged sectional view of FIG.
【０００６】図５及び図６に示すように、Ｐ型シリコン
基板１１の上に設けたＮ+ 型埋込層１２及びＮ型エピタ
キシャル層１３を溝１に埋込んだ絶縁膜１４で分離した
コレクタ領域内にコレクタ引出領域２の複数のベース領
域３を設け、ベース領域３のそれぞれに接続するベース
引出電極４を共通に設けて各ベース領域３を互に接続
し、ベース引出電極４を含む表面に設けた絶縁膜１５に
よりベース領域３と絶縁してベース領域３に設けたエミ
ッタ領域５及びエミッタ領域５と接続するエミッタ電極
１６を形成する。As shown in FIGS. 5 and 6, the N + type buried layer 12 and the N type epitaxial layer 13 provided on the P type silicon substrate 11 are separated by the insulating film 14 buried in the trench 1. A plurality of base regions 3 of the collector extraction region 2 are provided in the region, a base extraction electrode 4 connected to each of the base regions 3 is commonly provided to connect the base regions 3 to each other, and a surface including the base extraction electrode 4 The insulating film 15 provided in the base region 3 is insulated from the base region 3 to form the emitter region 5 provided in the base region 3 and the emitter electrode 16 connected to the emitter region 5.
【０００７】[0007]
【発明が解決しようとする課題】従来の半導体装置は、
配線による遅延時間を調整する方法として、出力トラン
ジスタに流す電流を変えて行なっている。そして電流を
変える方法として出力用のトランジスタを複数個用意
し、使用する個数を変えることで行なっていた。しか
し、この方法では素子数が多くなり、広い面積を必要と
するため、高集積化が困難であった。The conventional semiconductor device is
As a method of adjusting the delay time due to the wiring, the current flowing through the output transistor is changed. As a method of changing the current, a plurality of output transistors are prepared and the number of transistors used is changed. However, this method has a large number of elements and requires a large area, so that it is difficult to achieve high integration.
【０００８】この従来の半導体装置は、コレクタ領域を
共用しベース引出電極を共通接続した複数個のバイポー
ラトランジスタを有し、エミッタ電極の接続数を変える
ことにより、出力トランジスタの電流容量を変えてい
る。しかしこの方法では、小電流でエミッタを１個のみ
使用する場合でも大電流でエミッタを複数個使用する場
合でも、ベース領域３に接続されるベース引出電極によ
り複数のベース領域がつながっているため、ベースとコ
レクタ間に付く拡散容量Ｃjcは常に、エミッタが１個の
トランジスタにくらべエミッタの個数倍付いてしまう。This conventional semiconductor device has a plurality of bipolar transistors sharing the collector region and commonly connected to the base extraction electrode, and the current capacity of the output transistor is changed by changing the number of the emitter electrodes connected. . However, in this method, regardless of using only one emitter with a small current or using a plurality of emitters with a large current, a plurality of base regions are connected by the base extraction electrode connected to the base region 3, The diffusion capacitance C jc between the base and the collector is always twice as many as the number of emitters in a transistor having one emitter.
【０００９】したがって、出力トランジスタを小電流で
使用するためにエミッタを１個のみ使用する場合でもエ
ミッタ１個のトランジスタにくらべ２倍以上のベースと
コレクタ間容量が付いてしまうため、トランジスタのス
イッチング速度が低下してしまう問題があった。Therefore, even when only one emitter is used to use the output transistor with a small current, the switching speed of the transistor is increased because the capacitance between the base and the collector is more than twice that of the transistor with one emitter. However, there was a problem that
【００１０】また、従来例に示した様な溝により素子分
離したトランジスタでは、第１の絶縁膜１４の膜厚は薄
く、２つのベース領域を接続するベース多結晶シリコン
膜４とこの第１の絶縁膜上に形成されることになるた
め、ベース多結晶シリコン膜４とエピタキシャル層１３
の間の容量もベース・コレクタ間容量に加わってしまう
問題点があった。Further, in the transistor in which the elements are separated by the groove as shown in the conventional example, the thickness of the first insulating film 14 is thin, and the base polycrystalline silicon film 4 connecting the two base regions and the first polycrystalline silicon film 4 are connected. Since it is formed on the insulating film, the base polycrystalline silicon film 4 and the epitaxial layer 13
There is a problem that the capacitance between the two is added to the capacitance between the base and the collector.
【００１１】[0011]
【課題を解決するための手段】本発明の半導体装置は、
一導電型半導体基板上に設けて絶縁分離された逆導電型
のコレクタ領域と、前記コレクタ領域内に設けた複数の
一導電型ベース領域と、前記ベース領域内に設けた逆導
電型のエミッタ領域とを有する半導体装置において、前
記ベース領域に接続するベース引出電極が互に分離され
て形成される。The semiconductor device of the present invention comprises:
A reverse conductivity type collector region provided on a single conductivity type semiconductor substrate and insulated, a plurality of single conductivity type base regions provided in the collector region, and a reverse conductivity type emitter region provided in the base region. In the semiconductor device having, the base extraction electrode connected to the base region is formed separately from each other.
【００１２】[0012]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【００１３】図１は本発明の第１の実施例を示す平面
図、図２は図１の拡大断面図である。FIG. 1 is a plan view showing a first embodiment of the present invention, and FIG. 2 is an enlarged sectional view of FIG.
【００１４】図１及び図２に示すように、Ｐ型シリコン
基板１１の上面に選択的に設けたＮ+ 型埋込層１２を含
む表面にＮ型エピタキシャル層１３を形成する。次に、
エピタキシャル層１３の上面にＰ型シリコン基板１１に
達する溝１を設け、溝１内を充填し且つエピタキシャル
層１３の上面に絶縁膜１４を選択的に形成してＮ+ 型埋
込層１２及びＮ型エピタキシャル層１３からなるコレク
タ領域を分離する。As shown in FIGS. 1 and 2, an N type epitaxial layer 13 is formed on the surface including the N + type buried layer 12 selectively provided on the upper surface of the P type silicon substrate 11. next,
A groove 1 reaching the P-type silicon substrate 11 is provided on the upper surface of the epitaxial layer 13, the inside of the groove 1 is filled, and an insulating film 14 is selectively formed on the upper surface of the epitaxial layer 13 to form an N + -type buried layer 12 and an N-type buried layer 12. The collector region made of the type epitaxial layer 13 is separated.
【００１５】次に、絶縁膜１４に設けた中央部の開口部
よりＮ型エピタキシャル層１３にＮ型不純物をドープし
てＮ+ 型埋込層１２に達するコレクタ引出領域２を形成
し、コレクタ引出領域２を挾んで対向する左右の素子形
成領域にそれぞれベース領域３，ベース領域３に接続し
たベース引出電極４，ベース領域３内に設けたエミッタ
領域５，ベース引出電極４を含む表面に設けた絶縁膜１
５，エミッタ領域５に接続するエミッタ電極１６を形成
する。次に絶縁膜１５を選択的にエッチングしてベース
コンタクトホール６及びコレクタコンタクトホール７を
形成する。また、必要に応じコレクタ引出領域２を長径
方向に延長し、その両側にエミッタ領域５を有するベー
ス領域３を対向させて順次配列することでバイポーラト
ランジスタの電流容量も順次増大できる。Next, the N-type epitaxial layer 13 is doped with N-type impurities from the central opening provided in the insulating film 14 to form the collector extraction region 2 reaching the N + -type buried layer 12, and the collector extraction region 2 is formed. It is provided on the surface including the base extraction electrode 4 connected to the base region 3 and the base region 3, the emitter region 5 provided in the base region 3, and the base extraction electrode 4 in the left and right element formation regions that face each other across the region 2. Insulation film 1
5, an emitter electrode 16 connected to the emitter region 5 is formed. Next, the insulating film 15 is selectively etched to form the base contact hole 6 and the collector contact hole 7. Further, if necessary, the collector extraction region 2 is extended in the major axis direction, and the base regions 3 having the emitter regions 5 on both sides thereof are opposed to each other and sequentially arranged, whereby the current capacity of the bipolar transistor can be sequentially increased.
【００１６】図３は本発明の第２の実施例を示す平面図
である。FIG. 3 is a plan view showing a second embodiment of the present invention.
【００１７】図３に示すように、コレクタ領域を共有す
る２個のベース領域３の長辺を互に近接させ且つ対称的
に対向させて配置したバイホーラトランジスタのベース
引出電極４を素子分離用の溝１の上に延在させ配置し、
コレクタ引出領域２を対向させたベース領域３の短辺側
に近接させて配置した以外は第１の実施例と同様の構成
を有しており、コレクタ引出領域２を挾んでエミッタ領
域５を有するベース領域３の組を順次増設するこができ
る。As shown in FIG. 3, the base lead-out electrodes 4 of the bihora transistor in which the long sides of the two base regions 3 sharing the collector region are arranged close to each other and symmetrically opposed to each other are used for element isolation. It is arranged so as to extend above the groove 1 of
It has the same configuration as that of the first embodiment except that the collector extraction region 2 is arranged close to the short side of the opposed base region 3, and has the emitter region 5 sandwiching the collector extraction region 2. The set of base areas 3 can be sequentially added.
【００１８】[0018]
【発明の効果】以上説明したように本発明は、溝により
囲まれ分離されたコレクタ領域内に複数のベース領域と
エミッタ領域を配置する場合に、各ベース領域に接続さ
れるベース引出電極をそれぞれ独立して形成し素子分離
用溝の上に延在する様に配置してバイポーラトランジス
タの必要な電流容量に相当する個数のベース引出電極と
エミッタ電極をそれぞれ接続することにより、ベース・
コレクタ間に付く容量を最小に抑えられるという効果を
有する。As described above, according to the present invention, when a plurality of base regions and emitter regions are arranged in a collector region surrounded by a groove and separated from each other, each base lead electrode connected to each base region is arranged. By forming them independently and arranging them so that they extend above the isolation trenches, and connecting the base extraction electrodes and emitter electrodes in the number corresponding to the required current capacity of the bipolar transistor,
This has the effect of minimizing the capacitance between the collectors.
【００１９】したがって、本発明によれば容量の大幅な
増加なく、同一のコレクタ領域内に複数のエミッタを配
置可能となり、高集積化及び高性能化が容易となる効果
がある。Therefore, according to the present invention, it is possible to arrange a plurality of emitters in the same collector region without significantly increasing the capacitance, and it is easy to achieve high integration and high performance.
【図１】本発明の第１の実施例を示す平面図。FIG. 1 is a plan view showing a first embodiment of the present invention.
【図２】図１の拡大断面図。FIG. 2 is an enlarged sectional view of FIG.
【図３】本発明の第２の実施例を示す平面図。FIG. 3 is a plan view showing a second embodiment of the present invention.
【図４】ＥＣＬ回路の一例を示す回路図。FIG. 4 is a circuit diagram showing an example of an ECL circuit.
【図５】従来の半導体装置の一例を示す平面図。FIG. 5 is a plan view showing an example of a conventional semiconductor device.
【図６】図５の拡大断面図。6 is an enlarged sectional view of FIG.
１ 溝 ２ コレクタ引出領域 ３ ベース領域 ４ ベース引出電極 ５ エミッタ領域 ６ ベースコンタクトホール ７ コレクタコンタクトホール １１ Ｐ型シリコン基板 １２ Ｎ+ 型埋込層 １３ Ｎ型エピタキシャル層 １４，１５ 絶縁膜 １６ エミッタ電極Reference Signs List 1 groove 2 collector extraction region 3 base region 4 base extraction electrode 5 emitter region 6 base contact hole 7 collector contact hole 11 P-type silicon substrate 12 N + type buried layer 13 N-type epitaxial layer 14, 15 insulating film 16 emitter electrode
Claims (3)
された逆導電型のコレクタ領域と、前記コレクタ領域内
に設けた複数の一導電型ベース領域と、前記ベース領域
内に設けた逆導電型のエミッタ領域とを有する半導体装
置において、前記ベース領域に接続するベース引出電極
が互に分離されて形成されたことを特徴とする半導体装
置。1. A collector region of opposite conductivity type provided on a semiconductor substrate of one conductivity type and insulated and isolated, a plurality of base regions of one conductivity type provided in the collector region, and a reverse region provided in the base region. A semiconductor device having a conductive type emitter region, wherein a base extraction electrode connected to the base region is formed separately from each other.
クタ領域内に設けたコレクタ引出領域を挟んで対向する
ように配置した請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the base region having the emitter region is arranged so as to face each other with a collector extraction region provided in the collector region interposed therebetween.
長辺側を近接させて対向し、一対の前記ベース領域の短
辺側に近接して設けたコレクタ引出領域を有する請求項
１記載の半導体装置。3. The semiconductor according to claim 1, wherein the base regions having the emitter regions are opposed to each other with their long sides close to each other, and have collector extraction regions provided close to the short sides of the pair of base regions. apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4314483A JP3033372B2 (en) | 1992-11-25 | 1992-11-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4314483A JP3033372B2 (en) | 1992-11-25 | 1992-11-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06163561A true JPH06163561A (en) | 1994-06-10 |
| JP3033372B2 JP3033372B2 (en) | 2000-04-17 |
Family
ID=18053856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4314483A Expired - Fee Related JP3033372B2 (en) | 1992-11-25 | 1992-11-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3033372B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6300669B1 (en) | 1997-09-29 | 2001-10-09 | Nec Corporation | Semiconductor integrated circuit device and method of designing same |
| JP2005259775A (en) * | 2004-03-09 | 2005-09-22 | Oki Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2009200502A (en) * | 2009-03-19 | 2009-09-03 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
-
1992
- 1992-11-25 JP JP4314483A patent/JP3033372B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6300669B1 (en) | 1997-09-29 | 2001-10-09 | Nec Corporation | Semiconductor integrated circuit device and method of designing same |
| JP2005259775A (en) * | 2004-03-09 | 2005-09-22 | Oki Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| JP4657614B2 (en) * | 2004-03-09 | 2011-03-23 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP2009200502A (en) * | 2009-03-19 | 2009-09-03 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3033372B2 (en) | 2000-04-17 |
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