JPH06163311A - Multilayered ceramic capacitor - Google Patents

Multilayered ceramic capacitor

Info

Publication number
JPH06163311A
JPH06163311A JP4316836A JP31683692A JPH06163311A JP H06163311 A JPH06163311 A JP H06163311A JP 4316836 A JP4316836 A JP 4316836A JP 31683692 A JP31683692 A JP 31683692A JP H06163311 A JPH06163311 A JP H06163311A
Authority
JP
Japan
Prior art keywords
electrode
length
ceramic capacitor
electrodes
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4316836A
Other languages
Japanese (ja)
Other versions
JP2993301B2 (en
Inventor
Hiroshi Ito
博史 伊藤
Yoshihiro Tsutsumi
善弘 堤
Osamu Yamashita
修 山下
Masashi Hanya
正史 半谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4316836A priority Critical patent/JP2993301B2/en
Publication of JPH06163311A publication Critical patent/JPH06163311A/en
Application granted granted Critical
Publication of JP2993301B2 publication Critical patent/JP2993301B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:In a multilayered ceramic capacitor for surface mount for use in general electronic equipment, to solve the problem that when a multilayered ceramic capacitor is soldered to a printed board or the like, mechanical stress is applied to the external electrodes of the multilayered ceramic capacitor through solder by deformation stress or the like in the printed board thereby to produce cracks in the dielectric material below external electrodes, which leads to short-circuit between internal electrodes. CONSTITUTION:The sum of the length L2 of an internal electrode 2a in the direction of an external electrode 3b and the length R2 of a lower external electrode 4b in the direction of an external electrode 3a is made shorter than the distance W between the external electrodes 3a and 3b, and the sum of the length R1 of the internal electrode 2b in the direction of the external electrode 3a and the length L2 of a lower external electrode 4a in the direction of the external electrode 3b is made shorter than a distance W between the external electrodes 3a and 3b.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は積層セラミックコンデン
サに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated ceramic capacitor.

【0002】[0002]

【従来の技術】図7〜図10に従来の積層セラミックコ
ンデンサの構造を示す。
2. Description of the Related Art FIGS. 7 to 10 show the structure of a conventional monolithic ceramic capacitor.

【0003】図7〜図10において、1は複数のセラミ
ックシートを積層した誘電体、2a,2bは第1,第2
の複数の内部電極で誘電体1内部のセラミックシートを
介して交互に積層されている。3a,3bは第1,第2
の外部電極で、誘電体1の端面側に位置し、それぞれ第
1,第2の内部電極2a,2bに電気的に接続されてい
る。更に第1,第2の外部電極3a,3bに続いて使用
時のプリント基板へのはんだ付け接続、固定のための下
面電極4a,4bが形成されている(ここでは積層セラ
ミックコンデンサの各面のうちプリント基板に接すべき
面を下面と呼んでいる。)。
In FIGS. 7 to 10, reference numeral 1 is a dielectric material in which a plurality of ceramic sheets are laminated, and 2a and 2b are first and second dielectric materials.
The plurality of internal electrodes are alternately laminated via the ceramic sheets inside the dielectric 1. 3a and 3b are first and second
The external electrodes are located on the end face side of the dielectric 1 and are electrically connected to the first and second internal electrodes 2a and 2b, respectively. Further, the lower electrodes 4a and 4b for soldering and fixing to the printed circuit board during use are formed subsequently to the first and second external electrodes 3a and 3b (here, on each surface of the laminated ceramic capacitor). Of these, the surface that should contact the printed circuit board is called the bottom surface.)

【0004】以上のように構成された積層セラミックコ
ンデンサは、従来より小さな大きさで、大きな容量を得
るために、内部電極2a,2bを極力大きく広く設計す
る。また、プリント基板とのはんだ付け接続を確実に行
うために下面電極4a,4bも大きく設計されていた。
すなわち図7において第1の下面外部電極4aの第2の
外部電極3b方向への長さL1が長く、第2の内部電極
2bの第1の外部電極3a方向への長さR1も長く、両
者の和は第1,第2の外部電極3a,3b間の距離Wよ
りも長いものであった。
In the monolithic ceramic capacitor having the above-described structure, the internal electrodes 2a and 2b are designed to be as large and wide as possible in order to obtain a large size and a size smaller than conventional ones. Further, the lower electrodes 4a and 4b are also designed to be large in order to ensure the soldering connection with the printed circuit board.
That is, in FIG. 7, the length L1 of the first lower surface external electrode 4a in the direction of the second external electrode 3b is long, and the length R1 of the second internal electrode 2b in the direction of the first external electrode 3a is also long. Was longer than the distance W between the first and second external electrodes 3a and 3b.

【0005】[0005]

【発明が解決しようとする課題】前記の構造の積層セラ
ミックコンデンサをプリント基板にはんだ付けした断面
図を図10に示す。プリント基板8のランド5に下面外
部電極4a,4bが対向し、はんだ6にて接続されてい
る。このはんだ付けの際はんだ付け条件が不適切な場合
ははんだの温度等によりプリント基板8にたわみが発生
する。このたわみの応力は図上でFで代表して表され
る。この応力が積層セラミックコンデンサに伝わるとき
応力は下面外部電極4aの端部(内側)に集中し、その
部分から誘電体1にクラック7が発生する。内部電極2
a,2bは銀等にて形成されているので引っ張り応力に
対して伸びが生じ、応力が微小な場合クラックは発生し
ない。即ち、クラック7により、対向する内部電極2
a,2b間に空隙ができ、ここに湿気が浸入すると電気
回路動作時に内部電極2a,2b間にかかる電圧により
空隙内でリークが起こり、短絡不良に至る可能性がある
という問題点を有していた。
FIG. 10 shows a sectional view of the laminated ceramic capacitor having the above structure soldered to a printed circuit board. The lower surface external electrodes 4a and 4b are opposed to the land 5 of the printed circuit board 8 and are connected by the solder 6. If the soldering conditions are inappropriate during this soldering, the printed circuit board 8 will bend due to the temperature of the solder or the like. The stress of this deflection is represented by F in the figure. When this stress is transmitted to the monolithic ceramic capacitor, the stress concentrates on the end portion (inside) of the lower surface external electrode 4a, and a crack 7 is generated in the dielectric 1 from that portion. Internal electrode 2
Since a and 2b are formed of silver or the like, elongation occurs with respect to tensile stress, and cracks do not occur when the stress is small. That is, due to the crack 7, the internal electrodes 2 facing each other
There is a problem in that a gap is formed between a and 2b, and if moisture penetrates into the gap, a voltage may be applied between the internal electrodes 2a and 2b during operation of the electric circuit to cause a leak in the gap, leading to a short circuit failure. Was there.

【0006】本発明は上記従来の問題点を解決するもの
で、プリント基板にはんだ付けした際無理な応力が加わ
ってもリークにより短絡することのない高い信頼性を有
した積層セラミックコンデンサを提供することを目的と
する。
The present invention solves the above conventional problems and provides a highly reliable monolithic ceramic capacitor which does not short-circuit due to leakage even when excessive stress is applied to a printed circuit board when soldered. The purpose is to

【0007】[0007]

【課題を解決するための手段】この目的を達成するため
に本発明は第1の内部電極の第2の外部電極方向への長
さと、第2の下面外部電極の第1の外部電極方向への長
さとの和を、第1,第2の外部電極間の距離より短く、
第2の内部電極の第1の外部電極方向への長さと、第1
の下面外部電極の第2の外部電極方向への長さとの和
を、第1,第2の外部電極間の距離より短くした構成を
有している。
In order to achieve this object, the present invention is directed to the length of the first internal electrode in the direction of the second external electrode and the length of the second lower external electrode in the direction of the first external electrode. Is shorter than the distance between the first and second external electrodes,
The length of the second inner electrode in the direction of the first outer electrode,
The sum of the length of the lower surface external electrode in the direction of the second external electrode is shorter than the distance between the first and second external electrodes.

【0008】[0008]

【作用】この構成により積層セラミックコンデンサをプ
リント基板にはんだ付けした際に無理な応力がかかり誘
電体にクラックが発生したときにも、下面外部電極の端
部から走るクラックでできる誘電体の空隙は片方の内部
電極間(例えば第1の内部電極間)に発生し、対向する
第1,第2の内部電極間には発生しないため、電圧の印
加に原因する異極間リークが起きず、従って短絡不良に
は至らず、高い信頼性を得ることができる。
With this structure, even when an unreasonable stress is applied to the laminated ceramic capacitor when it is soldered to the printed circuit board and a crack is generated in the dielectric, the gap of the dielectric formed by the crack running from the end of the lower surface external electrode is It occurs between the internal electrodes on one side (for example, between the first internal electrodes) and does not occur between the opposing first and second internal electrodes, so that the leakage between different electrodes due to the application of the voltage does not occur. High reliability can be obtained without short circuit failure.

【0009】[0009]

【実施例】【Example】

(実施例1)以下、本発明の一実施例について、図面を
参照しながら説明する。図1〜図3において、1は複数
のセラミックシートを積層して形成した誘電体である。
2a,2bは第1,第2の複数の内部電極で、銀,パラ
ジウム等の材料よりなり、厚みは約3ミクロンであり、
厚み約15ミクロンのセラミックシートを介して交互に
積層されている。3a,3bは第1,第2の外部電極
で、誘電体1の端面部に位置し、それぞれ第1,第2の
内部電極2a,2bに電気的に接続されている。更に第
1,第2の外部電極3a,3bに続いて使用時のプリン
ト基板へのはんだ付け接続、固定のための下面外部電極
4a,4bが形成されている。
(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. 1 to 3, reference numeral 1 is a dielectric formed by laminating a plurality of ceramic sheets.
Reference numerals 2a and 2b denote first and second internal electrodes, which are made of a material such as silver or palladium and have a thickness of about 3 microns.
The ceramic sheets having a thickness of about 15 microns are alternately laminated. Reference numerals 3a and 3b denote first and second external electrodes, which are located on the end face portion of the dielectric 1 and electrically connected to the first and second internal electrodes 2a and 2b, respectively. Further, lower surface external electrodes 4a, 4b for soldering connection and fixing to a printed board at the time of use are formed following the first and second external electrodes 3a, 3b.

【0010】全体の大きさは約3.2mm×1.6mm×高
さ(厚み)1.2mmである。このうち、両端面の外部電
極3a,3b間の距離Wに相当するのは3.2mmであ
る。また、第1の内部電極2aの第2の外部電極3b方
向への長さL2は2.2mm、第2の下面外部電極4bの
第1の外部電極3a方向への長さR2は0.5mmであ
り、L2とR2との和は2.7mmであり、Wの3.2mm
よりも短くなっている。同様に、第2の内部電極2bの
第1の外部電極3a方向への長さR1は2.2mm、第1
の下面外部電極4aの第2の外部電極3b方向への長さ
L1は0.5mmであり、L1とR1との和は2.7mmで
ありWの3.2mmよりも短くなっている。
The overall size is about 3.2 mm × 1.6 mm × height (thickness) 1.2 mm. Of these, 3.2 mm corresponds to the distance W between the external electrodes 3a and 3b on both end surfaces. The length L2 of the first inner electrode 2a in the direction of the second outer electrode 3b is 2.2 mm, and the length R2 of the second lower surface outer electrode 4b in the direction of the first outer electrode 3a is 0.5 mm. And the sum of L2 and R2 is 2.7 mm, and W is 3.2 mm
Is shorter than. Similarly, the length R1 of the second inner electrode 2b in the direction of the first outer electrode 3a is 2.2 mm.
The length L1 of the lower surface external electrode 4a in the direction of the second external electrode 3b is 0.5 mm, the sum of L1 and R1 is 2.7 mm, which is shorter than W of 3.2 mm.

【0011】以上のように構成された積層セラミックコ
ンデンサについて、図4を用いてその動作を説明する。
プリント基板8のランド5に下面外部電極4a,4bが
対向しはんだ6にて接続されている。このはんだ付けの
際はんだ付け条件が不適切な場合ははんだの温度等によ
りプリント基板8にたわみが発生する。このたわみの応
力は図上でFで代表して表される。この応力が積層セラ
ミックコンデンサに伝わるとき応力は下面外部電極4a
の端部(内側)に集中し、その部分から誘電体1にクラ
ック7が発生する。内部電極2a,2bは銀等にて形成
されているので引っ張り応力に対して伸びが生じるの
で、応力が微小な場合クラックは発生しない。ここまで
のメカニズムは従来例と同様であるが、本実施例におい
ては、このクラック7は内部電極2aどうしの間で起
き、対向する内部電極2bには及ばない。そのためクラ
ック7の空隙を挟む第1,第2の内部電極2a,2b間
には電圧がかかることなく、従って電流のリークも起き
ることなく、コンデンサとしての性能をそのまま維持す
るので、従来のように回路動作時に電極間にかかる電圧
により空隙内でリークが起こり短絡不良に至るというこ
とがなく、信頼性の高いものとなる。
The operation of the monolithic ceramic capacitor configured as described above will be described with reference to FIG.
The lower surface external electrodes 4a and 4b are opposed to the land 5 of the printed circuit board 8 and are connected by the solder 6. If the soldering conditions are inappropriate during this soldering, the printed circuit board 8 will bend due to the temperature of the solder or the like. The stress of this deflection is represented by F in the figure. When this stress is transmitted to the monolithic ceramic capacitor, the stress is the bottom external electrode 4a.
Concentrate on the end (inner side), and cracks 7 occur in the dielectric 1 from that portion. Since the internal electrodes 2a and 2b are made of silver or the like, they are elongated with respect to the tensile stress, so that cracks do not occur when the stress is small. Although the mechanism up to this point is similar to that of the conventional example, in the present embodiment, the crack 7 occurs between the internal electrodes 2a and does not reach the opposing internal electrode 2b. Therefore, no voltage is applied between the first and second internal electrodes 2a and 2b sandwiching the void of the crack 7, and therefore current leakage does not occur, and the performance as a capacitor is maintained as it is. The voltage applied between the electrodes at the time of circuit operation does not cause a leak in the air gap to cause a short-circuit defect, resulting in high reliability.

【0012】(実施例2)以下、本発明の第2の実施例
について、図面を参照しながら説明する。図5は第2の
実施例の積層セラミックコンデンサをプリント基板に取
りつけた断面図であり、図中の符号等は前述の実施例に
て説明した構成部分と同じものについては省略する。第
2の内部電極2bの第1の外部電極3a方向への長さ
は、最下面側の長さR12は、最上面側の長さR11よ
りも長く、下面側から上面側にいくに従って順次短くな
っている。第1の内部電極2aについても同様の関係に
なっている。
(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings. FIG. 5 is a cross-sectional view in which the laminated ceramic capacitor of the second embodiment is attached to a printed circuit board, and the reference numerals and the like in the drawing are omitted for the same components as those described in the above embodiments. The length of the second inner electrode 2b in the direction of the first outer electrode 3a is such that the length R12 on the lowermost surface side is longer than the length R11 on the uppermost surface side, and gradually decreases from the lower surface side to the upper surface side. Has become. The same relationship holds for the first internal electrode 2a.

【0013】以上のように構成された積層セラミックコ
ンデンサに、クラック7が入るときを考える。一般にク
ラックは下面外部電極3a、または3bの端部から上面
側に進行する際に、垂直に真上に進行することが殆どで
あるが、まれに斜めに進行することがある。この斜めに
クラックが進行したときにも、第1,第2の内部電極2
a,2bの長さが上面にいくに従って順次短くなってい
るので、クラックは対向する内部電極2bまたは2aに
は及ばず、積層セラミックコンデンサの短絡不良を防止
できる。
Consider a case where cracks 7 are formed in the monolithic ceramic capacitor constructed as described above. Generally, when the crack progresses from the end portion of the lower surface external electrode 3a or 3b to the upper surface side, it progresses vertically right above, but rarely, it may progress obliquely. Even when the crack progresses diagonally, the first and second internal electrodes 2
Since the lengths of a and 2b are gradually shortened toward the upper surface, cracks do not reach the opposing internal electrodes 2b or 2a, and short-circuit failure of the laminated ceramic capacitor can be prevented.

【0014】(実施例3)以下、本発明の第3の実施例
について、図面を参照しながら説明する。図6は第3の
実施例の積層セラミックコンデンサをプリント基板に取
りつけた断面図であり、図中の符号等は前述の実施例に
て説明した構成部分と同じものについては省略する。第
2の内部電極2bの第1の外部電極3a方向への長さ
は、その中央部の長さR13が、その上、下面側の長さ
R11よりも長く、中央部から上、下面側にいくに従っ
て順次短くなっている。第1の内部電極2aについても
同様の関係になっている。
(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings. FIG. 6 is a cross-sectional view in which the laminated ceramic capacitor of the third embodiment is attached to a printed board, and the reference numerals and the like in the drawing are omitted for the same components as those described in the above embodiments. Regarding the length of the second inner electrode 2b in the direction of the first outer electrode 3a, the length R13 of the central portion thereof is longer than the length R11 of the upper and lower surfaces thereof, and the length from the central portion to the upper and lower surfaces is increased. It becomes shorter as you go. The same relationship holds for the first internal electrode 2a.

【0015】以上のように構成された積層セラミックコ
ンデンサに、クラック7が入るときを考える。一般にク
ラックは下面外部電極3a、または3bの端部から上面
側に進行する際に、垂直に真上に進行することが殆どで
あるが、まれに斜めに進行することがある。この斜めに
クラックが進行したときに、内部電極2bの長さを工夫
してクラックから逃げるようにした構造は第2の実施例
と同様であるが、更に本実施例では積層セラミックコン
デンサをプリント基板8に実装するときの事情を考慮し
た構造となっている。
Consider a case where cracks 7 are formed in the monolithic ceramic capacitor constructed as described above. Generally, when the crack progresses from the end portion of the lower surface external electrode 3a or 3b to the upper surface side, it progresses vertically right above, but rarely, it may progress obliquely. The structure in which the length of the internal electrode 2b is devised so as to escape from the crack when the crack progresses obliquely is the same as that of the second embodiment. It has a structure that takes into consideration the circumstances when it is mounted in No. 8.

【0016】即ち、積層セラミックコンデンサの下面を
プリント基板8と接触する方の面と規定して論議を進め
てきたのであるが、テーピング包装やスティック包装の
場合は表裏(上面、下面)を指定してのプリント基板8
への実装が可能だが、バルク包装のときはプリント基板
への実装時に表裏を指定できないことが起き得る。この
場合の上面、下面が逆に実装されたときも、本実施例で
は上面側も、下面側も内部電極が短くなっているのでク
ラックから逃げられる構造のものであり、従って短絡不
良の発生を防げるものである。
That is, although the lower surface of the monolithic ceramic capacitor has been defined as the surface that contacts the printed circuit board 8, discussion has been proceeded. In the case of taping packaging or stick packaging, the front and back surfaces (upper surface and lower surface) are specified. Printed circuit board 8
However, it is possible that the front and back sides cannot be specified when mounting on a printed circuit board in bulk packaging. Even when the upper surface and the lower surface in this case are mounted reversely, in this embodiment, the internal electrodes are short on both the upper surface side and the lower surface side, so that the structure escapes from the cracks, and therefore the occurrence of short circuit failure is prevented. It can be prevented.

【0017】[0017]

【発明の効果】以上のように本発明は第1の内部電極の
第2の外部電極方向への長さと、第2の下面外部電極の
第1の外部電極方向への長さとの和を、第1,第2の外
部電極間の距離Wより短く、第2の内部電極の第1の外
部電極方向への長さと、第1の下面外部電極の第2の外
部電極方向への長さとの和を、第1,第2の外部電極間
の距離より短くした構成とすることにより、積層セラミ
ックコンデンサをプリント基板にはんだ付けした際に無
理な応力がかかり誘電体にクラックが発生したときに
も、下面外部電極の端部から走るクラックでできる誘電
体の空隙は片方の内部電極間(例えば2a同士間)に発
生し、対向する内部電極間(2aと2bの間)には発生
しないため、電圧の印加に原因する異極間リークが起き
ず、従って短絡不良には至らず、高い信頼性を得ること
ができるものである。
As described above, according to the present invention, the sum of the length of the first internal electrode in the direction of the second external electrode and the length of the second lower surface external electrode in the direction of the first external electrode is calculated as follows. Shorter than the distance W between the first and second external electrodes, the length of the second internal electrode in the direction of the first external electrode, and the length of the first lower surface external electrode in the direction of the second external electrode. By making the sum shorter than the distance between the first and second external electrodes, even when unreasonable stress is applied to the laminated ceramic capacitor when soldering it to the printed circuit board and cracks occur in the dielectric, Since the void of the dielectric formed by the crack running from the end of the lower surface external electrode is generated between one internal electrode (for example, between 2a), it is not generated between the opposing internal electrodes (between 2a and 2b), Leakage between different poles caused by voltage application does not occur, thus short circuit failure It is not enough, in which it is possible to obtain high reliability.

【0018】また、その内部電極の長さを上面側、下面
側、中央部に応じて変えることにより、様々なクラック
に対しても上記目的を達成できるものである。
Further, by changing the length of the internal electrode depending on the upper surface side, the lower surface side, and the central portion, the above object can be achieved with respect to various cracks.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における積層セラミックコン
デンサの一部切欠斜視図
FIG. 1 is a partially cutaway perspective view of a monolithic ceramic capacitor according to an embodiment of the present invention.

【図2】本発明の一実施例における積層セラミックコン
デンサの平面図
FIG. 2 is a plan view of a monolithic ceramic capacitor according to an embodiment of the present invention.

【図3】本発明の一実施例における積層セラミックコン
デンサの正面断面図
FIG. 3 is a front sectional view of a monolithic ceramic capacitor according to an embodiment of the present invention.

【図4】本発明の一実施例における積層セラミックコン
デンサをプリント基板にはんだ付けした時、プリント基
板のたわみ状態での動作説明のための正面断面図
FIG. 4 is a front sectional view for explaining an operation in a flexed state of the printed circuit board when the multilayer ceramic capacitor according to the embodiment of the present invention is soldered to the printed circuit board.

【図5】本発明の他の実施例の積層セラミックコンデン
サの正面断面図
FIG. 5 is a front sectional view of a monolithic ceramic capacitor according to another embodiment of the present invention.

【図6】本発明のさらに他の実施例の積層セラミックコ
ンデンサの正面断面図
FIG. 6 is a front sectional view of a monolithic ceramic capacitor according to still another embodiment of the present invention.

【図7】従来の積層セラミックコンデンサの一部切欠斜
視図
FIG. 7 is a partially cutaway perspective view of a conventional monolithic ceramic capacitor.

【図8】従来の積層セラミックコンデンサの平面図FIG. 8 is a plan view of a conventional monolithic ceramic capacitor.

【図9】従来の積層セラミックコンデンサの正面断面図FIG. 9 is a front sectional view of a conventional monolithic ceramic capacitor.

【図10】従来の積層セラミックコンデンサをプリント
基板にはんだ付けした時、プリント基板のたわみ状態で
の動作説明のための正面断面図
FIG. 10 is a front cross-sectional view for explaining an operation in a flexed state of a printed circuit board when a conventional monolithic ceramic capacitor is soldered to the printed circuit board.

【符号の説明】[Explanation of symbols]

1 誘電体 2a,2b 第1,第2の内部電極 3a,3b 第1,第2の外部電極 4a,4b 第1,第2の下面外部電極 5 ランド 6 はんだ 7 クラック 8 プリント基板 1 Dielectric 2a, 2b 1st, 2nd internal electrode 3a, 3b 1st, 2nd external electrode 4a, 4b 1st, 2nd lower surface external electrode 5 Land 6 Solder 7 Crack 8 Printed circuit board

───────────────────────────────────────────────────── フロントページの続き (72)発明者 半谷 正史 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masafumi Hanatani 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 複数枚のセラミックシートを積層して形
成した誘電体と、前記誘電体の両端に形成された第1,
第2の外部電極と、前記誘電体の下面に設けられ、それ
ぞれ第1,第2の外部電極に電気的に接続された第1,
第2の下面外部電極と、前記誘電体の内部において、前
記セラミックシートを介して交互に積層され、それぞれ
第1,第2の外部電極に接続された第1,第2の複数の
内部電極とを有し、前記第1の内部電極の第2の外部電
極方向への長さと、第2の下面外部電極の第1の外部電
極方向への長さとの和を、前記第1,第2の外部電極間
の距離より短く、第2の内部電極の第1の外部電極方向
への長さと、第1の下面外部電極の第2の外部電極方向
への長さとの和を、前記第1,第2の外部電極間の距離
より短くした積層セラミックコンデンサ。
1. A dielectric body formed by laminating a plurality of ceramic sheets, and first and second dielectric layers formed on both ends of the dielectric body.
A second external electrode and first and second electrodes provided on the lower surface of the dielectric and electrically connected to the first and second external electrodes, respectively.
A second lower surface external electrode and a plurality of first and second internal electrodes which are alternately laminated inside the dielectric through the ceramic sheet and are connected to the first and second external electrodes, respectively. And the sum of the length of the first inner electrode in the direction of the second outer electrode and the length of the second lower surface outer electrode in the direction of the first outer electrode is The sum of the length of the second inner electrode in the direction of the first outer electrode and the length of the first lower surface outer electrode in the direction of the second outer electrode is shorter than the distance between the outer electrodes, and A laminated ceramic capacitor shorter than the distance between the second external electrodes.
【請求項2】 第1の内部電極の第2の外部電極方向へ
の長さを、下面側から上面側に移るに従って短くし、第
2の内部電極の第1の外部電極方向への長さを、上面側
に移るに従って短くした請求項1記載の積層セラミック
コンデンサ。
2. The length of the first internal electrode in the direction of the second external electrode is shortened as it moves from the lower surface side to the upper surface side, and the length of the second internal electrode in the first external electrode direction. The multilayer ceramic capacitor according to claim 1, wherein the length is shortened as it moves to the upper surface side.
【請求項3】 第1の内部電極の第2の外部電極方向へ
の長さを、中央部から上、下面側に移るに従って短く
し、第2の内部電極の第1の外部電極方向への長さを、
中央部から上、下面側に移るに従って短くした請求項1
記載の積層セラミックコンデンサ。
3. The length of the first inner electrode in the direction of the second outer electrode is shortened as it moves from the central portion to the upper side and the lower surface side, and the length of the second inner electrode in the direction of the first outer electrode is reduced. Length,
The length is shortened as moving from the central portion to the upper side and the lower side.
The multilayer ceramic capacitor described.
JP4316836A 1992-11-26 1992-11-26 Multilayer ceramic capacitors Expired - Fee Related JP2993301B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4316836A JP2993301B2 (en) 1992-11-26 1992-11-26 Multilayer ceramic capacitors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4316836A JP2993301B2 (en) 1992-11-26 1992-11-26 Multilayer ceramic capacitors

Publications (2)

Publication Number Publication Date
JPH06163311A true JPH06163311A (en) 1994-06-10
JP2993301B2 JP2993301B2 (en) 1999-12-20

Family

ID=18081458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4316836A Expired - Fee Related JP2993301B2 (en) 1992-11-26 1992-11-26 Multilayer ceramic capacitors

Country Status (1)

Country Link
JP (1) JP2993301B2 (en)

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