JPH06162773A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the access speed in the system where one sense amplifier is shared among plural bit lines. CONSTITUTION:Bit lines to which plural memory cells 1 are connected, a sense amplifier 4 which reads out data of memory cells 1, and transfer gates 3 which are provided between plural bit lines and the sense amplifier 4 and successively connect plural bit lines to the sense amplifier are provided. In this semiconductor storage device, a transfer order control circuit 13 which controls the order of driving of transfer gates by an external signal is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which one sense amplifier is shared by a plurality of bit lines.

[0002]

2. Description of the Related Art Conventionally, as a bit line configuration effective for a memory cell having a small area, there is an open bit line system in which a pair of bit lines and complementary bit lines are arranged on both sides of one sense amplifier. However, in this method, as the cell area becomes smaller, the interval between the bit lines becomes smaller, and the problem arises that the sense amplifier cannot be laid out at the bit line interval.

As a solution to this problem, a folded bit line system in which a cell area is enlarged and a bit line pair is arranged in a folded manner with respect to a sense amplifier is mainly used.
In this method, since the bit line pair is formed in one cell array, the sense amplifier pitch can be greatly improved, and the sense amplifier section with tight design rules can be easily laid out. However, since the memory cells can be arranged only at half of the intersections of the word lines and the bit lines, there is a problem that the area of the memory cell portion is increased and the chip size is enlarged.

Therefore, recently, a method has been proposed in which one sense amplifier is shared by a plurality of bit lines, and the data of the plurality of bit lines is sequentially amplified and read by the sense amplifier (1991 IEEE ISSCC DIGEST OF TECHNICAL PAPERS. vo
l.34 p106 TAM6.2). This method enables the layout of the sense amplifier without increasing the cell area, and is therefore attracting attention as a future bit line configuration.

However, this type of system has the following problems. That is, since one sense amplifier is shared by a plurality of bit lines, it is necessary to sequentially connect the plurality of bit lines to the sense amplifier. Therefore, 1
There is no problem when reading the data of the second bit line,
When reading the data of the sth bit line, s-1
Since it has to be performed after reading out each bit line, there is a drawback that access becomes slow.

[0006]

As described above, in the conventional semiconductor memory device in which one sense amplifier is shared by a plurality of bit lines, for example, the data of the sth bit line is read out to the outside. However, there is a problem in that it is necessary to read s−1 bit lines, which slows access.

The present invention has been made in consideration of the above circumstances, and its object is to increase the access speed in a system in which one sense amplifier is shared by a plurality of bit lines. It is to provide a semiconductor memory device to be obtained.

[0008]

The essence of the present invention is that when the data of the bit line is read to the outside, the switching elements for connecting the bit line to the sense amplifier are opened and closed in order. Is to change the position of the switching element in accordance with an external signal.

That is, according to the present invention, a bit line to which a plurality of memory cells are connected, a sense amplifier for reading data from the memory cell, and a plurality of bit lines and a sense amplifier are provided respectively. In a semiconductor memory device having a switching element for sequentially connecting the bit lines to a sense amplifier, a transfer order control circuit for controlling the order of driving the switching elements by an external signal is provided.

[0010]

According to the present invention, the switching element corresponding to the bit line to be read first can be arbitrarily set by the transfer order control circuit for controlling the order of driving the switching elements by the external signal. Therefore, conventionally, for example, when the data of the sth bit line is first read to the outside, it has to be performed after reading s−1 bit lines. Data can be read. This makes it possible to access the data faster than before.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to an embodiment of the present invention.

In FIG. 1, 1 is a memory cell array composed of a dynamic RAM, 2 is a row decoder, 3 is a transfer gate (switching element) for selecting a bit line, 4 is a sense amplifier / equalize gate, and 5 is a temporary storage register. A cell, 6 is a control signal buffer of the transfer gate 3. Reference numeral 11 is an address buffer to which an address is input.
The address signal held at is supplied to the transfer order signal generation circuit 12 together with the row decoder 2. The transfer order signal generation circuit 12 determines the order in which the transfer gates 3 are driven according to the input address, and the signal SL from this circuit 12 is supplied to the transfer order control circuit 13.

The transfer order control circuit 13 receives the signal C from the transfer gate control circuit 14 based on the signal SL.
The signal K from the circuit 13 is supplied to the control signal buffer 6. That is, the transfer order control circuit 13 is configured to distribute the basic clock CK for controlling the transfer gate 3 to the transfer gate 3 by the signal SL (generated by the transfer order signal generation circuit) decoded from the address. There is.

FIG. 2 is a circuit diagram showing a specific configuration of the transfer order control circuit 13. This circuit 13 includes four blocks each having four gates controlled by the same control signal SL.
It is configured by placing them individually. That is, the four gates of the first block are controlled by SL0, the four gates of the second block are controlled by SL1, the four gates of the third block are controlled by SL2, and the four gates of the fourth block are S.
It is controlled by L3. The basic clock CK is connected to the control signal buffer 6 through four blocks in parallel. That is, CK0 is 1 in each of the first to fourth blocks.
Connected to buffer 6 via two gates, CK1 ~ C
K3 is similarly connected. That is, the clock CK0
Signals K0 to K3 in which .about.CK3 are appropriately selected are supplied to the buffer 6.

Further, since the input of the buffer 6 is precharged to "L" during standby, it is connected to 0V (ground) with a large resistance. Clock input CK0
The driving capability of the input signal of CK3 is sufficiently larger than the precharge to 0V by this resistor, so that the input signal of the buffer 6 is determined only by SL0 to SL3 and CK0 to CK3.

FIG. 3 and FIG. 4 are circuit diagrams showing a concrete structure of the cell array, the bit line and the like. In this embodiment, one sense amplifier shares four bit lines BL0 to BL3, but the present invention is effective no matter how many bit lines are shared.

Each of the bit lines BL0 to BL3 is connected to the nodes N1 and N2 of the sense amplifier 4a through the transfer gate 3 (31 and 32). Gate terminals φt0 to φt3 of each transfer gate 3
Senses data on the bit lines BL0 to BL3
The transfer order control circuit 1 for controlling the order of transfer to a.
Connected to 3. As described above, the transfer sequence control circuit 13 outputs .phi.t0 to .phi.t3 according to the signals SL0 to SL3 obtained by decoding the basic clocks CK0 to CK3 from the addresses.
The bit line designated by the address is first selected and read.

The memory cell array 1 is composed of a plurality of memory cell units, and the memory cell unit is formed by connecting a plurality of memory cells in series. Here, an example is shown in which four memory cells MC are connected in series to form one memory cell unit. The configuration of this memory cell unit is as shown in FIG. In this embodiment, the memory cell is a DRAM memory cell, but the same effect can be obtained with an SRAM or a non-volatile memory cell, and the same effect can be obtained, so that it is also effective with other memory cells.

Memory cell arrays 1 ₁ and 1 ₂ in which a plurality of such memory cell units are arranged are arranged with a sense amplifier 4a in between. Memory cell array 1 ₁ ,
Dummy cell array _81, 82 respectively are provided in one _second end. Memory cell MC and dummy cell DC
Is a 1-transistor / 1-capacitor cell used in a normal DRAM.

The sense amplifier 4a is a CMOS flip-flop composed of nMOS transistors Q51 and Q52 and pMOS transistors Q53 and Q54. Sense amplifier 4a
Is provided with an equalizing circuit 4b adjacent thereto. The equalizing circuit 4b includes nMOS transistors Q41 and Q42 for precharging and an nMOS transistor Q for equalizing.
It is composed of 43.

Sense amplifier 4a and equalize circuit 4b
A register 5 for rewriting is arranged between the memory cell array and the memory cell arrays 1 ₁ and 1 ₂ . In this embodiment, register 5
Is configured as shown in FIG. 5B using the same memory cells MC used in the memory cell arrays 1 ₁ and 1 ₂ . Word lines WL0-WL3, / WL0- /
Corresponding to 32 memory cells selected by WL3, the register 5 also has register word lines RWL0 to RWL0 for each bit line.
16 memory cells selected by RWL7 and RWL8 to RWL15 are arranged.

The four bit lines BL0 to BL3 of _one memory cell array 1 ₁ are combined into one via a transfer gate 3 ₁ composed of nMOS transistors Q _{11 to} Q ₁₄ , respectively, and one of the sense amplifier 4a is connected. It is connected to the data node N1. 4 of the other memory cell 1 ₂
The bit lines / BL0 to / BL3 of the book are nMOS
Transfer gate 3 consisting of transistors Q61 to Q64
_They are grouped together via 2 and connected to the other data node N2 of the sense amplifier 4a.

Data nodes N1 and N of the sense amplifier 4a
2 is a global bit line G via a transfer gate 7 composed of nMOS transistors Q31 and Q32.
It is connected to BL and / GBL. The global bit lines GBL and / GBL are arranged over the memory cell arrays 1 ₁ and 1 ₂ , and are connected to a data input / output line (not shown).

6 and 7 are timing charts of this embodiment. In FIG. 6, when SL0 is activated from the address, φ
FIG. 9 is a timing diagram when t0 rises first and is read from the data of BL0. First, all bit lines are equalized and precharged. φt0 to φt
Lower 3 and raise WL0 to read data to all bit lines. First, .phi.t0 rises and the data in BL0 is transferred to the sense amplifier 4a. After reducing φt0, the sense amplifier 4a is operated to amplify the data.

Next, a register cell RC0 for temporary storage
Write to, inactivate the sense amplifier 4a, equalize, and precharge. Hereafter, perform the same operation from φt1 to φ
After t3, all φti (i = 0 to 3) are raised, all bit lines are equalized and precharged, and φti (i = 0 to 3) is lowered. Similarly, in the case of WL1 to WL3, the temporary storage register cell R
Data is stored in C1 to RC15.

The write back operation from the temporary storage register 5 to the memory cell MC is performed as follows. All φti (i =
0-3) is raised, equalized and precharged, and all φti (i = 0-3) are lowered. Data is read from the temporary storage register cell RC15 to operate the sense amplifier 4a. φt3 is raised, data is transferred to BL3, and data is written in the cell. After lowering φt3,
The sense amplifier 4a is deactivated, equalized and precharged. Similarly, from φt2 to φt0, WL3
To complete rewriting. After that, all bit lines are equalized and precharged. Similarly, WL
Perform from 2 to WL0.

FIG. 7 is a timing chart when SL2 is activated from the address, .phi.t2 first rises, and the data in BL2 is read first. Although the order of φt is different, the timing with other signals is the same as in FIG.

As described above, according to the present embodiment, the transfer order control circuit 13 for controlling the driving order of the transfer gates 3 connecting the plurality of bit lines BL and the sense amplifier 4a.
By providing, the transfer gate corresponding to the bit line to be read first can be arbitrarily set.
Therefore, conventionally, for example, when first reading the data of the sth bit line to the outside, it has to be performed after reading the s−1 bit lines. Data can be read. In other words, the bit line specified by the address is first selected and read, which makes it possible to significantly reduce the access time as compared with the conventional case.

Further, the memory cell area can be reduced as compared with the folded bit line system, and the design rules of the sense amplifier can be relaxed as compared with the open type bit line system. It is also possible to simultaneously achieve the two demands of relaxing the amplifier design rule.

The present invention is not limited to the above embodiment. In the embodiment, the case where four cells are connected in series has been described. However, this is effective not only in the case where they are connected in series but also in the case of a conventional one. There should be one or more. If the coupling noise between the bit lines can be eliminated in a process manner, the temporary storage register may be eliminated and the original bit lines may be written back immediately after the reading. In addition, various modifications can be made without departing from the scope of the present invention.

[0031]

As described above in detail, according to the present invention, 1
In the system in which one sense amplifier is shared by a plurality of bit lines, the sth bit is provided by providing a transfer order control circuit for controlling the driving order of the switching elements connecting the plurality of bit lines and the sense amplifier. When the line data is first read to the outside, it is not necessary to read s−1 bit lines, the data can be read by opening the sth switching element first, and the access speed can be increased. It becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a transfer order control circuit used in the embodiment.

FIG. 3 is a circuit diagram showing a specific configuration of a cell array and bit lines used in the example.

FIG. 4 is a circuit diagram showing a specific configuration of a cell array and bit lines used in the example.

FIG. 5 is a circuit diagram showing a specific configuration of a memory cell and a register cell used in the examples.

FIG. 6 is a signal waveform diagram showing the operation timing of the embodiment.

FIG. 7 is a signal waveform diagram showing the operation timing of the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Transfer gate (switching element), 4a ... Sense amplifier, 4b ... Equalize gate, 5 ... Temporary storage register cell, 6 ... Control signal buffer, 7 ... Transfer gate, 8 ... Dummy cell, 11 ... Address buffer, 12 ... Transfer order signal generation circuit, 13 ... Transfer order control circuit, 14 ... Transfer gate control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masako Ota 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center

Claims (3)

[Claims] 1. A bit line to which a plurality of memory cells are connected, a sense amplifier for reading data from the memory cell, and a plurality of bit lines provided between the plurality of bit lines and the sense amplifier, respectively. A semiconductor memory device comprising: a switching element that sequentially connects the bit lines of the present invention to a sense amplifier; and a transfer order control circuit that controls the order of driving these switching elements by an external signal. 2. The semiconductor memory device according to claim 1, wherein the external signal input to the transfer order control circuit is a signal decoded from an address. 3. The semiconductor memory device according to claim 1, wherein a memory cell unit in which a plurality of dynamic RAMs are connected in series is connected to the bit line.