JPH04283490A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To make the consumption power constant at an access time in spite of an access address and to reduce the noise by selecting a word line with an X decoder and making the number of memory array to access constant. CONSTITUTION:The memory array A consists of a memory cell array MCAi, and the array MCAi is connected in series with transistors QiA, QiA' and is connected with a data bus DB and an inversion DB with transistors Q4A, Q4A'. The transistors Q4A, Q4A' are made opening and closing with an output CS of a Y decoder CD and the word line WLAik is selected with the X decoder C. Here the line WLAik is selected with the X decoder C so as to be the number of array MCAi to access constant. Then when a column unit at the farthest end is accessed with the Y decoder CD, it is eliminated for the max. Consumption current to flow. Thus the consumption power at the access time is made constant in spite of the memory access address and a stable memory operation with less noise can be performed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-capacity dynamic semiconductor memory device in which bit lines are divided.

0002

[Prior Art] One transistor, one capacitor type (hereinafter referred to as
In a 1Tr type dynamic RAM, the magnitude of the differential voltage generated between a pair of bit lines during reading is influenced by the C ratio (ratio of memory cell capacitance to bit line capacitance). In a high-density memory, not only the cell capacitance becomes smaller, but also the number of cell lines connected to one bit line increases, so the bit line capacitance increases. As a result, the C ratio becomes smaller and the bit line potential difference during reading becomes smaller.

In order to improve this point, a method has been proposed in which one bit line is divided into a plurality of sections. FIG. 8 shows an example of the 1 selected by the column decoder CD.
The structure of the columns is shown. In the figure, BL0 to BL4
is each segmented bit line divided into one bit line, inverted B
L0 to inverted BL4 are complementary segmented bit lines that form a pair therewith. The dashed-dotted line frames MCA0 to MCA3 are memory cell arrays that belong to each section of the bit line. If the bit line is divided into four as in this example, the C ratio will quadruple,
The initial bit line potential difference (before the sense amplifier operates) is expanded accordingly. Each segment bit line BL0 to BL4
(Inverted BL0 to Inverted BL4) are MOS transistors Q0 to Q3 that constitute a transfer gate.
(Q0' to Q3'), and sense amplifiers SA0 to SA3 are provided for each section. WL indicates one of many word lines, and MC is one bit of a memory cell selected by the word line WL. The AR provided between the segmented bit line pair BL4 and inverted BL4 is active restore, and the AR provided between BL4 and inverted BL
Transfer gates Q4 and Q4', which are selected by the column select signal CS from the column decoder CD, are interposed between the data bus DB and the inverted DB.

φSE0 to φSE3 are sense amplifiers S
Clock that enables A0 to SA3, φT
0 to φT 3 are transfer gates Q0 to Q3
The clock that turns on (Q0' to Q3'), φA
R is a clock that enables active restore AR, and these changes at the timing shown in FIG. The operation of FIG. 8 will be described below with reference to this figure. For example, word line WL of cell array block MCA0
In order to select the word line WL, the potential of the corresponding word line WL is raised to the selection level (Vcc or higher) at time t0. This causes the data in memory cell MC to be transferred to bit line BL0, inverted BL0.
A minute potential difference (inverted BL0 > BL0) is generated between BL0 and inverted BL0. Therefore,
At time t1, a clock φSE0 is generated to activate the sense amplifier SA0. Sense amplifier SA0
consists of a flip-flop, and one transistor of the flip-flop is turned on and the other transistor is turned off by a minute potential difference between the bit line BL0 and the inverted BL0, and the turned-on transistor brings the bit line connected to the transistor to the Vss level. BL0
, inverted BL0. In this way, at time t2 when a large potential difference is generated between the bit line BL0 and the inverted BL0, the clock φT 0 to φT
3 all at once and transfer gate Q0 ~
Turn on Q3 (Q0' to Q3') and turn on bit line B.
The potentials of L0 and inverted BL0 are sequentially transferred to bit line pair BL1.
, Inverted BL1 → BL2 , Inverted BL2 → BL3 ,
The information is transmitted as follows: inverted BL3 → BL4, inverted BL4. Then, at time t3 when a potential change occurs on the final bit line BL4, inverted BL4, block φA R is started,
Operate active restore AR.

[0005] Active restore AR is connected to bit line BL.
4, the high potential side of inverted BL4 (in this case, inverted BL4
) to Vcc, further BL4, inverted BL
Since the potential difference between the transfer gates Q4 and Q4 is amplified, after waiting for this operation, the column select CS is raised at time t4 to turn on the transfer gates Q4 and Q4'. Through this series of operations, the data of the cell MC is read onto the data bus DB and inverted DB. At the same time, when the bit inversion BL4 rises to Vcc, the change is transferred to the transfer gate Q3'→Q
2'→Q1'→Q0' in the opposite direction and is transmitted to the bit line inversion BL0 on the cell MC side, raising its potential to Vcc, and this inversion BL0 = Vcc, BL = Vss
The above-mentioned read cell is rewritten. This rewriting end time t5 is the actual completion point of the read cycle.

[0006]

[Problems to be Solved by the Invention] However, when a memory with the above-mentioned configuration is applied to an actual device, it often has multiple memory array banks and multiple word lines rise during one access cycle. In such a case, in a memory device that connects columns and uses bit line pairs connected to other memory arrays as information transfer paths, the filling of the bit line pairs may vary depending on the position of the word line on the memory array bank. There is a problem in that the current consumed in discharging increases.

According to the present invention, when a plurality of word lines as described above rise, the current consumption due to bit line charging and discharging changes depending on where on the memory array bank the word line rises, , inverted BLφ, SAφ) is accessed, it is an object of the present invention to provide an excellent device that eliminates the problem of maximum current consumption flowing when a circuit including inverted BLφ, SAφ) is accessed.

[0008]

[Means for Solving the Problems] The present invention provides a memory array bank in which column units (a pair of bit lines and a column circuit including a memory cell and a sense amplifier connected thereto) are connected in series and a Y decoder is shared. In a semiconductor memory device having a plurality of devices, an X decoding means is provided so that a word line rises so that the number of memory arrays to be accessed (the number of column circuits to be activated) is constant.

[0009]

In the semiconductor memory device of the present invention, a word line is selected by an X decoder when memory array banks sharing a Y decoder access the memory array bank. This makes the number of memory arrays accessed by the Y decoder constant.

0010

[Embodiment] First, a first embodiment will be explained using FIG. Memory array bank A is memory cell array MCAi
(i=0 to 3), and MCAi is selected by bit line BLOAi, inverted BLOAi (i=0 to 3), and word line WLAlk (l=0 to n, k=0 to 3) or inverted BLOAi BLOAi
Memory cell MCpj (p=0~3, j=0~
m). MCAi is a transistor QiA
, QiA' (i=0 to 3) are connected in series, and data bus DB and inverting D are connected by transistors Q4A and Q4A'.
Connected to B. Each bit line BLiA and inverted BLiA (i=0 to 3) have a sense amplifier SAi (
i=0 to 3) are connected. The Q4A and Q4A' are opened and closed by the output CS of the Y decoder CD. Each word line WLAlk (k=0 to n) is selected by an X decoder C. Memory array bank B is mirror symmetrical to memory array bank A with respect to Y decoder CD.

FIG. 2(a) shows the circuit operation of left memory bank A, and FIG. 2(b) shows the circuit operation of memory bank B. Here, as shown in FIG. 3, WLA0i is set by C and WB0i is set by D so that the memory cells in MCA0 in memory bank A and MCB0 in memory bank B are accessed.
is selected, and read data is transferred in the CD direction. The shaded area indicates the memory cell array that becomes active.

First, the circuit operation of the left memory bank A will be described using FIGS. 1 and 2(a). WLA0i starts up at time t1. At this time, the information (charge) stored in memory cell MC0j is transferred to bit line BL0A, inverted B
A minute potential difference ΔV is generated at L0A. Then time t2
ΔV is amplified by SA0 at time t, and then at time t
At time t4, φt 0 rises, and the information on BL0A and inverted BL0A is transferred to BL1A and inverted BL1A, and is amplified by SA1 at time t4. Time t3
, t4, t5, t6 and t7, t8
As shown in the figure, this data is transferred, and when CS rises at time t9, information is sent to the DB and inverted DB. φT0~3
may rise at the same time, and the sense amplifier SA1
Even if ~3 is not necessarily active, transfer to the DB and inverted DB is possible. Here, as an example of increasing the speed of transfer, an example is shown in which the sense amplifiers are sequentially activated.

Furthermore, memory bank B is shown in FIGS. 1 and 2(b).
Shown using. WLB0i rises at time t1'. Thereafter, at time t0', the sense amplifier SB0 transfers the charge in the memory cell MC0j' to the bit line BL0B,
The memory cell information on BL0B (which generates a potential difference in the inverted BL0B) and the inverted BL0B is amplified. Time t3'
When CS' rises, the data bus D
The amplified information is transferred to B' and inverted DB'. At this time, MCBs 1 to 3, which are not related to transfer, do not become active as shown in FIG. In this way, as shown in Figure 3,
Decoder means C and D select word lines in memory array banks A and B such that when the number of active cell arrays in A is 4, the number of active cell arrays in B is 1. For example, as shown in Figure 4, when WLA1i and WLB1i start up, the number of active cell arrays of A is 3.
, B is 2, and the number of cell arrays that are always active is 5.
becomes constant.

If word lines are not selected so that the number of active memory cell arrays is constant as in the present invention, the worst case scenario is that the memory array will be 8 co-active, and power consumption will vary greatly depending on the access address. The generated noise becomes large.

Next, a second embodiment will be explained.

FIG. 5 shows another embodiment of the present invention. I, J
, K, and L are memory array banks as shown in the previous embodiment. In this example, the operations of the I and L memory array banks are completely the same as the circuit operations described in FIGS. 1 and 2. In this embodiment, the X decoder means selects the word lines so that when the word lines in the memory arrays of memory array banks I and L are selected, the word lines of memory cell banks J and K are not selected. When the I and L word lines are selected, the J and K word lines are selected. What is important here is that one of the upper and lower memory array banks is always active, and it does not matter if the word line rises so that the I, K or J, L memory array banks become active.

By doing this, the memory arrays shown in the shaded areas in FIG. The current Ip flows through the power supply line F. In the case shown in Figure 6, E has 3IP, F
2IP for E, 3IP for E in the case shown in Figure 7, F
2 IP flows. By dividing the active bank into upper and lower banks, current always flows through E and F when accessed, and does not concentrate on one power supply line. Therefore, the total power consumption is not affected by the memory access address, and since current does not concentrate on one power supply line, the width of the power supply line can be made narrower.

[0018]

As described above in detail, according to the present invention, when a Y decoder is shared and a memory array bank is accessed, the X decoder is used to Since the line is selected, the power consumption during access can be made constant regardless of the access address, and stable memory operation can be obtained.

[Brief explanation of the drawing]

[Fig. 1] Main part configuration diagram showing a first embodiment of the present invention.

[Figure 2
]Operation waveform diagram of the first embodiment of the present invention

[Fig. 3] Main part configuration diagram showing the first embodiment of the present invention

[Fig. 4] Main part configuration diagram showing the first embodiment of the present invention

[Fig. 5] Main part configuration diagram showing a second embodiment of the present invention

[Fig. 6] Main part configuration diagram showing a second embodiment of the present invention.

[Fig. 7] Main part configuration diagram showing a second embodiment of the present invention

[Figure 8] Conventional main part configuration diagram

[Figure 9] Conventional operation waveform diagram

[Explanation of symbols]

MCAi Memory cell array BL0Ai Bitline WLAlk Word line MCpj Memory cell QiA Transistor DB data bus SAi Sense Amplifier C, D X decoder CD Y decoder CS Y decoder output

Claims (2)

[Claims] 1. A memory array to be accessed in a semiconductor storage device having a plurality of memory array banks in which each column unit constituting a memory array is connected in series to other memory arrays and sharing a Y decoder. A semiconductor memory device characterized in that word lines are selected by an X decoder so that the number of word lines is constant. 2. The semiconductor memory device according to claim 1, wherein in the memory array bank having the memory array, the memory array banks to be accessed are arranged separately for two power supply lines.