JPH06162663A - Magnetic recording/reproduction device - Google Patents

Abstract

PURPOSE:To obtain a magnetic recording/reproduction device which can reproduce stable characteristics regardless of reproduction speed. CONSTITUTION:This device is provided with a first frequency switching means 8 for changing the frequency characteristics of a control channel amplifier and a second frequency switching means 9 for simultaneously changing the frequency characteristics of a control channel amplifier 5 and the above first and second main data amplifier group. The frequency characteristics of the above control channel amplifier 5 are varied between the case of high-speed search such as the search for leading end of a program and that of normal reproduction and the frequency characteristics of the above control channel amplifier and the above first and second main data amplifier groups 6 and 7 are simultaneously varied between the case of high-speed reproduction such as high-speed dubbing and that of normal reproduction, thus obtaining stable reproduction characteristics regardless of the reproduction speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital cassette tape magnetic recording / reproducing apparatus for reproducing digital signals recorded in a plurality of channels.

[0002]

2. Description of the Related Art In recent years, audio equipment tends to be converted to digital audio, and with the development of technology, a magnetic recording / reproducing apparatus with high fidelity by digital recording / digital reproduction has been developed. Among them, the S-DAT method using a fixed head has recently been commercialized and its function is being upgraded. In particular, it is predicted that high-speed playback operation of only the control channel used for cueing songs, etc. and high-speed playback operation of voice recording signals used for high-speed dubbing will become indispensable in the future. A recording / reproducing apparatus is desired. As an example of a conventional magnetic recording / reproducing apparatus capable of stable high-speed reproducing operation, Japanese Patent Publication No.
No. 055784, but there are many differences from this system, so a conventional example of this system will be given as a conventional example.

An example of a conventional magnetic recording / reproducing apparatus will be described below with reference to the drawings. FIG. 7 is a block diagram of a conventional magnetic recording / reproducing apparatus. In FIG. 7, 1 is a digital tape cassette, 2 is a magnetic head, 3
Is a tape mechanism and 4'is a digital reproducing / amplifying means, which is connected to the output of the magnetic head 2. Reference numeral 5 is a control channel amplifier, 6 is a main data first stage amplifier group, 7 is a main data second stage amplifier group, 10 is a parallel / serial conversion means, 11 'is a decoder means, 12 is a buffer amplifier, and a digital reproduction amplification means 4 The control channel amplifier 5 connected to the output of the control channel, which is one of the outputs of the magnetic head 2, and the main data connected to the main data output of the output of the magnetic head 2 other than the control channel. The data first-stage amplifier group 6, the main data second-stage amplifier group 7 connected to the output of the main data first-stage amplifier group 6, the decoder means 11 ', and the control channel amplifier connected to the output of the decoder means 11'. 5 connected to the output of the main data second stage amplifier group 7 and the parallel-serial conversion means 10
And a buffer amplifier 12 connected to the output of the parallel / serial conversion means 10. Reference numeral 14 is a variable resistor, one of both ends of the three terminals is connected to the output of the buffer amplifier 12 in the digital reproduction / amplification means 4 ', and the other is connected to the ground electrode. Reference numeral 15 is a capacitor, which is connected to the remaining intermediate terminal of the variable resistor 14.

Reference numeral 16 is a signal processing means, 17 is an A / D conversion means, and 18 is a digital signal processing means. In the signal processing means 16, an A / D conversion means 17 connected to a capacitor 15 and an A / D conversion means The decoder means 1 in the digital reproduction / amplification means 4'is connected to the output of the D / D conversion means 17.
1 ', and a digital signal processing means 18 connected to 1'. Reference numeral 19 is a D / A conversion means, which is connected to the output of the digital signal processing means 18 in the signal processing means 16.

Reference numeral 20 is a control means, 21 is an operation means, and 21a.
Is a reproduction operation switch, 21b is a search operation switch, 2
2 is a mechanism control means, the output of the operation means 21 is connected to the control means 20, the output of the control means 20 is connected to the signal processing means 16 and the mechanism control means 22,
The output of the mechanism control means 22 is connected to the tape mechanism 3.

The operation of the magnetic recording / reproducing apparatus configured as described above will be described below.

During normal reproduction, when the reproduction operation switch 21a in the operation means 21 is pressed, a reproduction operation instruction signal is output to the control means 20 and the control means 20 is operated by the mechanism control means 2
2 outputs a reproduction operation signal to the signal processing means 16 and puts the signal processing means 16 into a reproduction state. The mechanism control means 22 puts the tape mechanism 3 in which the digital tape cassette 1 is loaded into the normal reproduction operation. Digital tape cassette 1 at this time
The recorded signal is converted into a minute electric signal by the magnetic head 2, the control channel is amplified by the control channel amplifier 5 in the digital reproduction amplification means 4 ', and the main data channel is reproduced by the digital reproduction amplification means 4'.
It is amplified by the main data first stage amplifier group 6 in. The frequency characteristics of the control channel amplifier 5 and the main data first-stage amplifier group 6 are primary low-pass filter characteristics for cutting the high band which is an unnecessary band.

The output signal of the main data first stage amplifier group 6 is further amplified by the main data second stage amplifier group 7, and is output to the parallel / serial conversion means 10 together with the output signal of the control channel amplifier 5. The frequency characteristic of the main data second stage amplifier group 7 is a primary high-pass filter for correcting the frequency characteristic of the magnetic head 2 and a primary low-pass filter characteristic for cutting a high band which is an unnecessary band.

On the other hand, the digital signal processing means 18 in the signal processing means 16 which is in the reproduction operation by the output of the control means 20 converts the timing signal into the digital reproduction amplification means 4.
Output to the decoder means 11 'in the
Reference numeral 1'outputs an output channel timing signal to the parallel / serial conversion means 10 for converting the plurality of outputs of the control channel amplifier 5 and the main data second stage amplifier group 7 into one time-divided signal.

The output of the parallel / serial conversion means 10 is a buffer amplifier 12 and a variable resistor 1 for level adjustment.
4. Coupling capacitor 15 for DC level cut
Is output to the A / D conversion means 17 in the signal processing means 16 via an A / D conversion means to be converted from an analog signal to a digital signal and the magnetic head 2 in the second main data amplifier group 7
The frequency characteristic correction is supplemented and the phase characteristic is corrected. The output of the A / D conversion means 17 is a digital signal, and the digital signal processing means 18
Demodulation and error correction are performed by. The output of the digital signal processing means 18 is converted into an analog reproduction signal by the D / A conversion means 19 and can be heard as a reproduction sound.

During high-speed reproduction of the control channel used to find the beginning of a piece of music, when the search operation switch 21b in the operating means 21 is pressed, a search operation instruction signal is output to the control means 20, which causes the mechanism control means 22 to operate. The search operation signal is output to the signal processing means 16 and the signal processing means 16 is brought into the search operation state in which the cue signal of the music piece can be detected. The mechanism control means 22 sets the tape mechanism 3 in which the digital tape cassette 1 is mounted to the high speed search operation. At this time, the signal recorded in the digital tape cassette 1 is converted into a minute electric signal by the magnetic head 2,
The control channel is amplified by the control channel amplifier 5 in the digital reproduction / amplification means 4 ', and the main data channel is amplified by the main data first-stage amplifier group 6 and the main data second-stage amplifier group 7 in the digital reproduction / amplification means 4'. However, the digital signal processing means 18 in the signal processing means 16 which is in the search operation by the output of the control means 20 outputs the timing signal for selecting only the control channel to the decoder means in the digital reproduction amplifying means 4 '. 11 ', and the decoder means 11' outputs a signal to the parallel / serial conversion means 10 so as to output only the signal of the control channel amplifier 5. At this time, the frequency characteristic of the control channel amplifier 5 is a first-order low-pass filter characteristic for cutting a high frequency band which is an unnecessary band, and does not change from the characteristic at the time of normal reproduction.

The output of the parallel / serial conversion means 10 is the same as that in the normal reproduction mode, and is output from the A in the signal processing means 16 via the buffer amplifier 12, the variable resistor 14 for level adjustment, and the coupling capacitor 15 for DC level cut. Only the continuous control channel signal output to the / D conversion means 17 is converted from an analog signal to a digital signal.

The output of the A / D conversion means 17 is a digital signal, and when the digital signal processing means 18 detects a signal for cueing a prerecorded music, a detection signal is output to the control means 20. The control means 20 outputs an operation stop signal and a reproduction operation signal from the signal portion for finding the beginning of the music to the mechanism control means 22 to change the tape mechanism 3 from the high speed search state to the reproduction state. In this high speed search state, the output of the digital signal processing means 18 is D / A.
It is not output to the conversion means 19, and the D / A conversion means 19 is in the muting state.

The high-speed reproducing operation of the main data channel used for high-speed dubbing does not have the function of the conventional magnetic recording / reproducing apparatus, and the main data first-stage amplifier group in the digital reproducing / amplifying means 4 '. 6 and the main data second-stage amplifier group 7 have constant frequency characteristics, the tape mechanism 3 is brought into a high-speed reproduction state and the signal processing means 16
When the high-speed reproduction operation of the main data channel is forcibly performed by, for example, increasing the processing time of, the signal band at the time of high-speed reproduction does not match the frequency characteristics of the digital reproduction amplification means 4'and the digital reproduction at the time of high-speed reproduction The output characteristic of the means obviously becomes bad, which is a practical problem.

Next, the control channel amplifier 5, the main data first stage amplifier 6a, which is one of the main data first stage amplifier groups 6, and the main data second stage, which is one of the main data second stage amplifier groups 7, are provided. A detailed circuit of the eye amplifier 7a will be described with reference to FIG.

The control channel amplifier 5 is composed of a differential amplifier and an emitter follower output. Q1, Q2
Is a transistor that constitutes the input of the differential amplifier, and has a common emitter. I1 is a constant current source, which is connected to the common emitters of the transistors Q1 and Q2,
The other one is connected to the ground electrode. R1 and R2 are resistors, one of which is connected to the bases of Q1 and Q2, respectively, and the other of which is common. E1 is a constant voltage circuit, which is connected to the common terminal of the resistors R1 and R2.

R3 is a resistor, which is connected to the collector of the transistor Q2. The other of the resistor R3 and the collector of the other transistor Q1 of the differential amplifier are connected to the power supply electrode. C1 is a capacitor, one of which is connected to the connection point of the collector of the transistor Q2 and the resistor R3,
The other is connected to the ground electrode. Q3 is a transistor, I2 is a constant current source, and constitutes the output stage of the control channel amplifier 5. The base of the transistor Q3 is
Transistor Q2 collector, resistor R3, capacitor C
1 and the emitter of the transistor Q3 is connected to the constant current source I2. The other of the constant current sources I2 is connected to the ground electrode. The collector of the transistor Q3 is connected to the power supply electrode.

The operation will be described below. Constant voltage circuit E1
Is a transistor Q via resistors R1 and R2, respectively.
The bias voltage is supplied to Q1 and Q2, and the resistor R1 determines the input impedance of the control channel amplifier 5. The resistor R2 is a differential input transistor Q1, Q2.
This is for maintaining the balance of the base potential of.
The constant current source I1 is for determining the gain of the control channel amplifier 5 together with the resistor R3. The gain of the control channel amplifier 5 is G5, and the current value of the constant current source I1 is I.
1, and the resistance value of the resistor R3 is R3, it is expressed by the following equation.

[0019]

[Equation 1]

The transistor Q3 and the constant current source I2 form an output buffer having an emitter follower structure so that the next stage is not affected. The capacitor C1 is a first-order low-pass filter for determining the frequency characteristic of the control channel amplifier 5 together with the resistor R3, and for cutting the high band which is an unnecessary band. The cutoff frequency f5 is expressed by the following equation, where the capacitance value of the capacitor C1 is C1.

[0021]

[Equation 2]

Next, the main data initial stage amplifier 6a, which is one of the main data initial stage amplifier groups 6, will be described.

The main data first stage amplifier 6a has the same structure as the control channel amplifier 5. The main data first stage amplifier 6a is composed of a differential amplifier and an emitter follower output. Q7 and Q8 are transistors that form the input of the differential amplifier, and have the same emitter. I4 is a constant current source, which is connected to the common emitter of the transistors Q7 and Q8, and the other of the constant current source I4 is connected to the ground electrode. R8 and R9 are resistors, one of which is connected to the bases of Q7 and Q8, respectively, and the other of which is common. E
A constant voltage circuit 2 is connected to the common terminal of the resistors R8 and R9.

R10 is a resistor, which is connected to the collector of the transistor Q7. The other of the resistor R10 and the collector of the other transistor Q7 of the differential amplifier are connected to the power supply electrode. C3 is a capacitor, one of which is connected to the connection point of the collector of the transistor Q8 and the resistor R10, and the other of which is connected to the ground electrode. Q9 is a transistor, I5 is a constant current source, and constitutes the output stage of the main data first stage amplifier 6a.

The base of the transistor Q9 is connected to the connection point of the collector of the transistor Q8, the resistor R10 and the capacitor C3, and the emitter of the transistor Q9 is connected to the constant current source I5. The other of the constant current sources I5 is connected to the ground electrode. The collector of the transistor Q9 is connected to the power supply electrode.

The operation will be described below. Constant voltage circuit E2
Is a transistor Q via resistors R8 and R9, respectively.
A bias voltage is supplied to Q7 and Q8, and the resistor R8 determines the input impedance of the main data first stage amplifier 6a. The resistor R9 is a differential input transistor Q7, Q
This is for maintaining the balance of the base potential of No. 8. The constant current source I4 is for determining the gain of the main data first stage amplifier 6a together with the resistor R10. The gain of the main data first stage amplifier 6a is G6, and the constant current source I4 is
When the current value of is I4 and the resistance value of the resistor R10 is R10, it is expressed by the following equation.

[0027]

[Equation 3]

The transistor Q9 and the constant current source I5 form an output buffer having an emitter follower structure so that the next stage is not affected. The capacitor C3 is a resistor R10
Together with this, it is a first-order low-pass filter for determining the frequency characteristic of the main data first-stage amplifier 6a and cutting the high band which is an unnecessary band. The cutoff frequency f6 is represented by the following equation, where the capacitance value of the capacitor C3 is C3.

[0029]

[Equation 4]

Next, the main data second stage amplifier 7a which is one of the main data second stage amplifier groups 7 will be described.

C4 is a capacitor, and one of them is an input of the main data second stage amplifier 7a. Q10 and Q11 are transistors that form the input of the differential amplifier, and have the same emitter. I8 is a constant current source, which is connected to the common emitter of the transistors Q10 and Q11, and the other of the constant current source I8 is connected to the ground electrode.

R11, R12 and R13 are resistors, Q12,
Q13 is a transistor, I6 and I7 are constant current sources,
The bases of the transistors Q12 and Q13 are common and connected to the power supply electrode via the resistor R11. The collectors of the transistors Q12 and Q13 are connected to the power supply electrode. Transistor Q1
The emitter of 2 is connected to the other of the base of the transistor Q10, the constant current source I6, and the capacitor C4 via R12. The other of the constant current sources I6 is connected to the ground electrode. The emitter of the transistor Q13 is connected to the base of the transistor Q11 and the constant current source I7 via R13. The other of the constant current sources I7 is connected to the ground electrode. R14 is a resistor and is connected to the collector of the transistor Q11. The other of the resistor R14 and the collector of the other transistor Q10 of the differential amplifier are connected to the power supply electrode. C5 is a capacitor, one of which is connected to the connection point of the collector of the transistor Q11 and the resistor R14, and the other of which is connected to the ground electrode. Q14 is a transistor, and I9 is a constant current source, and constitutes the output stage of the second main data amplifier 7a.

The base of the transistor Q13 is connected to the connection point of the collector of the transistor Q11, the resistor R14 and the capacitor C5, and the emitter of the transistor Q14 is
It is connected to the constant current source I9. The other of the constant current sources I9 is connected to the ground electrode. The collector of the transistor Q14 is connected to the power supply electrode.

The operation will be described below. The resistor R11 and the transistor Q12 have a potential obtained by subtracting the sum of the voltage drop of the resistor R11, the base-emitter voltage drop of the transistor Q12, and the voltage drop of the resistor R12 and the constant current source I6 from the power supply voltage. , The bias potential of the transistor Q10, and the transistor Q1
The input impedance of the differential amplifier composed of 0 and Q11 is determined. The value can be approximated by the resistance value of R12, assuming that the resistance value of R12 is sufficiently larger than the output impedance of the emitter follower circuit formed by the transistor Q12. Similarly, the potential obtained by subtracting the sum of the voltage drop of the resistor R11, the voltage drop between the base and emitter of the transistor Q13, and the voltage drop of the resistor R13 and the constant current source I7 from the power supply voltage is the transistor Q1.
It is supplied as a bias potential of 1. This is for maintaining the balance of the base potentials of the transistors Q10 and Q11 which are differential inputs. The capacitor C4, together with the resistor R12, constitutes a first-order high-pass filter for correcting the frequency characteristic of the magnetic head, and its cutoff frequency f7H is C4 when the capacitance value of the capacitor C4 is C4.
It is expressed by the following formula.

[0035]

[Equation 5]

The constant current source I8 is for determining the gain of the main data second stage amplifier 7a together with the resistor R14, and the gain of the main data second stage amplifier 7a is G7,
The current value of the constant current source I8 is I8, and the resistance value of the resistor R14 is R
When it is set to 14, it is represented by the following equation.

[0037]

[Equation 6]

The transistor Q14 and the constant current source I9 form an output buffer having an emitter follower structure so that there is no influence on the next stage. The capacitor C5 is the resistor R1
4 is a primary low-pass filter for determining the frequency characteristics of the main data second stage amplifier 7a together with 4 and cutting the high band which is an unnecessary band. Its cutoff frequency f7L
Is expressed by the following equation, where the capacitance value of the capacitor C5 is C5.

[0039]

[Equation 7]

[0040]

However, in the conventional magnetic recording / reproducing apparatus as described above, the frequency characteristic of the control channel amplifier does not change during high-speed reproduction of only the control channel, and also during high-speed reproduction of the main data, As in the normal reproduction, the frequency characteristics of the control channel amplifier and the first and second main data channel amplifier groups do not change, and there is a problem that the change in the band of the actual reproduction signal is not followed.

In view of the above-mentioned conventional problems, the present invention changes the frequency characteristic of the control channel amplifier to an optimum characteristic during high speed reproduction of only the control channel, and during high speed reproduction of main data, the control channel amplifier and the first and second control channels. The object of the present invention is to provide a magnetic recording / reproducing apparatus capable of obtaining an optimum reproducing characteristic by changing the frequency characteristic of the second main data channel amplifier group to the optimum characteristic.

[0042]

In order to solve the above-mentioned problems, the magnetic recording / reproducing apparatus of the present invention is designed to switch the frequency of the control channel amplifier by the output from the decoder means during high speed reproduction of only the control channel. The frequency of the control channel amplifier is changed by determining whether the frequency switching means 1 is operating or not, and at the time of high speed reproduction of the main data channel used for high speed dubbing,
The frequency characteristics of the control channel amplifier and the first and second main data channel amplifier groups are switched according to the state of the frequency switching terminal for inputting a signal indicating whether the reproduction state of the digital tape cassette is high speed reproduction or normal reproduction. By determining whether the second frequency switching means is operating or not and changing the frequency characteristics of the control channel amplifier and the first and second main data channel amplifier groups, it is possible to optimize the high speed reproduction and the normal reproduction. A characteristic control channel amplifier and first and second main data channel amplifier groups are provided.

[0043]

According to the present invention, the control channel for amplifying the output signal of the magnetic head during the normal reproduction which is the reproduction state of the digital tape cassette, the high speed reproduction of only the control channel and the high speed reproduction of the audio signal is constituted by the above-mentioned structure. First channel other than amplifier and control channel
Since the frequency characteristic of the second main data channel amplifier group can be set to the optimum state, the reproducing operation of the digital tape cassette can be stably and optimally performed regardless of the reproducing speed.

[0044]

Embodiments of the magnetic recording / reproducing apparatus of the present invention will be described in detail below with reference to FIGS.

FIG. 1 is a block diagram of a magnetic recording / reproducing apparatus according to the first embodiment of the present invention.

FIG. 1 shows the configuration of the digital reproducing / amplifying means 4 in the block diagram of the conventional magnetic recording / reproducing apparatus of FIG. The description thereof will be omitted.

In FIG. 1, 4 is a digital reproducing / amplifying means, and 11 is a decoder means, which is different from the conventional digital reproducing / amplifying means.

Reference numeral 8 is a control channel amplifier frequency switching means, 9 is a frequency switching means, 13 is a frequency switching terminal, the control channel amplifier frequency switching means 8 is connected to the output of the decoder means 11, and the control channel amplifier frequency switching means 8 is provided. Is connected to the control channel amplifier 5.

The frequency switching terminal 13 is connected to the output of the control means 20 and at the same time connected to the frequency switching means 9. The output of the frequency switching means 9 is connected to the control channel amplifier 5, the main data first stage amplifier group 6 and the main data second stage amplifier group 7.

The operation of the magnetic recording / reproducing apparatus having the above structure will be described below.

First, the operation of each component during normal reproduction is almost the same as that of the conventional example, but there is a difference in the frequency characteristic of the control channel amplifier 5. The control channel amplifier frequency switching means 8 is activated by the output of the decoder means 11 to which the timing signal in the normal reproduction state is input, and the control channel amplifier frequency switching means 8 is activated.
The output of the control channel amplifier 5 sets the frequency characteristic of the control channel amplifier 5 to a high-frequency cut first-order low-pass filter characteristic that passes only the control channel signal band in the normal reproduction state.

Further, the frequency characteristics of the main data first stage amplifier group 6 and the main data second stage amplifier group 7 are the same as those of the conventional example, but at this time, the frequency switching means 9 is in the operating state.

During high speed reproduction of only the control channel, the decoder means 11 outputs a signal to the parallel / serial conversion means 10 so as to output only the signal of the control channel amplifier 5, and at the same time the control channel amplifier frequency switching means 8 is deactivated. Put in a state. When the control channel amplifier frequency switching means 8 is in the non-operating state, the frequency characteristic of the control channel amplifier 5 is different from that in the normal reproducing state, and the high frequency cut is made to pass only the control channel signal band in the control channel high speed reproducing state. 1st order low pass filter characteristic.

Further, at the time of high speed reproduction of the main data channel used for high speed dubbing or the like, when the high speed reproduction operation switch 21n in the operating means 21 is pushed, the control means 20 is pressed.
The high-speed reproduction operation instruction signal is output to the control means 20, and the control means 20 outputs the high-speed reproduction operation signal to the mechanism control means 22 and also outputs the high-speed reproduction state signal to the frequency switching terminal 13 in the digital reproduction amplification means 5, and at the same time. The signal processing means 16 is brought into a high speed reproduction operation state. Mechanism control means 2
2 makes the tape mechanism 3 in which the digital tape cassette 1 is mounted operate at high speed. At this time, the signal recorded in the digital tape cassette 1 is the magnetic head 2
Is converted into a minute electric signal by the control channel amplifier 5 in the digital reproduction / amplification means 4 and the main data channel is amplified by the main data first stage amplifier group 6 in the digital reproduction / amplification means 4. At this time, the high-speed reproduction operation signal is also input to the frequency switching terminal 13, and by making the frequency switching means 9 inactive via the frequency switching terminal 13,
Control channel amplifier 5 and main data first stage amplifier group 6
The frequency characteristics of are set so as to match the reproduction signal band during high-speed reproduction. The frequency characteristics of the control channel amplifier 5 and the main data first-stage amplifier group 6 are primary low-pass filter characteristics for cutting the high band which is an unnecessary band.

The output signal of the main data first stage amplifier group 6 is further amplified by the main data second stage amplifier group 7, and is output to the parallel / serial conversion means 10 together with the output signal of the control channel amplifier 5. The frequency characteristic of the main data second stage amplifier group 7 is set so as to match the reproduction signal band at the time of high speed reproduction, as in the control channel amplifier 5 and the main data first stage amplifier group 6. The frequency characteristics of the second stage amplifier group 7 of the main data are the primary high-pass filter for correcting the frequency characteristics of the magnetic head 2 during high-speed reproduction and the high-frequency cut that is a reproduction signal unnecessary band during high-speed reproduction. It is a first-order low-pass filter characteristic.

On the other hand, the digital signal processing means 18 in the signal processing means 16 which is in the high speed reproduction operation by the output of the control means 20 outputs the high speed reproduction timing signal to the decoder means 11 in the digital reproduction amplifying means 4. The decoder means 11 outputs an output channel timing signal to the parallel / serial conversion means 10 for converting the plurality of outputs of the control channel amplifier 5 and the main data second stage amplifier group 7 into one signal which is time-divided. The frequency of the output channel timing signal at this time is high due to the high speed reproduction, but the order of the output channels is the same as in the normal reproduction.

The output of the parallel / serial conversion means 10 is a buffer amplifier 12, a variable resistor 14 for level adjustment, and D.
The signal is output to the A / D conversion means 17 in the signal processing means 16 through the C level cut coupling capacitor 15 to be converted from an analog signal to a digital signal and at the same time in the main data second stage amplifier group 7. The supplement of the frequency characteristic correction of the magnetic head 2 at the time of high-speed reproduction is further frequency characteristic corrected, and the phase is also corrected. A / D conversion means 1
The output of 7 is a digital signal, and the digital signal processing means 18 performs demodulation and error correction. The output of the digital signal processing means 18 is increased by the D / A conversion means 19 due to the high speed reproduction, but is converted into an analog reproduction signal.

Next, detailed circuits of the control channel amplifier 5, the control channel frequency switching means 8 and the decoder circuit 11 will be described with reference to FIG.

Since the structure of the control channel amplifier 5 is the same as that of the conventional example, its explanation is omitted. In the decoder circuit 11, 11a is a clock signal input terminal, 11b is a synchronization signal input terminal, 11c is a parallel-serial conversion timing generation circuit, 11d and 11e are D flip-flops, 11
f is a 3-input NAND circuit and has a clock signal input terminal 1
1a is a parallel / serial conversion timing generation circuit 11
c, connected to the clock input terminals of the D flip-flops 11d and 11e, the synchronization signal input terminal 11b has a parallel / serial conversion timing generation circuit 11c, the data input terminal of the D flip-flop 11d, and the first input of the 3-input NAND circuit 11f. The Q output terminal of the D flip-flop 11d is connected to the data input terminal of the D flip-flop 11e and the second input terminal of the 3-input NAND circuit 11f, and the Q output terminal of the D flip-flop 11e is 3 It is connected to the third input terminal of the input NAND circuit 11f.

Next, the configuration of the control channel amplifier frequency switching circuit 8 will be described. Q4 and Q5 are transistors forming a switching differential circuit, and have common emitters. I3 is a constant current source, one of which is connected to the common emitter of the transistors Q4 and Q5, and the other of which is connected to the power supply electrode. R4 and R5 are resistors, one of the resistors R4 and R5 is common and connected to the base of the transistor Q4, the other of the resistors R4 is connected to the power supply electrode, and the other of the resistors R5 is connected to the ground electrode. .

The base of the transistor Q5 is connected to the output of the 3-input NAND circuit 11f in the decoder means 11.

R6 and R7 are resistors, Q6 is a transistor,
C2 is a capacitor, one of the resistors R6 and R7 is common and connected to the collector of the transistor Q4, the other of the resistors R7 is connected to the ground electrode, and the other of the resistors R6 is connected to the base of the transistor Q6. . The emitter of the transistor Q6 is connected to the ground electrode, and the collector of the transistor Q6 is connected to one of the capacitors C2. The other of the capacitors C2 is the capacitor C1 in the control channel amplifier 5, the resistor R3 and the transistor Q3.
It is connected to the connection point with the base of.

The operation of the control channel amplifier 5, the control channel amplifier frequency switching means 8 and the decoder means 11 constructed as above will be described below.

Sync signal input terminal 11 of the decoder means 11
As shown in FIG. 4, a synchronization signal that determines the timing of the control channel and a clock signal that determines the selection timing of each channel are input to b and the clock signal input terminal 11a, and the left half of FIG. It is a signal in the normal reproduction state. At this time, which of the outputs of the control channel amplifier 5 and the plurality of outputs of the main data second stage amplifier group 7 input to the parallel / serial conversion means 10 is output by the parallel / serial conversion timing generation circuit 11c. A signal for determining whether to output to the buffer amplifier 12 in the subsequent stage is output to the parallel / serial conversion means 10.

In the decoder means 11, circuits other than the parallel / serial conversion timing generation circuit 11c are for detecting the high speed reproduction state of the control channel, and as shown in the timing chart of FIG. The input signal of 11f is a synchronization signal input terminal 11b, the Q output of the D flip-flop 11d, and the D flip-flop 11e.
Since there are three Q outputs and the three inputs do not simultaneously go to the high level, the output of the 3-input NAND 11f is always at the high level.

Since the output of the 3-input AND 11f which is the input signal of the control channel amplifier frequency switching means 8 is at high level, the base of the transistor Q5 also becomes high level. The base voltage of the other transistor Q4 forming the differential circuit is a potential obtained by dividing the power supply voltage by the resistors R4 and R5. When the resistance values of the resistors R4 and R5 are set to the same resistance value, the base of the transistor Q5 is set. The potential becomes 1/2 of the power supply voltage, and the transistor Q4 is turned on.

When the transistor Q4 is turned on, the collector current of the transistor Q4 flows and the transistor Q4
6 is also turned on. The resistor R7 is for preventing malfunction due to the collector leak current of the transistor Q4 when the transistor Q4 is in the off state, and the resistor R6 is a resistor for preventing an excessive base current when the transistor Q6 is in the on state.

When the transistor Q6 is turned on, the collector-emitter of the transistor Q6 has a low impedance, which is equivalent to a circuit in the control channel amplifier 5 in which the capacitor C2 is connected in parallel with the capacitor C1. The cut-off frequency f5n of the control channel amplifier 5 at this time is expressed by the following equation, where the capacitance value of the capacitor C2 is C2.

[0069]

[Equation 8]

Needless to say, the cutoff frequency f5n of the control channel amplifier 5 is set to the control channel reproduction signal band during normal reproduction and is 20 to 30 kHz.

In the high speed reproduction state of only the control channel, the sync signal is always at the high level in the sync signal input terminal 11b and the clock signal input terminal 11a of the decoder means 11 as shown in the right half of FIG. The same signal as that for normal reproduction is input as the signal. At this time, only the output of the control channel amplifier 5 input to the parallel / serial conversion means 10 is output by the parallel / serial conversion timing generation circuit 11c to the buffer amplifier 1 in the subsequent stage.
The signal to be output to 2 is output to the parallel / serial conversion means 10.

In the decoder means 11, circuits other than the parallel / serial conversion timing generation circuit 11c are for detecting the high speed reproduction state of only the control channel, and as shown in the timing chart of FIG. The input signal of the NAND circuit 11f is the synchronization signal input terminal 11b,
There are three outputs, the Q output of the D flip-flop 11d and the Q output of the D flip-flop 11e, and the output of the 3-input NAND 11f is always at the low level when the 3 inputs are simultaneously at the high level.

Since the output of the 3-input AND 11f which is the input signal of the control channel frequency switching means 8 is low level, the base of the transistor Q5 also becomes low level.
The base voltage of the other transistor Q4 forming the differential circuit is 1/2 of the power supply voltage as described above, and the transistor Q4 is turned off.

When the transistor Q4 is turned off, the collector current of the transistor Q4 does not flow and the transistor Q6 is also turned off. When the transistor Q6 turns on, the impedance between the collector and the emitter of the transistor Q6 becomes high, and the capacitor C2 connected to the collector of the transistor Q6 floats. At this time, the capacitor C2 is connected to the control channel amplifier 5
Does not affect. The cutoff frequency f5s of the control channel amplifier 5 is expressed by the following equation.

[0075]

[Equation 9]

Needless to say, the cutoff frequency f5s of the control channel amplifier 5 is set to the control channel reproduction signal band during high speed reproduction of only the control channel,
It is 300 to 500 kHz. FIG. 5 shows frequency characteristics during normal reproduction of the control channel amplifier and during high speed reproduction of only the control channel.

Next, the main data first stage amplifier 6a which is one of the main data first stage amplifier group 6, the main data second stage amplifier 7a which is one of the main data second stage amplifier group 7, and the frequency switching. Detailed circuit of means 9
Will be explained.

The configurations of the main data first-stage amplifier 6a and the main data second-stage amplifier 7a are the same as those of the conventional example, and therefore their explanations are omitted.

Reference numeral 13 is a frequency switching terminal, Q21 and Q22 are transistors constituting a switching differential circuit, and the emitters thereof are common. I10 is a constant current source, one of which is connected to the common emitter of the transistors Q21 and Q22, and the other of which is connected to the power supply electrode. R2
2, R23 are resistors, one of the resistors R22 and R23 is common and connected to the base of the transistor Q21, the other of the resistors R22 is connected to the power supply electrode, and the resistor R2.
The other of 3 is connected to the ground electrode.

The base of the transistor Q22 is connected to the frequency switching terminal 13. R15, R16, R2
0, R21, R24 are resistors, Q15, Q16, Q19,
Q20 is a transistor, C6, C7 and C8 are capacitors, and resistors R15, R16, R20 and R
21 and one of the resistor R24 are common, and the transistor Q2
1, the other end of the resistor R24 is connected to the ground electrode, the other end of the resistor R15 is connected to the base of the transistor Q15, and the other end of the resistor R16 is connected to the transistor Q15.
The other end of the resistor R20 is connected to the base of the transistor Q19, and the other end of the resistor R21 is connected to the base of the transistor Q20.

The emitters of the transistors Q15, Q16, Q20 are connected to the ground electrode, the collector of the transistor Q15 is connected to one of the capacitors C6, and the collector of the transistor Q16 is connected to one of the capacitors C7. The other of the capacitors C6 is a capacitor C1, a resistor R3, and a transistor Q in the control channel amplifier 5.
3 is connected to the connection point of the base, and the other side of the capacitor C7 is the capacitor C in the main data first stage amplifier 6a.
3, the resistor R10 and the base of the transistor Q9 are connected, and the other end of the capacitor C8 is connected to the connection of the base of the capacitor C5, the resistor R14 and the transistor Q14 in the main data second stage amplifier 7a. There is.

R17, R18 and R19 are resistors, Q17,
Q18 is a transistor, the base of the transistor Q17 and the base of the transistor Q18 are common, and the resistor R1
7 and the collector of the transistor Q19. The emitter of the transistor Q17 has R
18 is connected, one of R19 is connected to the emitter of the transistor Q18, and the transistors Q17, Q
The collector of 18 is connected to the power supply electrode.

The other end of the resistor R18 is connected to the connection point of the capacitor C4, the resistor R12, the base of the transistor Q10 and the constant current source I6 in the main data second stage amplifier 7a, and the other end of the resistor R19 is connected to the main data 2. Stage amplifier 7
It is connected to the connection point of the resistor R13 in a, the base of the transistor Q11, and the constant current source I7.

9b ... 9h are frequency switching means 9 shown in FIG.
, 9a in the main data first stage amplifier 6b, main data second stage amplifier 7b, ..., Main data first stage amplifier 6h Main data second stage amplifier 7
Although it is connected to h, the description is omitted here.

The operation of the main data first stage amplifier 6a, the main data second stage amplifier 7a and the frequency switching circuit 9 configured as described above will be described below.

During normal reproduction, a high level signal is output from the control means 20 to the frequency switching terminal 13, and the base of the transistor Q22 also becomes high level. The base voltage of the other transistor Q21 forming the differential circuit is a potential obtained by dividing the power supply voltage by the resistors R22 and R23, and when the resistance values of the resistors R22 and R23 are set to the same resistance value, the base of the transistor Q21 is set. The potential becomes 1/2 of the power supply voltage, and the transistor Q21 is turned on.

When the transistor Q21 is turned on,
The collector current of the transistor Q21 flows, and the transistors Q15, Q16, Q19 and Q20 are also turned on.
The resistor R24 is for preventing malfunction due to the collector leak current of the transistor Q21 when the transistor Q21 is in the off state, and the resistors R15, R16, R20, and R21 are the transistors Q15, Q16, Q19, and Q20, respectively.
This is a resistance for preventing an excessive base current when is on.

When the transistors Q15, Q16 and Q20 are turned on, the collector and
The impedance between the emitters is low, and the transistor Q
When the switch 15 is turned on, the capacitor C1 is connected in parallel with the capacitor C1 in the control channel amplifier 5 (FIG. 2).
It becomes equivalent to the circuit in which 6 is connected, and the transistor Q16 is turned on, so that the main data first stage amplifier 6a
Is equivalent to a circuit in which a capacitor C7 is connected in parallel with the capacitor C3 in the above, and a circuit in which a capacitor C8 is connected in parallel with the capacitor C5 in the main data second stage amplifier 7a by turning on the transistor Q20. Will be equivalent. At this time, the cutoff frequency f5m of the control channel amplifier 5, the cutoff frequency f6m of the main data first stage amplifier 6a, and the high cutoff frequency f7Hm of the main data second stage amplifier 7a are the capacitor C6,
When the capacitance values of C7 and C8 are C6, C7, and C8, respectively, they are expressed by the following equation.

[0089]

[Equation 10]

[0090]

[Equation 11]

[0091]

[Equation 12]

Needless to say, the cut-off frequency f5m of the control channel amplifier 5 is set to the control channel reproduction signal band during normal reproduction and is 20 to 30 kHz. Cutoff frequency f of main data first stage amplifier 6a
The cutoff frequency f7Hm of 6m and the main data two-stage amplifier 7a is set to the main channel reproduction signal band at the time of normal reproduction, and is 100 to 150 kHz.

At this time, the transistor Q19 is also in the ON state, the collector current of the transistor Q19 flows, and a voltage drop occurs due to the resistor R17. The base potentials of the transistors Q17 and Q18 are equal to the voltage drop of the resistor R11. A transistor Q17 having a voltage substantially equal to the potential obtained by subtracting the sum of the base-emitter voltage drop of the transistors Q12 and Q13 and the voltage drop due to the resistors R12 and R13 and the constant current sources I6 and I7 from the power supply voltage, The potential is sufficiently lower than the emitter potential of Q18. Therefore, the resistors R18 and R19 are in a floating state and do not affect the main data two-stage amplifier 7a. The low-frequency cutoff frequency f7Lm of the main data second stage amplifier 7a at this time is represented by the following equation.

[0094]

[Equation 13]

The cutoff frequency for frequency correction of the magnetic head output during normal reproduction is 50 to 100 kHz.
z.

During high speed reproduction such as high speed dubbing, a low level signal is output from the control means 20 to the frequency switching terminal 13 and the base of the transistor Q22 also becomes low level. The base potential of the other transistor Q21 forming the differential circuit is half the power supply voltage as described above,
The transistor Q21 is turned off.

When the transistor Q21 is turned off,
The collector current of the transistor Q21 does not flow and the transistors Q15, Q16, Q19 and Q20 are also turned off.

When the transistors Q15, Q16 and Q20 are turned off, the collector and
High impedance between the emitters and capacitor C
6, C7 and C8 are in a floating state and do not affect the control channel amplifier 5, main data first stage amplifier 6a and main data two stage amplifier 7a, respectively. At this time, the cutoff frequency f5k of the control channel amplifier 5, the cutoff frequency f6k of the main data first stage amplifier 6a, and the high cutoff frequency f7Hk of the main data second stage amplifier 7a are expressed by the following equations.

[0099]

[Equation 14]

[0100]

[Equation 15]

[0101]

[Equation 16]

Needless to say, the cutoff frequency f5k of the control channel amplifier 5 is set in the control channel reproduction signal band during high speed reproduction, and is 40 to 60 kHz when the reproduction speed is double speed. Main data first stage amplifier 6
The cut-off frequency f6k of a and the cut-off frequency f7Hk of the second stage main data amplifier 7a are set in the main channel reproduction signal band during high-speed reproduction, and are 200 to 300 kHz when the reproduction speed is double speed.

At this time, the transistor Q19 is also in the off state, the collector current of the transistor Q19 does not flow, and the transistors Q17 and Q18 are in the on state. Assuming that the resistance values of the resistors R12, R13, R18, and R19 are sufficiently larger than the output impedance of the emitter follower circuit composed of the transistors Q12, Q13, Q17, and Q18, the main data second stage amplifier 7a.
The input impedance of can be approximated to the impedance when the resistors R12 and R18 are connected in parallel. At this time, the cutoff frequency f7 of the low band of the main data second stage amplifier 7a
Lk is represented by the following equation.

[0104]

[Equation 17]

The cutoff frequency for frequency correction of the magnetic head output during normal reproduction is 100 to 200 k.
Hz. FIG. 6 shows the total frequency characteristics during normal reproduction and high-speed reproduction when the main data first-stage amplifier and the main data second-stage amplifier are connected. As for the frequency characteristic of the control channel amplifier, the cutoff frequency during normal reproduction is f
At 5 m, the cutoff frequency during high-speed reproduction is f5b, but the rest is similar to the frequency characteristic shown in FIG.

As described above, according to this embodiment, the frequency characteristic of the control channel amplifier is set to the optimum characteristic in accordance with the reproduction frequency of the control channel at the time of high speed reproduction of only the control channel, and at the time of high speed reproduction used for high speed dubbing or the like, The frequency characteristics of the control channel amplifier, the main data first-stage amplifier group, and the main data second-stage amplifier group can be optimized according to the reproduction frequency of each channel of the control channel and the main data.

[0107]

INDUSTRIAL APPLICABILITY As described above, the present invention is a magnetic recording / reproducing apparatus for a digital tape cassette capable of normal reproduction, high-speed reproduction of only control channels, and high-speed reproduction of audio signals, which is recorded in the digital cassette. A magnetic head with multiple channels for converting signals to electrical signals,
A control channel amplifier for amplifying the control channel output of a plurality of channels of the magnetic head, a first main data amplifier group for amplifying the remaining plural channel outputs, and an output of the first main data amplifier group. The connected second main data amplifier group, the first frequency switching means for changing the frequency characteristic of the control channel amplifier, the control channel amplifier and the second main data amplifier group output which are a plurality of signals, The time-division parallel / serial conversion means for making a serial signal, the decoder means for determining the timing of the parallel / serial conversion means and the operation of the first frequency switching means, and the reproduction state of the digital tape cassette are A frequency switching terminal for inputting a signal indicating high-speed playback or normal playback, and the control channel above. A channel amplifier and second frequency switching means for simultaneously changing the frequency characteristics of the first main data amplifier group and the second main data amplifier group, and for normal reproduction, high-speed reproduction of only the control channel, and audio. A control channel amplifier for amplifying a magnetic head output signal and first and second channels other than the control channel according to respective cases during high-speed reproduction of a signal.
Since the frequency characteristics of the main data channel amplifier group can be set to the optimum state, the reproduction operation characteristics of the digital tape cassette can be made stable and optimum regardless of the reproduction speed.

[Brief description of drawings]

FIG. 1 is a block diagram of a magnetic recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of a control channel amplifier, a control channel amplifier frequency switching means and a decoder means of the magnetic recording / reproducing apparatus in the present embodiment.

FIG. 3 is a detailed circuit diagram of a main data first-stage amplifier, main data second-stage amplifier, and frequency switching means of the magnetic recording / reproducing apparatus in the present embodiment.

FIG. 4 is a timing chart showing the timing of the input signal to the decoder means and the internal circuit of the magnetic recording / reproducing apparatus in this embodiment.

FIG. 5 is a frequency characteristic diagram of a control channel amplifier of the magnetic recording / reproducing apparatus according to the present embodiment.

FIG. 6 is an overall frequency characteristic diagram when the main data first stage amplifier and the main data second stage amplifier of the magnetic recording / reproducing apparatus in the present embodiment are connected.

FIG. 7 is a block diagram of a conventional magnetic recording / reproducing device.

FIG. 8 is a detailed circuit diagram of a control channel amplifier, a main data first stage amplifier, and a main data second stage amplifier of a conventional magnetic recording / reproducing apparatus.

[Explanation of symbols]

 1 Digital Tape Cassette 2 Magnetic Head 3 Tape Mechanism 4, 4'Digital Reproducing / Amplifying Means 5 Control Channel Amplifier 6 Main Data First Stage Amplifier Group 6a Main Data First Stage Amplifier 7 Main Data Second Stage Amplifier Group 7a Main Data Second Stage Amplifier 8 Control Channel amplifier frequency switching means 9 Frequency switching means 10 Parallel / serial conversion means 11, 11 'Decoder means 12 Buffer amplifier 13 Frequency switching terminal 14 Resistor 15 Capacitor 16 Signal processing means 17 A / D conversion means 18 Digital signal processing means 19 D / A conversion means 20 control means 21 operation means 21a reproduction operation switch 21b search operation switch 21n high speed reproduction operation switch 22 mechanism control means

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hiroyuki Hayashita 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (2)

[Claims] 1. A magnetic recording / reproducing apparatus for reproducing a digitally recorded digital tape cassette, comprising: a magnetic head having a plurality of channels for converting a signal recorded in the digital cassette into an electric signal; A control channel amplifier for amplifying a control channel output of a plurality of channels, a first main data amplifier group for amplifying the remaining plural channel outputs, and an output of the first main data amplifier group. A second main data amplifier group, a first frequency switching means for changing the frequency characteristic of the control channel amplifier, a plurality of signals of the control channel amplifier and the output of the second main data amplifier group are time-shared. Parallel-serial conversion means for converting the serial signal to a serial signal, and the parallel-serial conversion means And a decoder means for determining the operation of the first frequency switching means and changing the frequency characteristic of the control channel amplifier during high speed reproduction and normal reproduction of the digital tape cassette. Recording / playback device. 2. A frequency switching terminal for inputting a signal indicating whether the reproduction status of the digital tape cassette is high speed reproduction or normal reproduction, the control channel amplifier, the first main data amplifier group, and the second main. A second frequency switching means for simultaneously changing the frequency characteristics of the data amplifier group, and depending on the state of the frequency switching terminal, the control channel amplifier and the first channel during high speed reproduction and normal reproduction of the digital tape cassette. 2. The magnetic recording / reproducing apparatus according to claim 1, wherein the frequency characteristics of the main data amplifier group and the second main data amplifier group are simultaneously changed.