JPH06161711A - Full-adder - Google Patents

Abstract

PURPOSE:To provide the full-adder which performs arithmetic operation at a high speed without increasing the number of transistors(TR) and is low in power consumption. CONSTITUTION:This full-adder which outputs a sum signal and a carry signal when a 1st, a 2nd, and a 3rd input signal are inputted is equipped with a 1st arithmetic part 1 which generates an exclusive OR signal D between the 1st input signal A and 2nd input signal B and the NOT signal of the exclusive OR signal and a 2nd arithmetic part 6 which generates the sum signal E and the NOT signal of the sum signal by selecting the 3rd input signal C or the NOT signal of the 3rd input signal by using the exclusive OR signal D and the NOT signal of the exclusive OR signal. Further, the full-adder is equipped with a 3rd arithmetic part 15 which generates the carry signal F and the NOT signal of the carry signal by selecting the 1st input signal A and the NOT signal of the signal A or the 3rd input signal C or its NOT signal by using the exclusive OR signal D and its NOT signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full adder, and more particularly to a full adder for generating a sum signal and a carry signal complementary to complementary input signals.

[0002]

2. Description of the Related Art FIGS. 2 and 3 are circuit diagrams of a conventional full adder that handles complementary input / output signals. FIG. 2 shows a sum signal generating portion thereof, and FIG. 3 shows a carry signal generating portion thereof. In FIG. 2, the first arithmetic unit 24, the second arithmetic unit 29, and the third arithmetic unit 3
6, the fourth arithmetic unit 41, the fifth arithmetic unit 46, 4
N-type field effect transistors 25-28, 30-3
3, 37-40, 42-45, 47-50. Further, output inverters 34, 35 and 51, 52 are added to the second arithmetic unit 29 and the fifth arithmetic unit 46, respectively. In the full adder shown in FIG. 2 and FIG. 3, the first input signal A, the second input signal B, the third input signal C, and respective negative signals are input as input signals, The third calculation unit 36 and the fourth calculation unit 41 respectively output two intermediate outputs G and a negative signal of G, a negative signal of H and H, and a negative signal of I and I,
The sum signals E and the negative signal of E and the carry signals F and the negative signal of F at the time of addition of A, B, and C are output as output signals.

Next, the operation of FIG. 2 will be described. First computing unit 2
4, when A is at a high level, the N-type field effect transistors 26 and 27 are turned on to output the negative signals of B and B to the negative signals of G and G, respectively. The effect transistors 25 and 28 are turned on, and the negative signal of B and the negative signal of B are output to the negative signals of G and G, respectively. If this is expressed by a logical expression,

[0004]

[Equation 1]

[0005] Further, in the second arithmetic unit 29, when C is at a high level, the N-type field effect transistor 3
0 and 33 become conductive, and the negative signals of G and G are respectively E
And the negative signals of E, and when C is at a low level, the N-type field effect transistors 31 and 32 are turned on to output the negative signals of G and G to the negative signals of E and E, respectively.
If this is expressed by a logical expression,

[0006]

[Equation 2]

Thus, E and the negative signal of E become the sum signal and the negative signal of the sum signal when A, B, and C are added, respectively.

Next, the operation of FIG. 3 will be described. Similar to FIG. 2, the intermediate outputs H, H of the third arithmetic unit 36 with respect to the input signals A, B, C and the intermediate output I of the fourth arithmetic unit 41, the negative signal of I, and the output signals F, F If the negative signal is expressed by a logical expression,

[0009]

[Equation 3]

[0010]

[Equation 4]

Therefore, the negative signals of F and F become the carry signal and the negative signal of the carry signal when A, B, and C are added, respectively.

As described above, in the full adders shown in FIGS. 2 and 3, a complementary sum signal and carry signal are obtained with respect to three complementary input signals.

[0013]

In FIG. 2 and FIG. 3,
Intermediate output G, negative signal of G, H, negative signal of H, I, I
The maximum value of the voltage of the Negative signal is greater than the maximum value of the voltage of the input signal A, the negative signal of A, the negative signal of B, B, and the negative signal of C, C The maximum value of the voltage at the input terminals of the inverters 34, 35, 51, 52 is also decreased by that amount. Therefore, the fall of the outputs of the inverters 34, 35, 51, 52 is delayed, and at the same time, the inverters 34, 35, 51,
Since a through current flows through the transistor forming 52, power consumption increases. One possible solution to this problem is to use a transfer gate composed of an N-type field effect transistor and a P-type field effect transistor instead of the transfer gate composed of an N-type field effect transistor. The number doubles and the circuit scale increases.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a full adder which can perform high-speed operation without increasing the number of transistors and has low power consumption.

[0015]

A full adder of the present invention is a full adder which outputs a sum signal and a carry signal in response to inputs of first, second and third input signals, A first arithmetic unit for generating an exclusive OR signal and an exclusive OR NOT signal of the first and second input signals, and a first operation unit using the exclusive OR signal and the exclusive OR NOT signal A second operation unit that generates a sum signal and a negation signal of the sum signal by selecting the third input signal or the negation signal of the third input signal, and the exclusive OR signal and the negation of the exclusive OR. The carry signal and the negate signal of the carry signal are selected by using the signal to select the first input signal and the negation signal of the first input signal or the third input signal and the negation signal of the third input signal. And a third operation unit for generating the second operation. And at least one of the third arithmetic units includes four sets of transfer gates including an N-type field effect transistor and a P-type field effect transistor, and two sets of the transfer gates are provided when the exclusive OR signal is at a high level. A full adder characterized in that the transfer gate is turned on and the other two sets of transfer gates are turned on when the exclusive OR signal is at a low level.

The first arithmetic unit is composed of four N-type field effect transistors, and the two N-type field effect transistors whose gate electrodes are supplied with the first input signal are electrically connected to each other, whereby The negative signal of the second input signal and the second input signal are output as the exclusive OR signal and the negative signal of the exclusive OR signal, respectively, and the negative signal of the first input signal is input to the gate electrode. When the two N-type field effect transistors become conductive, the second input signal and the negative signal of the second input signal are output as the exclusive OR signal and the negative signal of the exclusive OR signal, respectively. May be configured as.

Further, the second arithmetic unit is configured such that, when the exclusive OR signal is at a high level, the two sets of transfer gates become conductive, so that the negative signal of the third input signal and the third input signal. Are output as the sum signal and a negation signal of the sum signal, respectively, and when the exclusive OR signal is at a low level, the other two sets of transfer gates are turned on, so that the third input signal and the third input signal A negative signal of the input signal may be output as the sum signal and a negative signal of the sum signal, respectively.

In addition, the third arithmetic unit conducts the two sets of transfer gates when the exclusive OR signal is at a high level, so that the third input signal and the negative signal of the third input signal. Are output as the carry signal and a negation signal of the carry signal, respectively, and when the exclusive OR signal is at a low level, the other two sets of transfer gates become conductive, and the first input signal and the first input signal The negative signal of the input signal 1 may be output as the carry signal and the negative signal of the carry signal, respectively.

Further, the third arithmetic unit may use the second input signal and the negative signal of the second input signal instead of the first input signal and the negative signal of the first input signal. .

[0020]

In the full adder of the present invention, since the maximum value of the voltage at the input terminal of the inverter can be made equal to the maximum value of the voltage of the input signal by using the transfer gate, the fall of the output of the inverter becomes faster, and at the same time, Since it is possible to prevent a through current from flowing through the transistor forming the inverter, the power consumption is reduced. Moreover, since the number of arithmetic units can be reduced, the number of transistors does not increase even if the transfer gate is used.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit diagram of a full adder according to an embodiment of the present invention. The first calculation unit 1 is composed of four N-type field effect transistors 2 to 5, and the second calculation unit 6 is N-type.
Sets of transfer gates 9 to 12 and 2 each composed of a P-type field effect transistor 7 and a P-type field effect transistor 8
The third calculation unit 1 is composed of two inverters 13 and 14.
Reference numeral 5 denotes four pairs of transfer gates 1 each including an N-type field effect transistor 16 and a P-type field effect transistor 17.
8 to 21 and two inverters 22 and 23.

In FIG. 1, a first input signal A, a second input signal B, a third input signal C, and respective negative signals are input, and two intermediate outputs D from the first arithmetic unit 1 are input.
And D negation signals are output, and the sum signals E and E negation signals and carry signals F and F negation signals when adding A, B, and C are output.

In the first arithmetic unit 1, the second input signal B
Is connected to the drains of N-type field effect transistors 3 and 5. The negative signal of the second input signal B is connected to the drains of the N-type field effect transistors 2 and 4. The first input signal A is connected to the gates of N-type field effect transistors 2 and 5. The negative signal of the first input signal A is connected to the gates of the N-type field effect transistors 3 and 4. The negative signals of the outputs D and D of the first calculation unit 1 are the exclusive OR signal of the first input signal A and the second input signal B and the negative signal of the exclusive OR signal.

In the second arithmetic unit 6, the third input signal C
Is connected to the drains of transfer gates 9 and 12. The negative signal of the third input signal C is connected to the drains of the transfer gates 10 and 11. The output D of the first arithmetic unit 1 is connected to the gates of N-type field effect transistors forming the transfer gates 9 and 11. Similarly, the output D is the transfer gates 10 and 12
Is connected to the gate of the P-type field effect transistor constituting the. The negative signal of the output D of the first operation unit 1 is connected to the gates of the N-type field effect transistors forming the transfer gates 10 and 12. Similarly, the negative signal of the output D is P which constitutes the transfer gates 9 and 11.
Type field effect transistor is connected to the gate. The sources of the transfer gates 9 and 10 are the inverter 1
3 are connected to the input terminals. The sources of the transfer gates 11 and 12 are connected to the input terminal of the inverter 14.

In the third arithmetic unit 15, the first input signal A is connected to the drain of the transfer gate 21. The negative signal of the first input signal A is connected to the drain of the transfer gate 19. The third input signal C is connected to the drain of the transfer gate 20. The negative signal of the third input signal C is connected to the drain of the transfer gate 18. The output D of the first arithmetic unit 1 is connected to the gates of N-type field effect transistors forming the transfer gates 18 and 20. Similarly, the output D is the transfer gates 19 and 2.
1 is output to the gate of the P-type field effect transistor. The negative signal of the output D of the first operation unit 1 is connected to the gates of the N-type field effect transistors forming the transfer gates 19 and 21. Similarly output D
Is connected to the gates of the P-type field effect transistors forming the transfer gates 18 and 20. The sources of the transfer gates 18 and 19 are connected to the input terminal of the inverter 22. The sources of the transfer gates 20 and 21 are connected to the input terminal of the inverter 23.

Next, the operation of the full adder according to this embodiment will be described. In the first arithmetic unit 1, when A is at a high level, the N-type field effect transistors 2 and 5 are turned on to output B negative signals and B negative signals D and D, respectively.
Is low level, the N-type field effect transistors 3 and 4 are turned on and the negative signals of B and B are output as the negative signals of D and D, respectively. If this is expressed by a logical expression,

[0027]

[Equation 5]

Thus, the negative signals of D and D become the exclusive OR signal of A and B and the negative signal of the exclusive OR signal, respectively.

In the second operation unit 6, when D is at high level, the transfer gates 9 and 11 become conductive and C
The negative signal of C and the negative signal of C are output to the negative signals of E and E, respectively, and when D is at the low level, the transfer gate 10
And 12 are turned on, the negative signals of C and C are output to the negative signals of E and E, respectively. If this is expressed by a logical expression,

[0030]

[Equation 6]

Thus, E and the negation signal of E become the sum signal and the negation signal of the sum signal when A, B, and C are added, respectively.

In the third operation section 15, when D is at high level, the transfer gates 18 and 20 are turned on to output negative signals of C and C to negative signals of F and F, respectively, and when D is at low level. Transfer gate 19
And 21 become conductive and the negative signals of A and A are output to the negative signals of F and F, respectively. If this is expressed by a logical expression,

[0033]

[Equation 7]

The F and F negation signals are the carry signal and the negation signal of the carry signal when A, B and C are added, respectively.

As described above, the complementary sum signal and carry signal can be obtained with respect to the three complementary input signals.

In FIG. 1, the maximum value of the voltage of the negative signals of the intermediate outputs D and D is smaller than the maximum value of the voltage of the negative signals of the input signals B and B by the threshold value of the N-type field effect transistor. However, since the transfer gate is composed of the N-type field effect transistor and the P-type field effect transistor, the inverters 13, 14, 2
The maximum value of the voltage of the input terminals 2 and 23 is equal to the maximum value of the voltage of the input signals A, the negative signal of A, the negative signals of B and B, and the negative signals of C and C. Therefore, the inverters 13, 1
Outputs 4, 22, and 23 fall faster than in the conventional example shown in FIGS.
Since it is difficult for a through current to flow through the transistors forming 4, 22, and 23, power consumption is reduced. Also, in FIG.
The number of operation units in the conventional example of FIG. 3 is 5, whereas the number of operation units is as small as 3. Therefore, a transfer gate including an N-type field effect transistor and a P-type field effect transistor is used. The number of transistors required is 20, which is the same as the conventional example shown in FIGS.

In the third operation section 15, the inputs of the transfer gates 19 and 21 are set to A and the negative signal of A, respectively. However, the same result can be obtained by using the negative signals of B and B instead.

[0038]

According to the present invention, there is provided a first arithmetic unit for generating an exclusive OR of the first and second input signals and a NOT signal of the exclusive OR, and the exclusive OR signal and the NOT signal of the exclusive OR. By selecting a third input signal or a negative signal of the third input signal by using, a second arithmetic unit for generating a sum signal and a negative signal of the sum signal, and the exclusive OR signal and the exclusive OR signal A carry signal and a carry signal by selecting the first input signal and the negative signal of the first input signal or the third input signal and the negative signal of the third input signal by using the negative signal of the logical sum. And a third operation unit for generating a negative signal of the second operation unit and the third operation unit.
At least one of the operation units includes four sets of transfer gates including an N-type field effect transistor and a P-type field effect transistor, and the two sets of transfer gates become conductive when the exclusive OR signal is at a high level. However, when the exclusive OR signal is at a low level, the other two sets of transfer gates become conductive,
The maximum value of the input terminal of the inverter can be made equal to the maximum value of the voltage of the input signal, the fall of the output of the inverter becomes faster, and at the same time it is possible to prevent the through current from flowing through the transistor that constitutes the inverter, thus reducing the power consumption. Become.
Therefore, it is possible to provide a full adder that can perform high-speed calculation without increasing the number of transistors and that has low power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a full adder according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a sum signal generating portion of a conventional full adder.

FIG. 3 is a circuit diagram of a carry signal generation portion of a conventional full adder.

[Explanation of symbols]

1, 6, 15, 24, 29, 36, 41, 46 Operation part 2-5, 7, 16, 25-18, 30-33, 37-4
0, 42-45, 47-50 N-type field effect transistor 8,17 P-type field effect transistor 9-12, 18-21 Transfer gate 13, 14, 22, 23, 34, 35, 51, 52 Inverter

Claims (5)

[Claims] 1. A full adder that outputs a sum signal and a carry signal in response to inputs of first, second, and third input signals, the exclusive logic of the first and second input signals. A first operation unit that generates a sum signal and a negative signal of the exclusive OR, and a third input signal or a negative of the third input signal using the exclusive OR signal and the negative signal of the exclusive OR A second arithmetic unit that generates a sum signal and a negative signal of the sum signal by selecting a signal, and a first input signal and a first input signal using the exclusive OR signal and the negative signal of the exclusive OR. A negative signal of the input signal or a third input signal and a negative signal of the third input signal, thereby generating a carry signal and a negative signal of the carry signal. At least a second arithmetic unit and the third arithmetic unit One includes four sets of transfer gates each including an N-type field effect transistor and a P-type field effect transistor, and when the exclusive OR signal is at a high level, the two sets of transfer gates are conductive and the exclusive logic A full adder characterized in that the other two sets of transfer gates become conductive when the sum signal is at a low level. 2. The first arithmetic unit is composed of four N-type field effect transistors, and when the two N-type field effect transistors to which the first input signal is input to the gate electrode are made conductive, The negative signal of the second input signal and the second input signal are output as the exclusive OR signal and the negative signal of the exclusive OR signal, respectively, and the negative signal of the first input signal is input to the gate electrode. When the two N-type field effect transistors become conductive, the second input signal and the negative signal of the second input signal are output as the exclusive OR signal and the negative signal of the exclusive OR signal, respectively. The full adder according to claim 1, wherein the full adder is configured as follows. 3. The negation signal of the third input signal and the third input signal in the second arithmetic unit when the two sets of transfer gates become conductive when the exclusive OR signal is at a high level. Are output as the sum signal and a negation signal of the sum signal, respectively, and when the exclusive OR signal is at a low level, the other two sets of transfer gates are turned on, so that the third input signal and the third input signal The full adder according to claim 1, wherein a negative signal of the input signal is output as the sum signal and a negative signal of the sum signal, respectively. 4. The third arithmetic unit is configured such that, when the exclusive OR signal is at a high level, the two sets of transfer gates are turned on so that a third input signal and a negative signal of the third input signal. Are output as the carry signal and a negation signal of the carry signal, respectively, and when the exclusive OR signal is at a low level, the other two sets of transfer gates become conductive, and the first input signal and the first input signal 2. The full adder according to claim 1, wherein a negative signal of the input signal of 1 is output as the carry signal and a negative signal of the carry signal, respectively. 5. The third arithmetic unit uses a second input signal and a negative signal of the second input signal instead of the first input signal and the negative signal of the first input signal. The full adder according to claim 1.