JPH06152577A - Clock output circuit - Google Patents

Abstract

PURPOSE:To surely detect a signal disconnection in a reception input terminal while ensuring the generation of output signal with the duty ratio of 50% at the normal time. CONSTITUTION:A transmission ECL logic circuit 3 outputs an in-phase output signal for an input signal. A reception ECL logic circuit 9 takes a signal based on a signal sent from a transmission side through a co-axial cable 7 as an input signal, outputting a positive phase output signal and negative phase output signal for the input signal. A terminal resistance 13 connects the power source of a control voltage VTH. and the input of the reception ECL logic circuit 9 so that the input bias of the circuit 9 becomes a level separated more than the noise level from a threshold value. A reception averaging circuit 12 averages the negative phase output signal of the circuit 9 and generates the dc components. A transmission adder 15 superimposes the DC component returned to the transmission side as an input bias to the input signal of the circuit 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock output circuit in a digital data transmission system, and more particularly to ECL.
The present invention relates to a clock output circuit using an (Emitter Coupled Logic) logic circuit.

[0002]

2. Description of the Related Art In a digital data transmission system, two subsystems for transmitting and receiving via a coaxial cable (transmitter side subsystem (transmitter side device, etc .; hereinafter simply referred to as "transmitter side") and receiver side subsystem (receiver) A device on the side, etc., which is a clock output circuit realized simply on the "reception side" hereinafter, and uses a clock output circuit (ECL logic circuit) that outputs a clock signal with a duty ratio of 50% on the reception side. Clock output circuit)
think about.

Conventionally, this type of clock output circuit is shown in FIG.
Was configured as shown in. That is, this clock output circuit has an input terminal 1'and a post-filter terminal 2 '.
A transmitter ECL logic circuit 3 ', a transmitter positive phase output terminal 4', a transmitter negative phase output terminal 5 ', a transmitter averaging circuit 6', a coaxial cable 7 ', and a receiver input terminal. 8 ',
A receiving side ECL logic circuit 9 ', a positive phase output terminal 10',
It includes a negative phase output terminal 11 ', a receiving side averaging circuit 12', a low pass filter 14 ', a transmitting side adding circuit 15', a receiving side adding circuit 16 ', and a disconnection detecting circuit 17'. Was configured. Further, V _EE indicates the power supply voltage (DC voltage).

In the conventional clock output circuit shown in FIG. 3,
The following operations were performed.

The low pass filter 14 'has an input terminal 1'.
Signal (the input signal of the clock output circuit shown in FIG. 3) is input, and the signal in which the high frequency component of the signal is blocked is output to the terminal 2'after passing the filter.

The transmission side ECL logic circuit 3'inputs the signal at the terminal 2'after passing the filter, and outputs the positive phase output signal and the negative phase output signal for the signal (the input side ECL logic circuit 3'input signal). Output both. That is, the input signal is at the H (High) level (transmitting side ECL logic circuit 3 '
If it is a signal of a level higher than the threshold value of, the H-level positive phase output signal and the L (Low) level negative phase output signal are output, and the input signal is at the L level (lower than the threshold value). (Level) signal, L level positive phase output signal and H
It outputs the opposite phase output signal of the level. As described above, the transmission side ECL logic circuit 3'is an ECL logic circuit capable of outputting the output signals of both the positive and negative phases with respect to the input signal.

The transmitting side averaging circuit 6'averages the negative phase output signal of the transmitting side ECL logic circuit 3 '(the signal at the transmitting side negative phase output terminal 5').

The DC component after being averaged by the transmitting side averaging circuit 6'works as an input bias of the transmitting side ECL logic circuit 3 '. That is, the transmitting side adder circuit 15 '
Superimposes this input bias on the signal at the terminal 2 '(the input signal of the transmission side ECL logic circuit 3') after passing through the filter.

The input bias acts as follows to adjust the duty ratio of the output signals (the positive phase output signal and the negative phase output signal) of the transmission side ECL logic circuit 3'to 50%.

When the duty ratio of the signal at the transmission side negative phase output terminal 5 ′ is smaller than 50% due to the duty ratio of the signal at the input terminal 1 ′ being larger than 50%, the transmission side ECL logic circuit 3 The input bias of ′ becomes low, the possibility that the level of the input signal of the transmitting side ECL logic circuit 3 ′ becomes H level decreases, and the duty ratio of the signal at the transmitting side negative phase output terminal 5 ′ becomes large (transmitting side). The duty ratio of the signal at the positive phase output terminal 4'is small).

When the duty ratio of the signal at the transmission side negative phase output terminal 5 ′ is larger than 50% due to the duty ratio of the signal at the input terminal 1 ′ being smaller than 50%, the transmission side ECL logic circuit 3 The input bias of ′ becomes high, the possibility that the level of the input signal of the transmitting side ECL logic circuit 3 ′ becomes H level increases, and the duty ratio of the signal at the transmitting side anti-phase output terminal 5 ′ becomes small (transmitting side). The duty ratio of the signal at the positive phase output terminal 4'becomes large).

As a result of the above operations, the duty ratio of the signal at the transmission side positive phase output terminal 4'connected to the coaxial cable 7'is maintained at 50%.

The signal input to the receiving side input terminal 8'is
The signal at the transmission-side positive-phase output terminal 4 '(a signal whose duty ratio is maintained at 50% as described above) becomes a signal degraded by the frequency characteristic of the coaxial cable 7'.

The receiving side ECL logic circuit 9'receives such a signal and outputs both a positive phase output signal and a negative phase output signal corresponding to the signal (input signal of the receiving side ECL logic circuit 9 '). . That is, if the input signal is an H level signal (a level higher than the threshold value of the receiving side ECL logic circuit 9 '), an H level positive phase output signal and an L level negative phase output signal are output, If the signal is an L level signal (a level lower than the threshold value), an L level positive phase output signal and an H level negative phase output signal are output. Thus, the receiving side ECL logic circuit 9'is
Similar to the L logic circuit 3 ', this is an ECL logic circuit capable of outputting output signals of both positive and negative phases with respect to an input signal.

The receiving side averaging circuit 12 'is a receiving side ECL.
The negative phase output signal of the logic circuit 9 '(the signal at the negative phase output terminal 11') is averaged.

The DC component after being averaged by the receiving side averaging circuit 12 'serves as an input bias of the receiving side ECL logic circuit 9'. That is, the receiving side adder circuit 16 '
Superimposes this input bias on the signal at the receiving side input terminal 8 '(the input signal of the receiving side ECL logic circuit 9').

This input bias acts in the same manner as the input bias in the transmission side ECL logic circuit 3 ', and the duty ratio of the output signals (the positive phase output signal and the negative phase output signal) of the reception side ECL logic circuit 9'is determined. Work to adjust to 50%. As a result, the duty ratio of the normal phase output signal of the receiving side ECL logic circuit 9 '(the signal at the normal phase output terminal 10'), that is, the output signal of the clock output circuit shown in FIG. 3 is maintained at 50%.

Now, let us consider the operation of the conventional clock output circuit when a signal disconnection occurs at the receiving side input terminal 8'due to the disconnection or unconnection of the coaxial cable 7 '.

In this case, due to the feedback action of the receiving side averaging circuit 12 'and the receiving side addition circuit 16', the receiving side E
The level of the input bias of the CL logic circuit 9'is EC on the receiving side.
It becomes the threshold level of the L logic circuit 9 '.

On the other hand, a noise signal (generally an irregular signal having a weak level) may be mixed in the input side of the receiving side ECL logic circuit 9 '.

Therefore, when the signal disconnection occurs at the receiving side input terminal 8 ', the above-mentioned noise is caused due to the level of the input bias of the receiving side ECL logic circuit 9'being the threshold level. A noise signal (an unstable signal which becomes H level or L level) based on the signal is output to the positive phase output terminal 10 'and the negative phase output terminal 11'.

The presence of this noise signal hinders the output of an alarm (alarm warning the signal disconnection at the receiving side input terminal 8 ') by the disconnection detection circuit 17' connected to the negative phase output terminal 11 '. It also becomes a factor that causes.

[0023]

In the conventional clock output circuit described above, a noise signal obtained by amplifying a noise signal mixed in the input signal of the ECL logic circuit on the receiving side when a signal disconnection occurs on the input terminal on the receiving side is generated. Since it is output to the output side of the reception side ECL logic circuit, the output signal of the reception side ECL logic circuit does not become a fixed level (it becomes unstable by becoming H level or L level). There is a drawback that it is difficult to detect a signal break in the side input terminal (there is no certainty in detecting the signal break).

In view of the above points, an object of the present invention is to ensure that an output signal having a duty ratio of 50% is generated in a normal state, and to receive the ECL logic circuit on the receiving side even if a signal disconnection occurs at the input terminal on the receiving side. It is an object of the present invention to provide a clock output circuit capable of surely detecting the signal disconnection by preventing a noise signal from being output to the output side of the.

[0025]

A clock output circuit according to the present invention uses a low-pass filter for cutting off a high-pass component of a signal at an input terminal, and an output signal of the low-pass filter as an input signal for the input signal. A transmitting-side ECL logic circuit that outputs a positive-phase output signal, a coaxial cable that transmits a signal at a transmitting-side output terminal based on the positive-phase output signal of the transmitting-side ECL logic circuit to the receiving side, and a coaxial cable from the transmitting side Receiving side E that takes a signal based on the signal at the receiving side input terminal that has been transmitted as an input signal and outputs a positive-phase output signal and a negative-phase output signal for the input signal
The CL logic circuit and a control voltage supply source and the reception side ECL logic circuit are set so that the input bias of the reception side ECL logic circuit becomes a level separated from the threshold value of the reception side ECL logic circuit by a noise level or more. A terminating resistor for connecting the input side, and a receiving side averaging circuit for averaging the negative phase output signal of the receiving side ECL logic circuit to generate a DC component.
The receiving side adder circuit for returning the DC component generated by the receiving side averaging circuit to the transmitting side, and the DC component returned to the transmitting side by the function of the receiving side adding circuit for input bias of the transmitting side ECL logic circuit. As the sending EC
A transmitting-side adder circuit for superimposing on the input signal of the L logic circuit;
A transmitting high-pass filter that blocks the DC component of the signal between the transmitting ECL logic circuit and the transmitting output terminal, and a DC component of the signal between the receiving input terminal and the receiving ECL logic circuit. An alarm indicating a signal loss by detecting a signal loss at the input terminal of the receiving side on the basis of the receiving high-pass filter for blocking and the recognition that the output signal of the receiving-side ECL logic circuit becomes a fixed level. A reception side disconnection detection circuit that outputs, and a transmission side averaging circuit that averages the output signals of the transmission side high-pass filter when a signal disconnection occurs at the reception side input terminal and passes it to the transmission side addition circuit, A transmission side disconnection detection circuit that detects a signal disconnection at the reception side input terminal based on the recognition that the output signal of the transmission side high-pass filter has a fixed level, and outputs an alarm indicating the signal disconnection. A.

[0026]

In the clock output circuit of the present invention, the low-pass filter cuts off the high-frequency component of the signal at the input terminal, and the transmission side ECL logic circuit uses the output signal of the low-pass filter as the input signal and corrects the input signal. Output the phase output signal,
The coaxial cable transmits to the receiving side the signal at the transmitting side output terminal based on the positive phase output signal of the transmitting side ECL logic circuit,
The ECL logic circuit on the receiving side uses the signal based on the signal at the input terminal on the receiving side transmitted from the transmitting side by the coaxial cable as an input signal, outputs a positive phase output signal and a negative phase output signal corresponding to the input signal, and the terminating resistor receives the signal. Side ECL
The control voltage supply source is connected to the input side of the reception side ECL logic circuit so that the input bias of the logic circuit becomes a level separated from the threshold value of the reception side ECL logic circuit by a noise level or more, and the reception side averaging is performed. The circuit averages the negative-phase output signal of the reception side ECL logic circuit to generate a DC component, the reception side addition circuit returns the DC component generated by the reception side averaging circuit to the transmission side, and the transmission side addition circuit The DC component returned to the transmission side by the function of the reception side addition circuit is transmitted to the transmission side EC
The input bias of the L logic circuit is superposed on the input signal of the transmission side ECL logic circuit, and the transmission side high-pass filter blocks the DC component of the signal between the transmission side ECL logic circuit and the transmission side output terminal, and the reception side. The high-pass filter blocks the DC component of the signal between the receiving-side input terminal and the receiving-side ECL logic circuit, and the receiving-side disconnection detection circuit keeps the output signal of the receiving-side ECL logic circuit at a fixed level. Based on the recognition, it detects a signal loss at the receiving side input terminal and outputs an alarm indicating the signal loss, and when the transmitting side averaging circuit has a signal loss at the receiving side input terminal, the transmitting side high-pass filter The output signal of the receiver is averaged and passed to the adder circuit on the transmitter side, and the disconnection detection circuit on the transmitter side recognizes that the output signal of the high-pass filter on the transmitter side has a fixed level, and disconnects the signal at the input terminal on the receiver side. Out and outputs an alarm indicating the effect of a signal break in.

[0027]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the clock output circuit of the present invention.

The clock output circuit of this embodiment includes an input terminal 1, a post-filter terminal 2 and a transmitting side ECL logic circuit 3 (H when the input signal is at H level or L level.
ECL logic circuit that outputs a level or L level output signal (positive phase output signal), a transmission side output terminal 4, an input bias terminal 5, a transmission side averaging circuit 6, a coaxial cable 7, and a reception side Input terminal 8 and receiving side ECL logic circuit 9
(ECL that outputs an output signal of an H level or an L level (a positive phase output signal) and an output signal of an L level or an H level (a negative phase output signal) when the input signal is an H level or an L level Logic circuit) and positive phase output terminal 1
0, the negative phase output terminal 11, the receiving side averaging circuit 12,
The terminating resistor 13, the low-pass filter 14, the transmission-side addition circuit 15, the reception-side addition circuit 16, the reception-side disconnection detection circuit 17, the transmission-side high-pass filter 18, and the reception-side high-pass filter 19. And a transmission side disconnection detection circuit 20. Further, V _EE indicates the power supply voltage, and V _EE
TH represents a control voltage for supplying the input bias of the receiving side ECL logic circuit 9.

The clock output circuit of this embodiment is an embodiment corresponding to the invention described in claim 4. In the clock output circuit of this embodiment, the clock output circuit in which the transmission side averaging circuit 6, the reception side disconnection detection circuit 17 and the transmission side disconnection detection circuit 20 do not exist (the transmission side averaging circuit 6 is short-circuited) is This corresponds to the invention described in claim 1. Further, in the clock output circuit of this embodiment, the averaging circuit 6 on the transmitting side is used.
The clock output circuit (where the transmission side averaging circuit 6 is short-circuited) in which the transmission side disconnection detection circuit 20 does not exist corresponds to the invention of claim 2. Further, in the clock output circuit of this embodiment, the clock output circuit in which the reception side disconnection detection circuit 17 does not exist corresponds to the invention of claim 3.

FIGS. 2A to 2C are diagrams showing concrete examples of signal waveforms at the input terminal 1, the post-filter terminal 2 and the positive phase output terminal 10 of the clock output circuit of this embodiment. Here, FIG. 2A is a diagram showing the waveform of the signal at the input terminal 1, FIG. 2B is a diagram showing the waveform of the signal at the terminal 2 after passing through the filter, and FIG. 5 is a diagram showing a waveform of a signal at the phase output terminal 10. FIG.

Next, the operation of the clock output circuit of this embodiment having the above configuration will be described.

First, the operation in the normal state (when the signal disconnection at the receiving side input terminal 8 does not occur) will be described.

The low-pass filter 14 inputs a signal at the input terminal 1 (for example, a signal as shown in FIG. 2A) and cuts off a high-frequency component of the signal (FIG. 2).
The signal (shown in (b)) is output to the terminal 2 after passing through the filter.

The ECL logic circuit 3 on the transmitting side inputs the signal at the terminal 2 after passing through the filter and outputs the signal (EC on the transmitting side).
A positive phase output signal corresponding to the input signal of the L logic circuit 3) is output. That is, if the input signal is an H level signal (a level higher than the threshold value of the transmission side ECL logic circuit 3), an H level output signal (a positive phase output signal) is output, and the input signal is an L level signal (the relevant phase signal). If it is a signal of a level lower than the threshold value), an L level output signal is output.

The transmitting high-pass filter 18 has a transmitting side E
The signal in which the DC component of the output signal of the CL logic circuit 3 is cut off is output to the transmission side output terminal 4.

The signal input to the receiving side input terminal 8 is a signal obtained by passing the signal at the transmitting side output terminal 4 through the coaxial cable 7 (a signal deteriorated by the frequency characteristic of the coaxial cable 7 (a signal having pulse width distortion, etc.). ))

The receiving side ECL logic circuit 9 inputs the signal after the signal at the receiving side input terminal 8 has passed through the receiving side high pass filter 19, and responds to that signal (input signal of the receiving side ECL logic circuit 9). It outputs both the positive-phase output signal and the negative-phase output signal. That is, if the input signal is an H level signal (a level higher than the threshold value of the receiving side ECL logic circuit 9), an H level positive phase output signal and an L level negative phase output signal are output, and the input signal Is an L level signal (a level lower than the threshold value), an L level positive phase output signal and an H level negative phase output signal are output. In this output operation, the DC voltage given by the control voltage V _TH via the terminating resistor 13 is the receiving side ECL.
It functions as an input bias of the logic circuit 9.

The receiving side averaging circuit 12 is the receiving side ECL.
The anti-phase output signal of the logic circuit 9 (the signal at the anti-phase output terminal 11) is averaged.

The DC component after being averaged by the receiving side averaging circuit 12 is the receiving side adding circuit 16, the coaxial cable 7 and the transmitting side averaging circuit 6 (the transmitting side averaging circuit 6 in this case cuts off the high frequency range). Functioning as a circuit)
It functions as an input bias of the transmitting side ECL logic circuit 3. That is, the transmission side addition circuit 15 superimposes this input bias on the signal at the terminal 2 (the input signal of the transmission side ECL logic circuit 3) after passing through the filter.

The input bias acts as follows to adjust the duty ratio of the output signals (the positive phase output signal and the negative phase output signal) of the reception side ECL logic circuit 9 to 50%.

When the duty ratio of the signal at the negative phase output terminal 11 is smaller than 50% (when the duty ratio of the signal at the positive phase output terminal 10 is larger than 50%), the input bias of the transmission side ECL logic circuit 3 is It becomes low, the possibility that the level of the input signal of the transmission side ECL logic circuit 3 becomes H level decreases, the duty ratio of the signal at the transmission side output terminal 4 becomes small, and the duty ratio of the signal at the anti-phase output terminal 11 becomes It becomes large (the duty ratio of the signal at the positive phase output terminal 10 becomes small).

When the duty ratio of the signal at the negative phase output terminal 11 is larger than 50% (when the duty ratio of the signal at the positive phase output terminal 10 is smaller than 50%), the input bias of the transmission side ECL logic circuit 3 is Therefore, the possibility that the input signal level of the transmission side ECL logic circuit 3 becomes H level increases, the duty ratio of the signal at the transmission side output terminal 4 increases, and the duty ratio of the signal at the anti-phase output terminal 11 increases. It becomes smaller (the duty ratio of the signal at the positive phase output terminal 10 becomes larger).

As a result of the above operation, the duty ratio of the positive phase output signal (signal at the positive phase output terminal 10) of the receiving side ECL logic circuit 9 is 50 as shown in FIG. 2 (c).
Is kept at%. That is, in this way, the positive phase output terminal 10
In order to maintain the duty ratio of the signal in (1) (that is, the output signal of the clock output circuit of this embodiment) and the signal in the negative-phase output terminal 11 at 50%, correction for deterioration due to passage of the coaxial cable 7 (correction of pulse width distortion) The duty ratio of the signal at the transmission-side output terminal 4 is adjusted so that the above values are taken into consideration.

The reception side disconnection detection circuit 17 and the transmission side disconnection detection circuit 20 are not involved in the above-described normal operation. Further, even when the transmission side averaging circuit 6 is short-circuited, the above-described normal operation can be realized. Therefore, it can be said that the above-described normal operation applies to the inventions according to claims 1 to 4.

Secondly, due to disconnection or disconnection of the coaxial cable 7, failure of the transmitting side and receiving side, disconnection of the signal input to the input terminal 1, etc., signal disconnection at the receiving side input terminal 8 is caused. The operation when it occurs will be described.

In this case, only the input bias (DC voltage) supplied by the control voltage V _TH via the terminating resistor 13 (excluding the noise signal) is applied to the input side of the receiving side ECL logic circuit 9. It will be. The level of the input bias is set to be a level separated from the level of the threshold value of the reception side ECL logic circuit 9 by the level of the noise signal (noise level) which may be mixed (termination resistance 13 Is a control voltage V so that the input bias of the ECL logic circuit 9 on the receiving side becomes such a level.
_{(The TH} source is connected to the input side of the receiving side ECL logic circuit 9).

As a result, the level on the input side of the reception side ECL logic circuit 9 becomes a fixed state of H level or L level determined by the input bias even if a noise signal is mixed.

Therefore, the normal phase output signal of the reception side ECL logic circuit 9 (the signal at the normal phase output terminal 10) is fixed to the H level or the L level, and the reception side ECL logic circuit 9 is fixed.
The negative-phase output signal of (the signal at the negative-phase output terminal 11) is L
Fixed to level or H level. That is, the noise signal is less likely to be mixed in on the output side of the reception side ECL logic circuit 9. Therefore, it becomes possible to reliably detect the signal disconnection at the receiving side input terminal 8.

The operations up to this point are operations corresponding to the inventions according to claims 1 to 4 among the operations of the clock output circuit of the present embodiment.

Next, among the operations of the clock output circuit of the present embodiment, the operations corresponding to only the invention described in claim 2 and the invention described in claim 4 will be described.

The reception side disconnection detection circuit 17 includes the coaxial cable 7
When a signal disconnection occurs at the receiving side input terminal 8 due to a cable disconnection or disconnection of the receiving side ECL logic circuit 9 whose level is fixed as described above (a reverse phase output signal). The signal at the output terminal 11) is input, and the anti-phase output signal is fixed to the L level or the H level (which level is known in advance by the level of the input bias given by the control voltage V _TH ). The signal disconnection is detected based on the recognition that the signal is a signal, and an alarm indicating that the signal is disconnected is output (a predetermined lamp is turned on). This enables the receiving side to easily and quickly detect (recognize) a signal break.

Next, among the operations of the clock output circuit of the present embodiment, the operations corresponding only to the invention of claim 3 and the invention of claim 4 will be described.

When a signal disconnection occurs at the receiving side input terminal 8 due to disconnection or disconnection of the coaxial cable 7, failure of the receiving side ECL logic circuit 9, or the like, the transmitting side averaging circuit 6 transmits the signal. The signal at the side output terminal 4 is averaged and passed to the transmission side addition circuit 15. The feedback loop formed by the transmission side averaging circuit 6 and the transmission side addition circuit 15 has a positive feedback effect on the transmission side ECL logic circuit 3. Therefore, in the case of the signal disconnection, the signal at the transmission-side output terminal 4 is fixed at a constant level due to the positive feedback action.

The disconnection detection circuit 20 connected to the transmission-side output terminal 4 has a fixed signal level at the transmission-side output terminal 4 when the reception-side input terminal 8 has a signal disconnection. The signal disconnection is detected based on the recognition of, and an alarm indicating the signal disconnection is output. This enables the transmitting side to easily and quickly detect (recognize) a signal break.

[0056]

As described above, according to the present invention, the receiving side E
The input bias of the transmission side ECL logic circuit is generated based on the reverse phase output signal of the CL logic circuit to output the output signal of the reception side ECL logic circuit (that is, the output signal of the clock output circuit).
By adjusting the duty ratio of (1), it is possible to prevent the noise signal from being output to the output side of the receiving side ECL logic circuit even if a signal disconnection occurs at the receiving side input terminal. The level on the output side is fixed), and there is an effect that the signal disconnection can be reliably detected. Needless to say, an output signal having a duty ratio of 50% can be generated under normal conditions.

Further, by utilizing the fact that the negative phase output signal of the receiving side ECL logic circuit becomes a fixed level when a signal loss occurs at the receiving side input terminal, the fact that the signal loss occurs is taken into account. By causing the reception side disconnection detection circuit to output an alarm indicating that, there is an effect that the reception side can easily and promptly detect (recognize) the signal disconnection.

Further, based on the positive feedback action by the feedback loop formed in the transmitting side when the signal disconnection occurs at the receiving side input terminal (the transmitting side averaging circuit is provided for forming this feedback loop). By using the fact that the signal at the output terminal on the transmitting side becomes a fixed level, an alarm to that effect is output by the transmitting side disconnection detection circuit, so that the signal disconnection can be easily performed. In addition, there is an effect that quick detection (recognition) is possible on the transmission side.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a clock output circuit of the present invention.

FIG. 2 is a diagram showing a specific example of signal waveforms at an input terminal, a post-filter terminal and a positive phase output terminal of the clock output circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of an example of a conventional clock output circuit.

[Explanation of symbols]

 1 input terminal 2 terminal after passing filter 3 transmission side ECL logic circuit 4 transmission side output terminal 5 input bias terminal 6 transmission side averaging circuit 7 coaxial cable 8 reception side input terminal 9 reception side ECL logic circuit 10 normal phase output terminal 11 reverse Phase output terminal 12 Reception side averaging circuit 13 Termination resistor 14 Low pass filter 15 Transmission side addition circuit 16 Reception side addition circuit 17 Reception side disconnection detection circuit 18 Transmission side high pass filter 19 Reception side high pass filter 20 Transmission side Disconnection detection circuit

Claims (4)

[Claims] 1. A low-pass filter that blocks high-pass components of a signal at an input terminal, and a transmission-side ECL that outputs an in-phase output signal corresponding to the input signal, which is an output signal of the low-pass filter.
A logic circuit, a coaxial cable for transmitting a signal at the transmission side output terminal based on the positive phase output signal of the transmission side ECL logic circuit to the reception side, and a signal at the reception side input terminal transmitted from the transmission side by the coaxial cable. Is used as an input signal and outputs a positive-phase output signal and a negative-phase output signal to the input signal, and an input bias of the receiving-side ECL logic circuit is a threshold of the receiving-side ECL logic circuit. A terminating resistor that connects the control voltage supply source and the input side of the receiving side ECL logic circuit so that the level is separated from the value by a noise level or more, and the reverse phase output signal of the receiving side ECL logic circuit is averaged. Receiving side averaging circuit that generates a direct current component by the receiving side, and a receiving side addition circuit that returns the direct current component generated by this receiving side averaging circuit to the transmitting side. A transmission side addition circuit that superimposes a DC component returned to the transmission side by the function of the reception side addition circuit on an input signal of the transmission side ECL logic circuit as an input bias of the transmission side ECL logic circuit; Side ECL logic circuit and transmission side output terminal which cuts off the DC component of the signal, and the transmission side high pass filter cuts off the DC component of the signal between the reception side input terminal and the reception side ECL logic circuit. A clock output circuit having a receiving side high-pass filter. 2. A receiving side which detects a signal loss at an input terminal of the receiving side based on the recognition that the output signal of the receiving side ECL logic circuit becomes a fixed level and outputs an alarm indicating the signal loss. The clock output circuit according to claim 1, further comprising a disconnection detection circuit. 3. A transmission side averaging circuit for averaging an output signal of the transmission side high-pass filter and passing it to the transmission side addition circuit when a signal disconnection occurs at the reception side input terminal, and the transmission side high band. And a transmission side disconnection detection circuit that detects a signal disconnection at the reception side input terminal based on the recognition that the output signal of the pass filter has a fixed level, and outputs an alarm indicating the signal disconnection. Claim 1
The described clock output circuit. 4. A transmission side averaging circuit for averaging an output signal of the transmission side high-pass filter and passing it to the transmission side addition circuit when a signal disconnection occurs at the reception side input terminal, and the transmission side high band. And a transmission side disconnection detection circuit that detects a signal disconnection at the reception side input terminal based on the recognition that the output signal of the pass filter has a fixed level, and outputs an alarm indicating the signal disconnection. Claim 2
The described clock output circuit.