JPH06152368A - Reference voltage generating circuit - Google Patents

Abstract

PURPOSE:To provide a reference voltage generating circuit capable of reducing both current consumption and the variation of reference voltage against noise. CONSTITUTION:A potential difference between ground potential and positive polarity potential is divided by resistors 10, 11 and reference voltage VREF is supplied to an output terminal 14. The emitter-collector of a pnp type transistor(TR) 15 is inserted between the terminal 14 and the ground potential and the collector-emitter of an npn type TR 16 is inserted between the positive polarity potential and the terminal 14. Bias voltage VB0 having the same value as reference voltage VREF obtained by the resistance division of resistors 12, 13 is supplied to the bases of the TRs 15, 16. The resistance values of the resistors 12, 13 are set to a high level capable of supplying a sufficient base current to one of the TRs 15, 16 to suppress current consumption. When the reference voltage VREF is changed, a current is allowed to flow between either of collector-emitter of the TR 15 and 16 and the changed voltage is absorbed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a reference voltage in a semiconductor integrated circuit, which has a particularly low current consumption,
Further, the present invention relates to a reference voltage generation circuit that can stably generate a reference voltage even if noise is mixed.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram of a conventional reference voltage generating circuit. In this circuit, a constant reference voltage VREF is obtained at the output terminal 52 by dividing the power supply voltage by a pair of resistors 50 and 51.

[0003]

By the way, the value of the reference voltage VREF varies due to the inclusion of noise. In order to prevent such voltage fluctuations due to noise, it is necessary to reduce the resistance values of the resistors 50 and 51 to lower the impedance between the power supply potential and the ground potential.
However, there is a problem that the current consumption constantly increases by lowering this impedance.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a reference voltage generating circuit which has a small steady current consumption and a small fluctuation of the reference voltage with respect to noise. .

[0005]

A reference voltage generating circuit according to the present invention has a first resistor having one end connected to a first potential and the other end connected to a reference voltage output terminal, and one end having a second resistance. A second resistor connected to the output terminal and the other end connected to the output terminal, and a first polarity first transistor whose collector is connected to the first potential and whose emitter is connected to the output terminal. And a second transistor having a second polarity whose collector is connected to the second potential and whose emitter is connected to the output terminal, and the same value as the voltage appearing at the output terminal due to the first and second resistors. And a bias means for supplying the DC bias voltage of 1) to the bases of the first and second transistors.

[0006]

In the reference voltage generating circuit configured as described above, the voltage at the output terminal fluctuates, and the potential difference between the DC bias voltage and the voltage at the output terminal causes a forward voltage between the base and emitter of the first or second transistor. If it exceeds, the first or second
One of the transistors is turned on to rapidly charge or discharge the output terminal in the direction of absorbing the voltage fluctuation of the output terminal.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a reference voltage generating circuit according to a first embodiment of the present invention. The reference voltage generating circuit of this embodiment comprises four resistors 10 to 13, a reference voltage output terminal 14, a PNP type bipolar transistor 15 and an NPN type bipolar transistor 16.

One end of the resistor 10 is connected to the ground potential,
The other end is connected to the output terminal 14. One end of the resistor 11 is connected to the positive power source potential, and the other end is connected to the output terminal 14. Therefore, the potential difference between the power supply potential and the ground potential is resistance-divided by the resistors 10 and 11, and the divided voltage is output from the output terminal 14 as the reference voltage VREF.

The collector of the PNP type bipolar transistor 15 is connected to the ground potential, and the emitter is connected to the output terminal 14. NPN type bipolar transistor 16
The collector of is connected to the positive power source potential, and the emitter is connected to the output terminal 14.

The two resistors 12 and 13 are connected in series between the positive power source potential and the ground potential. Like the resistors 10 and 11, the resistors 12 and 13 divide the potential difference between the power source potential and the ground potential to generate a DC bias voltage VB0. This bias voltage VB0 is applied to both transistors 1
Supplied on 5, 16 bases. The value of the bias voltage VB0 is set to be the same as the reference voltage VREF. That is, if the resistance values of the resistors 10, 11, 12, and 13 are R10, R11, R12, and R13, respectively, R10: R11 = R
The resistance ratio of the two resistors 12 and 13 is set so as to satisfy the relationship of 12: R13. Further, the resistance values of the resistors 12 and 13 are set high enough to supply a sufficient base current to one of the transistors 15 or 16 so that the direct current flowing from the power supply potential to the ground potential is minimized. . Here, the operation of the reference voltage generating circuit when noise is added to the reference voltage VREF will be described with reference to the waveform diagram of FIG.

First, the case where the reference voltage VREF rises above the design voltage VA due to noise will be described. The base-emitter forward voltage is determined by the material of the substrate on which the transistor is formed, and is 0.6 in the case of silicon.
Although it is about 0.7V, it is assumed that the transistors 15 and 16 have, for example, 0.6V. Therefore, when the reference voltage VREF becomes higher than the bias voltage VB0 by 0.6V, a voltage of 0.6V is applied between the base and emitter of the transistor 15, so that a base current flows through the transistor 15.
Then, since the emitter current flows through the transistor 15, the reference voltage VREF appearing at the output terminal 14 to which the emitter is connected decreases. As a result, the reference voltage V
Noise components of (VA +0.6) V or more contained in REF are absorbed by the ground potential.

Next, the case where the reference voltage VREF drops due to noise will be described. Reference voltage VREF is bias voltage V
When the voltage is 0.6V lower than BO, a voltage of 0.6V is applied between the base and emitter of the transistor 16,
Base current flows to 16. Then, a collector current flows in the transistor 16 and the design voltage VREF appearing at the output terminal 14 to which the emitter is connected becomes high. As a result, a noise component of (VA +0.6) V or less contained in the reference voltage VREF is absorbed in the power supply potential.

Therefore, in the circuit of the first embodiment,
Due to the operation of the transistors 15 and 16, the reference voltage VREF does not fluctuate more than 0.6V from the design voltage VA.
Therefore, it is not necessary to suppress the fluctuation of the reference voltage VREF by lowering the resistance values of the resistors 10 and 11. Therefore,
It is possible to set the resistance value of resistors 10 and 11 high,
It is possible to reduce the steady current consumption.

FIG. 3 is a circuit diagram of a reference voltage generating circuit according to the second embodiment of the present invention. This embodiment circuit differs from the embodiment circuit of FIG. 1 in that different bias voltages are supplied to the bases of the transistors 15 and 16, and the other points are the same as those of the embodiment circuit of FIG. . Therefore, in FIG. 3, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and only different portions will be described.

That is, the bias voltage VB1 supplied to the base of the PNP type transistor 15 is formed by two resistors 17 and 18 connected in series between the power supply potential and the ground potential, and the bias voltage VB1 of the NPN type transistor 16 is increased. The bias voltage VB2 supplied to the base is formed by two resistors 19 and 20 connected in series between the power supply potential and the ground potential.

Since the two resistors 17 and 18 and the resistors 19 and 20 connected in series are inserted between the positive power source potential and the ground potential, a direct current constantly flows in each of them. However, like the first embodiment circuit, in order to suppress the value of this DC current, the values of the resistors 17 to 20 are set to a high value such that one of the transistors 15 or 16 can be supplied with a sufficiently large base current. Therefore, the value of this direct current is small.

The value of the DC bias voltage VB1 is the same as that of the transistor in the normal state where noise is not mixed.
It is set so that the base current does not flow through the transistor 15, but the base current flows through the transistor 15 by a slight fluctuation of the reference voltage VREF. Since the forward voltage between the base and the emitter of the transistor 15 is 0.6 V, the bias voltage VB1
Is lower than (VREF −0.6) V, the transistor 15
The base-emitter voltage of 0.6V or higher is reached and a base current flows. Therefore, for example, when the reference voltage VREF is 0.
The value of the bias voltage VB1 is set to (VREF-0.
4) Set to V.

Further, the value of the DC bias voltage VB2 is set so that the base current does not flow through the transistor 16 in a normal state where noise is not mixed, but the base current flows through the transistor 16 due to a slight fluctuation of the reference voltage VREF. To do. Since the forward voltage between the base and the emitter of the transistor 16 is 0.6 V, the bias voltage VB2 becomes (VRE
When it becomes higher than F + 0.6) V, the voltage between the base and the emitter of the transistor 16 becomes 0.6V or more, and the base current flows. Therefore, the value of the bias voltage VB2 is set to (VREF + 0.4) V so that the base current flows through the transistor 16 when the reference voltage VREF decreases by 0.2V.

In the circuit of the second embodiment, the reference voltage VREF
The waveform diagram when noise is added to is as shown in Fig. 4. Now, when the reference voltage VREF becomes higher than the design voltage VA by 0.2V due to noise, the potential difference between the bias voltage VB1 which is the voltage between the base and the emitter of the transistor 15 and the voltage VREF becomes 0.6V. An electric current flows. Then, since the emitter current flows in the transistor 15, the output terminal to which this emitter is connected
14 voltage drops. As a result, the noise component of (VA +0.2) V or more contained in the reference voltage VREF is absorbed by the ground potential.

When the reference voltage VREF drops 0.2 V below the design voltage VA due to noise, the bias voltage VB2 and the voltage VB2 which are the voltage between the base and emitter of the transistor 16 are generated.
Since the potential difference from REF is 0.6 V, the transistor 16
The base current flows to. Then, in this transistor 16, a current flows to the collector, so that the voltage appearing at the output terminal 14 to which the emitter is connected decreases. As a result, the noise component of (VA −0.2) V or less contained in the reference voltage VREF is absorbed in the power supply potential.

In this second embodiment circuit, the transistor
Since the base bias voltages of 15 and 16 can be set individually, the fluctuation voltage of the reference voltage VREF can be reduced to 0.2V, for example, as compared with the first embodiment circuit. Further, since the resistance values of the resistors 10 and 11 can be set to be high and the resistance values of the resistors 17 to 20 can be set to be high as in the first embodiment circuit, the steady state can be set similarly to the first embodiment circuit. Power consumption can be reduced.

[0023]

As described above, according to the present invention, it is possible to provide a reference voltage generating circuit which consumes less constant current and has less fluctuation of the reference voltage due to noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a reference voltage generating circuit according to a first embodiment of the present invention.

FIG. 2 is an output voltage waveform diagram of the embodiment circuit of FIG.

FIG. 3 is a circuit diagram of a reference voltage generating circuit according to a second embodiment of the present invention.

4 is an output voltage waveform diagram of the embodiment circuit of FIG.

FIG. 5 is a circuit diagram of a conventional reference voltage generation circuit.

[Explanation of symbols]

10, 11, 12, 13, 17, 17, 18, 19, 20 ... Resistor, 14 ... Output terminal, 15 ... PNP type bipolar transistor, 16 ... NP
N-type bipolar transistor.

Claims (2)

[Claims] 1. A first resistor, one end of which is connected to a first potential and the other end of which is connected to an output terminal of a reference voltage, and one end of which is connected to a second potential and the other end of which is connected to the output terminal. A second resistor connected to the collector; a collector connected to the first potential; a first transistor having a first polarity connected to the output terminal; and a collector connected to the second potential; A second transistor having a second polarity whose emitter is connected to the output terminal, and a DC bias voltage having the same value as the voltage appearing at the output terminal generated by the first and second resistors to generate the first and second transistors. 2. A reference voltage generating circuit, comprising: a bias generating means for supplying the base of the second transistor. 2. A first resistor, one end of which is connected to a first potential and the other end of which is connected to an output terminal of a reference voltage, and one end of which is connected to a second potential and the other end of which is connected to the output terminal. A second resistor connected to the first potential, a collector connected to the first potential, a first polarity first bipolar transistor having an emitter connected to the output terminal, and a collector connected to the second potential A second bipolar transistor of the second polarity whose emitter is connected to the output terminal, and a base-emitter sequence of the first bipolar transistor with respect to the voltage appearing at the output terminal due to the first and second resistors. The first bias generating means for generating a first DC bias voltage higher than the voltage lower than the direction voltage and supplying it to the base of the first bipolar transistor, and the first and second resistors generate the first DC bias voltage. A second DC bias voltage lower than a voltage obtained by adding the forward voltage between the base and the emitter of the second bipolar transistor to the voltage appearing at the terminal is generated and is supplied to the base of the second transistor. A reference voltage generating circuit comprising: a bias generating means.