JPH06152143A - Manufacture of electronic part mounting board - Google Patents

Manufacture of electronic part mounting board

Info

Publication number
JPH06152143A
JPH06152143A JP4328900A JP32890092A JPH06152143A JP H06152143 A JPH06152143 A JP H06152143A JP 4328900 A JP4328900 A JP 4328900A JP 32890092 A JP32890092 A JP 32890092A JP H06152143 A JPH06152143 A JP H06152143A
Authority
JP
Japan
Prior art keywords
circuit board
opening hole
metal plating
electronic component
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4328900A
Other languages
Japanese (ja)
Inventor
Yasutaka Kato
泰隆 加藤
Tetsuro Asano
哲朗 浅野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP4328900A priority Critical patent/JPH06152143A/en
Publication of JPH06152143A publication Critical patent/JPH06152143A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15157Top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate

Landscapes

  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

PURPOSE:To provide a means for manufacturing an electronic parts mounting board wherein metal plating can be done within an opening hole, there is no short circuit between a bonding wire and a ring-like plating, and further, a fine pattern is easily formed. CONSTITUTION:In manufacturing an electronic parts mounting board that contains an opening hole 99 for forming a recessed section for mounting an electronic parts, the opening hole 99 that contains a tapered inner wall 991, gradually becoming wider in the direction from the front side of a circuit board 9 toward the rear side of it, is formed. The entire surface of the circuit board 9 including the surface of the opening hole 99 is coated with a metal plating 5 and an electro-deposition film 6. For the opening hole 99 and its vicinity to be irradiated with light 79 for exposure, a mask film 7 is placed, and the light is poured for development, and then the electro-deposition film 6 around the opening hole 99 is removed. Further, the metal plating 5 around the opening hole 99 is removed by etching, then remaining electro-deposition film 6 is removed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は,電子部品搭載用基板の
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electronic component mounting board.

【0002】[0002]

【従来技術】従来,電子部品搭載用基板としては,例え
ば,図7に示すごとく,内層回路51,52を有する回
路基板9と,該回路基板9に設けた開口穴99と,該開
口穴99の一端を被覆するように接着したヒートシンク
8と,該ヒートシンク8と上記開口穴99とにより形成
される電子部品搭載用凹部900とを有するものがあ
る。
2. Description of the Related Art Conventionally, as an electronic component mounting board, for example, as shown in FIG. 7, a circuit board 9 having inner layer circuits 51 and 52, an opening hole 99 provided in the circuit board 9, and an opening hole 99 are provided. There is a heat sink 8 adhered so as to cover one end thereof, and an electronic component mounting recess 900 formed by the heat sink 8 and the opening hole 99.

【0003】上記開口穴99の内壁999には湿気侵入
防止用の金属メッキ5が施されており,また開口穴99
の周辺には,リング状メッキ59が形成されている。一
方,回路基板9の裏側面における上記開口穴99周辺に
は,接着シート65を介してヒートシンク8が接着固定
されている。回路基板9は,絶縁基板91,92,93
を積層することにより形成されている。絶縁基板91,
92の上には,上記内層回路51,52が形成されてい
る。
The inner wall 999 of the opening hole 99 is provided with a metal plating 5 for preventing moisture intrusion, and the opening hole 99 is also formed.
A ring-shaped plating 59 is formed around the area. On the other hand, the heat sink 8 is adhesively fixed to the periphery of the opening hole 99 on the back side of the circuit board 9 via an adhesive sheet 65. The circuit board 9 includes insulating boards 91, 92, 93.
Are formed by stacking. Insulating substrate 91,
The inner layer circuits 51 and 52 are formed on 92.

【0004】回路基板9の表側面には,外層回路50が
形成されている。また,回路基板9の裏側面は,湿気防
止用の金属メッキ5により被覆されている。上記電子部
品搭載用凹部900には,電子部品3が搭載され,ボン
ディングワイヤー30により回路基板9上の外層回路5
0と電気的に接続されている。
An outer layer circuit 50 is formed on the front surface of the circuit board 9. Further, the back side surface of the circuit board 9 is covered with a metal plating 5 for preventing moisture. The electronic component 3 is mounted in the electronic component mounting recess 900, and the outer layer circuit 5 on the circuit board 9 is bonded by the bonding wire 30.
It is electrically connected to 0.

【0005】次に,上記電子部品搭載用基板の製造方法
について説明する。上記製造法においては,近年,電着
膜を用いたパターン形成方法がある。電着膜法は,ファ
インパターンの形成にとって,優れた方法である。以下
に,まずこの方法を示す。
Next, a method of manufacturing the electronic component mounting board will be described. In the above manufacturing method, recently, there is a pattern forming method using an electrodeposition film. The electrodeposition film method is an excellent method for forming fine patterns. Below, this method is shown first.

【0006】即ち,図8(J)に示すJ工程において,
絶縁基板91,92,93を下から順に積層し,回路基
板9を作製する。絶縁基板91,92の上には内層回路
51,52がそれぞれ形成されている。次に,図8
(K)に示すK工程において,上記回路基板9に開口穴
99を穿設する。次に,図8(L)に示すL工程におい
て,上記開口穴99の内壁999を含む上記回路基板9
の表面全体に金属メッキ5を施す。
That is, in the J process shown in FIG.
The insulating substrates 91, 92, 93 are laminated in order from the bottom to manufacture the circuit board 9. Inner layer circuits 51 and 52 are formed on the insulating substrates 91 and 92, respectively. Next, FIG.
In step K shown in (K), the opening hole 99 is formed in the circuit board 9. Next, in the L step shown in FIG. 8L, the circuit board 9 including the inner wall 999 of the opening hole 99 is formed.
Metal plating 5 is applied to the entire surface of.

【0007】次に,図9(M)に示すM工程において,
上記金属メッキ5の表面全体に電着膜6を形成する。次
に,図9(N)に示すN工程において,回路基板9の表
側面に,外層回路及びリング状メッキと同形状のパター
ン70を有するマスクフィルム7を載置する。そして,
該マスクフィルム7の上方から紫外線79を照射し,電
着膜6を露光する。
Next, in the M step shown in FIG.
An electrodeposition film 6 is formed on the entire surface of the metal plating 5. Next, in the N step shown in FIG. 9N, the mask film 7 having the pattern 70 having the same shape as the outer layer circuit and the ring-shaped plating is placed on the front surface of the circuit board 9. And
Ultraviolet rays 79 are irradiated from above the mask film 7 to expose the electrodeposition film 6.

【0008】次に,図10(O)に示すO工程におい
て,上記マスクフィルムを取り去り,電着膜6における
露光された部分を現像により除去する。次に,図10
(P)に示すP工程において,上記電着膜6により被覆
されていない部分の金属メッキ5をエッチングにより除
去する。次に,図10(Q)に示すQ工程において,上
記残りの電着膜6を除去する。
Next, in the step O shown in FIG. 10 (O), the mask film is removed and the exposed portion of the electrodeposition film 6 is removed by development. Next, FIG.
In the step P shown in (P), the metal plating 5 in the portion not covered with the electrodeposition film 6 is removed by etching. Next, in the step Q shown in FIG. 10 (Q), the remaining electrodeposited film 6 is removed.

【0009】次に,図10(R)に示すR工程におい
て,上記回路基板9の裏側面において上記開口穴99を
被覆するように,接着シート65を介してヒートシンク
8を接着する。上記電着膜法によれば,図7,図11に
示すごとく,開口穴99の壁面999に金属メッキ5が
形成されていると共に表側面において開口穴99周辺に
リング状メッキ59が残存形成されている。このリング
状メッキ59を形成する理由は,次のようである。
Next, in the R step shown in FIG. 10 (R), the heat sink 8 is bonded via the adhesive sheet 65 so as to cover the opening hole 99 on the back side surface of the circuit board 9. According to the electrodeposition film method, as shown in FIGS. 7 and 11, the metal plating 5 is formed on the wall surface 999 of the opening hole 99, and the ring-shaped plating 59 remains on the front surface side around the opening hole 99. ing. The reason for forming the ring-shaped plating 59 is as follows.

【0010】即ち,マスクフィルム7と回路基板9との
位置関係にズレがあると,光照射位置にズレを生じ,開
口穴99の内壁999も光照射され,その表面の電着膜
6が露光され,現像,エッチング工程において,開口穴
99の内壁999表面の金属メッキ5が除去されてしま
うためである。それ故,リング状メッキを形成せざるを
得ないのである。
That is, if the positional relationship between the mask film 7 and the circuit board 9 is deviated, the light irradiation position is deviated, and the inner wall 999 of the opening hole 99 is also irradiated with light, and the electrodeposition film 6 on the surface is exposed. This is because the metal plating 5 on the surface of the inner wall 999 of the opening hole 99 is removed in the developing and etching processes. Therefore, there is no choice but to form ring-shaped plating.

【0011】[0011]

【解決しようとする課題】しかしながら,上記リング状
メッキ59は,ボンディングワイヤー30とショートす
るおそれがある。そこで,図12に示すごとく,表側面
において,開口穴99の周辺にリング状メッキを形成さ
せないことが考えられる。そのためには,上記N工程に
おいて,図13に示すごとく,回路基板9の開口穴99
及びその周辺が全て透明に形成されたマスクフィルム7
を用いることが考えられる(図9と比較)。
However, the ring-shaped plating 59 may short-circuit with the bonding wire 30. Therefore, as shown in FIG. 12, it is considered that the ring-shaped plating is not formed around the opening hole 99 on the front surface. For that purpose, in the above N process, as shown in FIG.
And a mask film 7 in which the periphery of the mask film 7 is transparent
Can be used (compare with FIG. 9).

【0012】しかし,これでは,光照射の際に開口穴9
9の内壁999表面の電着膜6も露光されてしまう。そ
のため,その後の現像,エッチング工程において,内壁
999表面の金属メッキ5も除去されてしまう。それ
故,図14に示すごとく,内壁999に金属メッキ不着
部分990が形成されてしまう。その結果,該金属メッ
キ不着部分990から開口穴99に湿気が浸入するおそ
れがある。また,電子部品を搭載した上記電子部品搭載
用基板を使用する際には,インダクタンスを低下させる
ことができないことがある。
However, in this case, the opening hole 9 is not exposed when the light is irradiated.
The electrodeposition film 6 on the surface of the inner wall 999 of 9 is also exposed. Therefore, the metal plating 5 on the surface of the inner wall 999 is also removed in the subsequent development and etching steps. Therefore, as shown in FIG. 14, the metal plating non-adhesive portion 990 is formed on the inner wall 999. As a result, moisture may enter the opening 99 from the metal plating non-adhesive portion 990. Further, when using the electronic component mounting board on which the electronic component is mounted, it may not be possible to reduce the inductance.

【0013】そこで,上記問題点に鑑み,半田剥離法を
用いる方法が考えられる。以下,該半田剥離法につい
て,図15〜図17を用いて説明する。まず,上記電着
膜法と同様に,前記の図8(J)〜図8(L)に示すJ
工程〜L工程を行う。次に,図15(S)に示すS工程
において,回路基板9の表側面及び裏側面に感光性ドラ
イフィルム60,61を載置する。
In view of the above problems, a method using the solder peeling method is considered. The solder peeling method will be described below with reference to FIGS. First, as in the case of the above electrodeposition film method, J shown in FIGS. 8 (J) to 8 (L) above is used.
Process-L process are performed. Next, in step S shown in FIG. 15 (S), the photosensitive dry films 60 and 61 are placed on the front and back surfaces of the circuit board 9.

【0014】次に,図15(T)に示すT工程におい
て,感光性ドライフィルム60の上に,上記開口穴99
周辺が透明であって,かつ外層回路及び開口穴99と同
形状のパターン70を有するマスクフィルム7を載置す
る。そして,該マスクフィルム7の上から紫外線79を
光照射し,パターン70以外の部分の下に位置する感光
性ドライフィルム60を露光する。
Next, in the step T shown in FIG. 15 (T), the opening 99 is formed on the photosensitive dry film 60.
The mask film 7 having a pattern 70 having the same shape as that of the outer layer circuit and the opening hole 99 and having a transparent periphery is placed. Then, ultraviolet rays 79 are irradiated from above the mask film 7 to expose the photosensitive dry film 60 located below the portion other than the pattern 70.

【0015】次に,図16(U)に示すU工程におい
て,上記マスクフィルムを取り去り,感光性ドライフィ
ルム60,61における露光されていない部分を現像に
より除去する。次に,図16(V)に示すV工程におい
て,上記感光性ドライフィルム60により被覆されてい
ない金属メッキ5の表面に半田メッキ62を施す。次
に,図16(W)に示すW工程において,上記残りの感
光性ドライフィルム60を除去する。
Next, in step U shown in FIG. 16 (U), the mask film is removed, and the unexposed portions of the photosensitive dry films 60 and 61 are removed by development. Next, in a step V shown in FIG. 16 (V), solder plating 62 is applied to the surface of the metal plating 5 not covered with the photosensitive dry film 60. Next, in the step W shown in FIG. 16 (W), the remaining photosensitive dry film 60 is removed.

【0016】次に,図17(X)に示すX工程におい
て,上記半田メッキ62により被覆されていない部分の
金属メッキ5をエッチングにより除去する。次に,図1
7(Y)に示すY工程において,上記残りの半田メッキ
62を除去する。その後,図12に示すごとく,前記電
着膜法のR工程と同様に,回路基板9の裏側面にヒート
シンク8を接着する。これにより,表側面の開口穴99
の周辺にリング状メッキ59(図7,図11)を有しな
い,電子部品搭載用基板が得られる。
Next, in step X shown in FIG. 17 (X), the metal plating 5 in the portion not covered with the solder plating 62 is removed by etching. Next, Fig. 1
In the Y step shown in FIG. 7 (Y), the remaining solder plating 62 is removed. Thereafter, as shown in FIG. 12, the heat sink 8 is adhered to the back side surface of the circuit board 9 as in the R step of the electrodeposition film method. As a result, the opening hole 99 on the front side
An electronic component mounting substrate is obtained which does not have the ring-shaped plating 59 (FIGS. 7 and 11) around the substrate.

【0017】しかし,上記半田剥離法は,製造工程が多
く,製造に長時間を要する。また,鮮明な配線パターン
を得難く,ファインパターン形成に不向きである。本発
明はかかる問題点に鑑み,上記開口穴の内壁に金属メッ
キを形成できると共に,ボンディングワイヤーとリング
状メッキとのショートがなく,ファインパターン形成が
容易な電子部品搭載用基板の製造方法を提供しようとす
るものである。
However, the solder stripping method has many manufacturing steps and requires a long time for manufacturing. Further, it is difficult to obtain a clear wiring pattern, which is not suitable for forming a fine pattern. In view of the above problems, the present invention provides a method for manufacturing a substrate for mounting electronic components, which can form a metal plating on the inner wall of the opening hole, has no short circuit between the bonding wire and the ring-shaped plating, and can easily form a fine pattern. Is what you are trying to do.

【0018】[0018]

【課題の解決手段】本発明は,回路基板と,該回路基板
に設けた電子部品搭載用凹部を形成するための開口穴と
を有する電子部品搭載用基板の製造方法において,回路
基板を準備するA工程と,該回路基板の表側面から裏側
面に向けて拡開するテーパー状内壁を有する開口穴を形
成するB工程と,上記開口穴の表面を含めた回路基板の
全表面を金属メッキにより被覆するC工程と,上記金属
メッキの表面を電着膜により被覆するD工程と,上記回
路基板の表側面に配線パターン形成用の露光用のマスク
フィルムを載置し,該マスクフィルムの上から光照射す
るE工程と,上記回路基板上のマスクフィルムを取り去
り,回路基板を現像することにより,開口穴周辺の電着
膜を除去するF工程と,上記回路基板をエッチングする
ことにより表側面における開口穴周辺の金属メッキを除
去するG工程と,上記回路基板から残りの電着膜を除去
するH工程とよりなることを特徴とする電子部品搭載用
基板の製造方法にある。
According to the present invention, a circuit board is prepared in a method of manufacturing an electronic part mounting board having a circuit board and an opening hole for forming an electronic part mounting recess provided in the circuit board. A step, B step of forming an opening hole having a tapered inner wall that expands from the front side surface to the back side surface of the circuit board, and the entire surface of the circuit board including the surface of the opening hole is plated with metal. Step C for coating, Step D for coating the surface of the metal plating with an electrodeposition film, placing an exposure mask film for forming a wiring pattern on the front surface of the circuit board, and from the top of the mask film E step of irradiating light, F step of removing the mask film on the circuit board and developing the circuit board to remove the electrodeposition film around the opening hole, and the front surface of the circuit board by etching the circuit board And G step of removing the metal plating around definitive opening hole, in the manufacturing method of the electronic component mounting board, characterized in that the more the H step of removing the remaining electrodeposited film from the circuit board.

【0019】本発明において最も注目すべきことは,B
工程において,回路基板に,該回路基板の表側面方向か
ら裏側面に向けて拡開するテーパー状内壁を有する開口
穴を形成しておくことである。上記回路基板は,1又は
複数の絶縁基板からなる。また,回路基板の内部には,
内層回路,スルーホールを形成することができる。
What is most noticeable in the present invention is B
In the step, an opening hole having a tapered inner wall that expands from the front side surface direction of the circuit board toward the back side surface is formed in the circuit board. The circuit board is composed of one or a plurality of insulating boards. Also, inside the circuit board,
Inner layer circuits and through holes can be formed.

【0020】上記電子部品搭載用基板の表側面,裏側面
の一方又は双方には,外層回路を形成することができ
る。回路基板の開口穴周辺にはヒートシンクが接着され
る。該ヒートシンクを回路基板に接着する際には,接着
シート等を用いることが好ましい。
An outer layer circuit can be formed on one or both of the front side surface and the back side surface of the electronic component mounting board. A heat sink is adhered around the opening of the circuit board. When adhering the heat sink to the circuit board, an adhesive sheet or the like is preferably used.

【0021】[0021]

【作用及び効果】本発明においては,開口穴は,表側面
から裏側面にかけて拡開したテーパー状内壁を有する。
そのため,露光を行なうE工程において,光は拡開した
テーパー状内壁上端に遮られて,テーパー状内壁全体に
は光が照射されない(図4(実施例)参照)。それ故,
前記現像,エッチングを行なっても,テーパー状内壁全
体に金属メッキを残存形成することができる。
In the present invention, the opening hole has a tapered inner wall that widens from the front side surface to the back side surface.
Therefore, in the E step of exposing, the light is blocked by the upper end of the expanded tapered inner wall, and the entire tapered inner wall is not irradiated with light (see FIG. 4 (Example)). Therefore,
Even if the development and etching are performed, the metal plating can be formed on the entire tapered inner wall.

【0022】また,上記マスクフィルムは,回路基板の
開口穴及びその周辺に位置する部分が透明であるため,
光照射の際に開口穴周辺の電着膜が露光される。そのた
め,開口穴周辺の金属メッキを除去することができる。
そのため,従来のごとくリング状メッキは形成されな
い。それ故,本発明によればリング状メッキを形成する
ことなく,開口穴内に金属メッキを残存形成することが
できる。
Further, since the mask film is transparent in the opening hole of the circuit board and the portion located around the opening hole,
At the time of light irradiation, the electrodeposition film around the opening is exposed. Therefore, the metal plating around the opening hole can be removed.
Therefore, ring-shaped plating is not formed unlike the conventional case. Therefore, according to the present invention, the metal plating can be formed in the opening hole without forming the ring-shaped plating.

【0023】また,そのため,電子部品と外層回路とを
電気的に接続するボンディングワイヤーが,リング状メ
ッキとの間でショートすることはない。したがって,本
発明によれば,上記開口部内に金属メッキを形成できる
と共に,ボンディングワイヤーとリング状メッキとのシ
ョートがなく,ファインパターン形成が容易な電子部品
搭載用基板の製造方法を提供することができる。
Therefore, the bonding wire that electrically connects the electronic component and the outer layer circuit does not short-circuit with the ring-shaped plating. Therefore, according to the present invention, it is possible to provide a method for manufacturing a substrate for mounting electronic parts in which a metal plating can be formed in the opening, a bonding wire and a ring-shaped plating are not short-circuited, and a fine pattern can be easily formed. it can.

【0024】[0024]

【実施例】【Example】

実施例1 本発明にかかる実施例について,図1〜図5を用いて説
明する。本例により製造される電子部品搭載用基板は,
図1,図2に示すごとく,内層回路51,52を有する
回路基板9と,該回路基板9に設けた開口穴99と,該
開口穴99の一端を被覆するように接着したヒートシン
ク8と,該ヒートシンク8と上記開口穴99とにより形
成される電子部品搭載用凹部900とを有している。
Example 1 An example according to the present invention will be described with reference to FIGS. The electronic component mounting board manufactured by this example is
As shown in FIGS. 1 and 2, a circuit board 9 having inner layer circuits 51 and 52, an opening hole 99 provided in the circuit board 9, and a heat sink 8 bonded so as to cover one end of the opening hole 99, It has an electronic component mounting recess 900 formed by the heat sink 8 and the opening 99.

【0025】上記開口穴99の内壁全体は,金属メッキ
5により被覆されている。回路基板9の裏側面における
上記開口穴99には,接着シート65を介して,ヒート
シンク8が回路基板9に接着固定されている。回路基板
9は,絶縁基板91,92,93を積層することにより
形成されている。絶縁基板91,92の上には,内層回
路51,52が形成されている。
The entire inner wall of the opening hole 99 is covered with the metal plating 5. The heat sink 8 is adhesively fixed to the circuit board 9 through the adhesive sheet 65 in the opening 99 on the back side of the circuit board 9. The circuit board 9 is formed by stacking insulating boards 91, 92, 93. Inner layer circuits 51 and 52 are formed on the insulating substrates 91 and 92.

【0026】回路基板9の表側面には,外層回路50が
形成されている。回路基板9において,その電子部品搭
載用凹部900と裏側面は,湿気防止のために金属メッ
キ5が被覆されている。また,表側面において,開口穴
99の周辺には前記従来例で示したリング状メッキ59
(図7,図11)は形成されていない。その他は,従来
例と同様である。
An outer layer circuit 50 is formed on the front surface of the circuit board 9. In the circuit board 9, the electronic component mounting recess 900 and the back side surface thereof are covered with a metal plating 5 to prevent moisture. Further, on the front side, the ring-shaped plating 59 shown in the above-mentioned conventional example is provided around the opening hole 99.
(FIGS. 7 and 11) are not formed. Others are the same as the conventional example.

【0027】次に,上記電子部品搭載用基板の製造方法
について説明する。先ず,図3(A)に示すA工程にお
いて,絶縁基板91,92,93を準備すると共にこれ
らを下から順に積層し,回路基板9を作製する。絶縁基
板91,92の上には内層回路51,52がそれぞれ形
成されている。次に,図3(B)に示すB工程におい
て,上記回路基板9に,該回路基板9の表側面方向から
裏側面に向けて拡開するテーパー状内壁991を有する
開口穴99を形成する。
Next, a method of manufacturing the electronic component mounting board will be described. First, in the step A shown in FIG. 3A, the insulating substrates 91, 92, 93 are prepared, and these are stacked in order from the bottom to manufacture the circuit board 9. Inner layer circuits 51 and 52 are formed on the insulating substrates 91 and 92, respectively. Next, in a step B shown in FIG. 3B, an opening hole 99 having a tapered inner wall 991 that expands from the front side surface direction of the circuit board 9 toward the back side surface is formed in the circuit board 9.

【0028】次に,図3(C)に示すC工程において,
開口穴99のテーパー状内壁991を含めて,上記回路
基板9の表面全体に金属メッキ5を施す。次に,図3
(D)に示すD工程において,上記金属メッキ5の表面
全体に電着膜6を形成する。
Next, in the step C shown in FIG.
Metal plating 5 is applied to the entire surface of the circuit board 9 including the tapered inner wall 991 of the opening hole 99. Next, FIG.
In step D shown in (D), an electrodeposition film 6 is formed on the entire surface of the metal plating 5.

【0029】次に,図4(E)に示すE工程において,
上記表側面にマスクフィルム7を載置する。マスクフィ
ルム7は外層回路形成用のパターン70が形成されてい
る。また,マスクフィルム7は,回路基板9の外層回路
を形成する位置に光が照射されないように形成してあ
る。
Next, in the step E shown in FIG.
The mask film 7 is placed on the front side surface. The mask film 7 is provided with a pattern 70 for forming an outer layer circuit. Further, the mask film 7 is formed so that the position where the outer layer circuit of the circuit board 9 is formed is not irradiated with light.

【0030】次にマスクフィルム7の上方から紫外線7
9を光照射し,電着膜6を露光する。次に,図4(F)
に示すF工程において,上記マスクフィルムを取り去
り,回路基板9を現像することにより,開口穴99周辺
の光照射された電着膜6を除去する。また,外層回路を
形成しない位置にある光照射された電着膜6も除去す
る。
Next, ultraviolet rays 7 are applied from above the mask film 7.
9 is irradiated with light to expose the electrodeposition film 6. Next, FIG. 4 (F)
In the step F shown in (1), the mask film is removed and the circuit board 9 is developed to remove the electrodeposited film 6 around the opening hole 99 which is irradiated with light. Further, the electrodeposited film 6 irradiated with light at the position where the outer layer circuit is not formed is also removed.

【0031】次に,図4(G)に示すG工程において,
上記回路基板9をエッチングすることにより,開口穴9
9周辺の金属メッキ5及び外層回路を形成しない部分の
金属メッキ5を除去する。次に,図5(H)に示すH工
程において,上記回路基板9から残りの電着膜を除去す
る。次に,図5(I)に示すI工程において,上記回路
基板9の裏側面における上記開口穴99付近に,接着シ
ート65を介してヒートシンク8を接着する。これによ
り,前記図1,図2に示した電子部品搭載用基板が得ら
れる。
Next, in the G step shown in FIG.
By etching the circuit board 9, the opening hole 9
The metal plating 5 around 9 and the metal plating 5 in the portion where the outer layer circuit is not formed are removed. Next, in step H shown in FIG. 5H, the remaining electrodeposition film is removed from the circuit board 9. Next, in a step I shown in FIG. 5I, the heat sink 8 is adhered to the vicinity of the opening hole 99 on the back side surface of the circuit board 9 via the adhesive sheet 65. As a result, the electronic component mounting board shown in FIGS. 1 and 2 is obtained.

【0032】次に,本例の作用効果につき説明する。本
例においては,図3に示すごとく,開口穴99は,表側
面から裏側面にかけて拡開したテーパー状内壁991を
有する。そのため,図4に示すごとく,露光を行なうE
工程において,紫外線79は,拡開したテーパー状内壁
991上端に遮られて,テーパー状内壁991全体には
照射しない。それ故,前記現像,エッチングを行なって
も,開口穴99全体に金属メッキ5を残存形成すること
ができる。
Next, the function and effect of this example will be described. In this example, as shown in FIG. 3, the opening hole 99 has a tapered inner wall 991 that widens from the front side surface to the back side surface. Therefore, as shown in FIG.
In the process, the ultraviolet ray 79 is blocked by the upper end of the expanded tapered inner wall 991 and does not irradiate the entire tapered inner wall 991. Therefore, even if the developing and etching are carried out, the metal plating 5 can be left and formed on the entire opening 99.

【0033】また,上記マスクフィルム7は,回路基板
9の開口穴99及びその周辺に位置する部分が透明であ
るため,光照射の際に開口穴99周辺の電着膜6が露光
される。そのため,開口穴99周辺の金属メッキ5を除
去することができる。そのため,従来のごとくリング状
メッキは形成されない。
Further, since the mask film 7 is transparent in the opening hole 99 of the circuit board 9 and the portion located around the opening hole 99, the electrodeposition film 6 around the opening hole 99 is exposed during light irradiation. Therefore, the metal plating 5 around the opening hole 99 can be removed. Therefore, ring-shaped plating is not formed unlike the conventional case.

【0034】それ故,本例によればリング状メッキを形
成することなく,開口穴99のテーパー状内壁991に
金属メッキ5を残存形成することができる。また,その
ため,電子部品3と外層回路50とを電気的に接続する
ボンディングワイヤー30がリング状メッキとの間でシ
ョートすることはない(図11参照)。
Therefore, according to this embodiment, the metal plating 5 can be left on the tapered inner wall 991 of the opening hole 99 without forming the ring-shaped plating. Therefore, the bonding wire 30 that electrically connects the electronic component 3 and the outer layer circuit 50 does not short-circuit with the ring-shaped plating (see FIG. 11).

【0035】実施例2 本例により製造された電子部品搭載用基板は,図6に示
すごとく,絶縁基板94〜96からなる回路基板9と,
該回路基板9に設けた開口穴97,98と,該開口穴9
8の一端を被覆するように接着したヒートシンク8とを
有する。上記開口穴97,98は,回路基板9の表側面
方向から裏側面に向けて拡開するテーパー状内壁97
1,981を有する。開口穴98の下方は,ヒートシン
ク8を埋設するための拡大部982が形成されている。
開口穴97,98とヒートシンク8とにより電子部品搭
載用凹部900が形成されている。
Example 2 An electronic component mounting board manufactured by this example is, as shown in FIG. 6, a circuit board 9 composed of insulating boards 94 to 96,
Opening holes 97, 98 provided in the circuit board 9 and the opening holes 9
8 has a heat sink 8 adhered so as to cover one end thereof. The opening holes 97 and 98 are tapered inner walls 97 that widen from the front side surface direction of the circuit board 9 toward the back side surface.
1,981. An enlarged portion 982 for burying the heat sink 8 is formed below the opening hole 98.
The opening holes 97 and 98 and the heat sink 8 form an electronic component mounting recess 900.

【0036】上記絶縁基板94,95の表側面には,内
層回路54,55が形成されている。上記絶縁基板94
の裏面側には接着シート65を介してヒートシンク8が
接着している。上記絶縁基板95,96と絶縁基板94
とは,接着シート65により接着している。回路基板9
の表側面には外層回路50が形成されている。その裏側
面は金属メッキ5により覆われている。
Inner layer circuits 54 and 55 are formed on the front side surfaces of the insulating substrates 94 and 95. The insulating substrate 94
The heat sink 8 is adhered to the back surface side of the via a bonding sheet 65. The insulating substrates 95 and 96 and the insulating substrate 94
And are bonded by an adhesive sheet 65. Circuit board 9
An outer layer circuit 50 is formed on the front side surface of the. The back side surface is covered with metal plating 5.

【0037】上記電子部品搭載用基板の製造方法につい
て説明する。まず,絶縁基板95,96について,実施
例1と同様にA〜H工程を行なう。なお,絶縁基板96
の裏面側には金属メッキを形成させない。また,絶縁基
板94について,B工程において,テーパー状内壁98
1及び拡大部982からなる開口穴98を形成する。以
下,C〜I工程において実施例1と同様に行なう。
A method of manufacturing the electronic component mounting board will be described. First, steps A to H are performed on the insulating substrates 95 and 96 as in the first embodiment. The insulating substrate 96
No metal plating is formed on the back side of the. Further, regarding the insulating substrate 94, in the process B, the tapered inner wall 98 is formed.
1 and the opening hole 98 including the enlarged portion 982 are formed. Thereafter, the steps C to I are performed in the same manner as in Example 1.

【0038】その後,上記絶縁基板94の表側面に接着
シート65を介して絶縁基板95,96を積層する。こ
れにより,図6に示す電子部品搭載用基板が得られる。
本例においても,開口穴97,98にはテーパー状内壁
971,981が形成されているので,実施例1と同様
の効果を得ることができる。
Thereafter, insulating substrates 95 and 96 are laminated on the front surface of the insulating substrate 94 with an adhesive sheet 65 interposed therebetween. As a result, the electronic component mounting board shown in FIG. 6 is obtained.
Also in this example, since the tapered inner walls 971 and 981 are formed in the opening holes 97 and 98, the same effect as that of the first embodiment can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例1の電子部品搭載用基板の断面図。FIG. 1 is a sectional view of an electronic component mounting board according to a first embodiment.

【図2】実施例1の電子部品搭載用基板の平面図。FIG. 2 is a plan view of the electronic component mounting board according to the first embodiment.

【図3】実施例1にかかる,電子部品搭載用基板の製造
工程説明図。
FIG. 3 is an explanatory view of the manufacturing process of the electronic component mounting board according to the first embodiment.

【図4】図3に続く,製造工程説明図。FIG. 4 is an explanatory view of the manufacturing process subsequent to FIG.

【図5】図4に続く,製造工程説明図。FIG. 5 is an explanatory view of the manufacturing process following FIG.

【図6】実施例2の電子部品搭載用基板の断面図。FIG. 6 is a cross-sectional view of an electronic component mounting board according to a second embodiment.

【図7】従来例の電子部品搭載用基板の断面図。FIG. 7 is a cross-sectional view of a conventional electronic component mounting substrate.

【図8】従来例にかかる,電子部品搭載用基板の電着膜
法による製造工程説明図。
FIG. 8 is an explanatory view of a manufacturing process of an electronic component mounting substrate according to a conventional example by an electrodeposition film method.

【図9】図8に続く,製造工程説明図。9 is an explanatory view of the manufacturing process following FIG. 8. FIG.

【図10】図9に続く,製造工程説明図。10 is an explanatory view of the manufacturing process subsequent to FIG. 9. FIG.

【図11】従来例の電子部品搭載用基板の平面図。FIG. 11 is a plan view of a conventional electronic component mounting board.

【図12】他の従来例において,得ようとする電子部品
搭載用基板の断面図。
FIG. 12 is a cross-sectional view of an electronic component mounting board to be obtained in another conventional example.

【図13】他の従来例にかかる,電子部品搭載用基板の
他の電着膜法による製造工程説明図。
FIG. 13 is an explanatory view of a manufacturing process of an electronic component mounting substrate according to another conventional example by another electrodeposition film method.

【図14】他の従来例にかかる,電子部品搭載用基板の
製造方法の問題点を示す説明図。
FIG. 14 is an explanatory view showing a problem of a method of manufacturing an electronic component mounting board according to another conventional example.

【図15】更に他の従来例にかかる,電子部品搭載用基
板の半田剥離法による製造工程説明図。
FIG. 15 is an explanatory view of a manufacturing process by a solder peeling method of an electronic component mounting board according to still another conventional example.

【図16】図15に続く,製造工程説明図。FIG. 16 is an explanatory view of the manufacturing process following FIG. 15.

【図17】図16に続く,製造工程説明図。FIG. 17 is an explanatory view of the manufacturing process continued from FIG. 16;

【符号の説明】[Explanation of symbols]

3...電子部品, 30...ボンディングワイヤー, 5...金属メッキ, 50...外層回路, 6...電着膜, 65...接着シート, 8...ヒートシンク, 9...回路基板, 900...電子部品搭載用凹部, 91〜96...絶縁基板, 97〜99...開口穴, 971,981,991...テーパー状内壁, 3. . . Electronic components, 30. . . Bonding wire, 5. . . Metal plating, 50. . . Outer layer circuit, 6. . . Electrodeposition film, 65. . . Adhesive sheet, 8. . . Heat sink, 9. . . Circuit board, 900. . . Recesses for mounting electronic components, 91-96. . . Insulating substrate, 97-99. . . Open hole, 971, 981, 991. . . Tapered inner wall,

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 回路基板と,該回路基板に設けた電子部
品搭載用凹部を形成するための開口穴とを有する電子部
品搭載用基板の製造方法において,回路基板を準備する
A工程と,該回路基板の表側面から裏側面に向けて拡開
するテーパー状内壁を有する開口穴を形成するB工程
と,上記開口穴の表面を含めた回路基板の全表面を金属
メッキにより被覆するC工程と,上記金属メッキの表面
を電着膜により被覆するD工程と,上記回路基板の表側
面に配線パターン形成用の露光用のマスクフィルムを載
置し,該マスクフィルムの上から光照射するE工程と,
上記回路基板上のマスクフィルムを取り去り,回路基板
を現像することにより,開口穴周辺の電着膜を除去する
F工程と,上記回路基板をエッチングすることにより表
側面における開口穴周辺の金属メッキを除去するG工程
と,上記回路基板から残りの電着膜を除去するH工程と
よりなることを特徴とする電子部品搭載用基板の製造方
法。
1. A method of manufacturing an electronic component mounting board, comprising: a circuit board; and an opening hole for forming an electronic component mounting recess provided in the circuit board; A step B of forming an opening hole having a tapered inner wall that expands from the front side surface to the back side surface of the circuit board, and a step C of coating the entire surface of the circuit board including the surface of the opening hole with metal plating. A step D of coating the surface of the metal plating with an electrodeposition film, and a step E of placing an exposure mask film for forming a wiring pattern on the front surface of the circuit board and irradiating the mask film with light. When,
The masking film on the circuit board is removed, and the circuit board is developed to remove the electrodeposition film around the opening hole, and the circuit board is etched to remove metal plating around the opening hole on the front surface. A method of manufacturing an electronic component mounting substrate, comprising: a G step of removing and an H step of removing the remaining electrodeposition film from the circuit board.
JP4328900A 1992-11-13 1992-11-13 Manufacture of electronic part mounting board Pending JPH06152143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4328900A JPH06152143A (en) 1992-11-13 1992-11-13 Manufacture of electronic part mounting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4328900A JPH06152143A (en) 1992-11-13 1992-11-13 Manufacture of electronic part mounting board

Publications (1)

Publication Number Publication Date
JPH06152143A true JPH06152143A (en) 1994-05-31

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ID=18215350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4328900A Pending JPH06152143A (en) 1992-11-13 1992-11-13 Manufacture of electronic part mounting board

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JP (1) JPH06152143A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008098482A (en) * 2006-10-13 2008-04-24 Toshiba Corp High frequency circuit board and method for manufacturing the same
US9583459B2 (en) 2013-05-30 2017-02-28 Linxens Holding Method for producing a printed circuit, printed circuit obtained by this method and electronic module comprising such a printed circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008098482A (en) * 2006-10-13 2008-04-24 Toshiba Corp High frequency circuit board and method for manufacturing the same
US9583459B2 (en) 2013-05-30 2017-02-28 Linxens Holding Method for producing a printed circuit, printed circuit obtained by this method and electronic module comprising such a printed circuit

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