JPH06151868A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve endurance resistance of a nonvolatile semiconductor memory device in which electrons in a floating gate are erased by an F-N tunneling to a drain diffusion layer. CONSTITUTION:A part of a drain region 9 of an EEPROM cell is formed so that the part dives below a floating gate 3, and the drain region 9 comprises a shallow diffusion layer region 20 using an arsenic arom and a phosphorus atom as an impurity and a deep diffusion layer region 21 formed so as to surround the shallow diffusion layer 20 using the phosphorus atom as the impurity. Further, the drain region 9 is characterized in that a surface concentration of the arsenic atom of the shallow diffusion layer 20 is 5X10<15>atoms/cm<2> or more. By forming the surface concentration of the arsenic atom of the shallow diffusion layer 20 to 5X10<15>atoms/cm<2> or more in the above construction, a width of a depletion layer occurring in the circumference of the drain diffusion layer in applying a high voltage can be shortened and the occurrence number of holes in the depletion layer can be reduced. Thus, a trap of electrons in an oxide film can be controlled and a window narrowing is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and particularly to an electrically erasable / erasable EEP.
Relating to ROM cells.

[0002]

2. Description of the Related Art FIG. 5 shows a general SISOS (SIde wall).
It is a sectional view of a Select gate On Source side) type EEPROM cell.

As shown in FIG. 5, a P-type silicon substrate 10 is provided.
A first oxide film (gate oxide film) 102 is formed on the surface of the first oxide film 102.
Are formed. A floating gate 103 is formed on the first oxide film 102. This floating gate 103
A second oxide film 104 is formed on the top. This second
A control gate 105 is formed on the oxide film 104 in such a manner that the gate ends on the source side and the drain side are self-aligned with the floating gate 103. Floating gate 10
3 and the source side wall of the control gate 105, a third oxide film 106 is formed, and a fourth oxide film 107 is formed on the surface of the substrate 101. A select gate 108 whose gate end is self-aligned with the floating gate 103 is formed on the third oxide film 106 and the fourth oxide film 107. In the substrate 101, a drain region 109 whose region edge is self-aligned with the end of the floating gate 103 and a source region 110 whose region edge is self-aligned with the end of the select gate 108 are formed. . The operation of this type of cell will be described.

At the time of writing, a voltage close to a threshold value, for example, 1.5 V is applied to the select gate 108 to control the control gate 105.
A program voltage of, for example, 12 V is applied to the drain 10
By applying a power supply voltage, for example, 5 V, the hot electrons are injected from the source side to the floating gate 103.

At the time of erasing, the selection gate 108 and the control gate 1
05 is grounded, the source 110 is opened, and an erase voltage, for example, 12 V is applied to the drain 109,
Electrons are extracted from the floating gate 103 to the drain diffusion layer 109 by an FN tunnel.

At the time of reading, for example, 5 V is applied to the select gate 108 and the control gate 105, and a read voltage of 1 V is applied to the drain 109 to check the presence / absence of a channel current.

In this type of cell, conventionally, the implantation amount of arsenic impurity atoms for forming the drain high-concentration diffusion layer 120 is similar to that of the source diffusion layer, for example, 1 to 5 × 1.
0 ¹⁵ atoms / cm ² I am trying. However, the cell of the type shown in FIG. 5 has hitherto been unable to obtain sufficient reliability for the number of times of rewriting. The reason will be described below.

First, in this type of cell, the characteristic deterioration that the Vth on the erasing side increases as the number of times of rewriting increases. This is the window narrwing
This is shown in FIG. 6. Figure 6
Show that erasing is less likely to occur as the number of rewrites increases. The change on one writing side is small and there is no problem.

This window narrowing is caused by the trapping of electrons in the oxide film. When erasing
The electrons are extracted from the floating gate to the drain diffusion layer by the FN tunnel, but at this time, some of the electrons are trapped in the oxide film. This electron trap lowers the electron F-N tunnel efficiency at the time of erasing, and causes a window narrowing on the erasing side. Further, when holes are trapped in the oxide film, the number of electrons trapped in the oxide film increases. When the drain concentration is not sufficiently high as in the prior art, this hole trapping occurs many times, and the number of electrons trapped in the oxide film increases, and the window narrowing on the erase side is accelerated.

In order to explain why this hole trap changes depending on the drain concentration, first, what carriers are generated and transferred during the erase operation will be described with reference to FIGS. 7 and 8. . FIG. 7 is a cross-sectional view of the vicinity of the drain diffusion layer during the erase operation, and FIG. 8 is a band diagram on the drain diffusion layer at this time.

In the erase operation, a high voltage is applied to the drain diffusion layer as described above. Thereby, the electrons A in the floating gate are extracted to the drain diffusion layer by FN tunneling, but some of them are trapped in the oxide film.

On the other hand, when the electron A, which appears with energy in the conduction band of the drain diffusion layer, loses energy in the depletion layer of the drain diffusion layer, energy is given to the electron in the valence band, and electron Be-hole Bh. Generate a pair. This hole Bh
Is accelerated toward the oxide film by the vertical electric field in the depletion layer. If the energy of the generated holes is higher than the energy barrier for holes in the oxide film, the holes Bh are injected into the oxide film just above the generated holes, and part of them are trapped in the oxide film. As described above, this region is also a region through which electrons are transmitted by F-N tunneling, and electron traps easily occur due to the trap of holes Bh.

According to a simple calculation, the depletion layer width W and the drain diffusion layer concentration N _D have the following relationship. In _Equation 1, E _OX is an electric field applied to the oxide film.

[0014]

[Equation 1]

That is, as in the conventional case, the drain diffusion layer concentration N
_{When D} is thin, the width of the depletion layer expands, the number of holes generated in the depletion layer becomes larger than that in the case where the concentration of the drain diffusion layer is high, and the number of holes jumping into the oxide film immediately above increases.
For this reason, tunnel electrons are easily captured during erase. That is, the thinner the drain diffusion layer concentration, the more endurance window narrowing (Endurance win
There was a reliability issue that (dow narrowing) was accelerated.

[0016]

SUMMARY OF THE INVENTION It is an object of the present invention to have a high endurance resistance in a non-volatile semiconductor memory device having an EEPROM cell that erases electrons in a floating gate into a drain diffusion layer by FN tunneling. It is to provide a nonvolatile semiconductor memory device.

[0017]

A non-volatile semiconductor memory device according to the present invention has a SISOS type cell, a drain region of which is formed so as to partially underlie a floating gate. The surface of the arsenic atoms of the shallow diffusion layer is composed of a shallow diffusion layer region containing atoms as a main impurity and a deep diffusion layer region formed so as to surround the shallow diffusion layer and containing phosphorus atoms as a main impurity. Concentration is 5 × 10 ¹⁵ atoms / cm ² It is characterized by the above.

[0018]

According to the nonvolatile semiconductor memory device having the above structure,
The surface concentration of arsenic atoms in the shallow diffusion layer forming the drain region is 5 × 10 ¹⁵ atoms / cm ² As described above, the width of the depletion layer generated around the drain diffusion layer when a high voltage is applied can be reduced. As the width of the depletion layer becomes smaller, the number of holes generated in the depletion layer decreases, so that the holes injected into the oxide film can be reduced. Therefore, the trapping of electrons in the oxide film is not accelerated,
The problem of window narrowing can be reduced.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a SISO according to an embodiment of the present invention.
2A to 2D are cross-sectional views showing the EEPROM cell shown in FIG. 1 for each main step.

First, as shown in FIG. 2A, a first region having a thickness of about 100 Å is formed on the surface of the P-type silicon substrate 1 in the element region surrounded by a field oxide film (not shown).
A gate oxide film 2 is formed by a thermal oxidation method, a first polycrystalline silicon film 3 having a thickness of 1000 angstrom is deposited on the gate oxide film 2, and then phosphorus diffusion is performed thereon. Thereafter, although not shown, a part of the first polycrystalline silicon is removed by etching to form an opening (cell slit) for separating the floating gate for each cell. Then, a 100 Å thick silicon oxide film (not shown) is formed on the surface of the first polycrystalline silicon 3 by a thermal oxidation method, and then a 150 Å silicon nitride film (not shown) is formed by LPCVD. And then thermally oxidize the surface of the silicon nitride film to about 5
A silicon oxide film (not shown) of 0 angstrom is formed, and an interlayer insulating film 4 made of a laminated film of these is formed.
A 4000 angstrom second polycrystalline silicon layer 5 is deposited thereon, and then phosphorus diffusion is performed thereon.

Next, as shown in FIG. 2B, resist patterning is performed to etch the laminated structure portion of the second polycrystalline silicon film 5, the interlayer insulating film 4, and the first polycrystalline silicon film 3. As a result, the first polycrystalline silicon film 3 becomes a floating gate and the second polycrystalline silicon film 5 becomes a control gate. After that, thermal oxidation is performed to form a semiconductor layer having a thickness of 2 on the surface.
An oxide film having a thickness of 50 Å and a thermal oxide film (not shown) having a thickness of 500 Å are simultaneously formed on the side surfaces of the first and second polycrystalline silicon layers at the same time. An angstrom silicon nitride film (not shown) is deposited by LPCVD, and the surface of the silicon nitride film is thermally oxidized to form a silicon oxide film (not shown) of about 50 angstroms. Second interlayer insulating film 6 and second gate insulating film 7 made of a film
Was formed. After this, the third of 4000 angstrom
A polycrystalline silicon film 8 is deposited by the LPCVD method, and phosphorus diffusion is performed on this.

Next, as shown in FIG. 2C, resist patterning is performed so as to leave a contact region (not shown) of the third polycrystalline silicon film 8 and a third etching is performed by RIE of an anisotropic etching technique. The polycrystalline silicon film is etched. As a result, the contact region covered with the resist and the second polycrystalline silicon film 5 / interlayer insulating film 4 / first
The third polycrystalline silicon film 8 remains on the side wall of the laminated structure portion of the polycrystalline silicon film 3. The third polycrystalline silicon film 8 left on the side wall becomes a selective gate.

Next, as shown in FIG. 2D, after resist patterning is performed so as to cover the third polycrystalline silicon film 8 on the source side and the contact region, the drain is formed by the CDE of the isotropic etching technique. The third polycrystalline silicon film 8 on the side was etched. Subsequently, 1 × 10 ¹⁶ atoms / c of arsenic ions is applied to the drain region 9.
m ² , Phosphorus ions at 1 × 10 ¹⁴ atoms / cm ² Ion implantation is performed, and thereafter, annealing is performed at 1000 ° C. for 30 minutes. By these implantation steps, the drain region 9 becomes
A shallow high-concentration diffusion layer 20 containing arsenic atoms and phosphorus atoms as main impurities, and a deep low-concentration diffusion layer 21 surrounding the shallow high-concentration diffusion layer 20 and containing phosphorus atoms as main impurities are formed. Like In addition, a part of the shallow high-concentration diffusion layer 20 comes under the floating gate 3. Next, arsenic ions are added to the source region 10 by 5 × 10 5.
¹⁵ atoms / cm ² Ion implantation was performed.

Next, as shown in FIG. 1, the interlayer insulating film 11 is formed.
After depositing and reflowing and flattening, contact hole 1
2 is opened, metal wiring material 13 is deposited, and patterning is performed to form wiring. After that, the PSG film 14 and the plasma SiN film 1 are formed as a passivation film.
5 is deposited, and a pad portion (not shown) is opened. The non-volatile semiconductor memory device according to the embodiment of the present invention is completed by the above manufacturing method.

According to the above structure, the drain diffusion layer 9 is
Arsenic ions at 1 × 10 ¹⁶ atoms / cm ² , Phosphorus ions at 1 × 10 ¹⁴ atoms / cm ² And the high concentration diffusion layer 20 because it is obtained by introducing a large amount of impurities.
The impurity concentration N _D can be sufficiently increased. Since the impurity concentration N _D of the high-concentration diffusion layer 20 is sufficiently high as described above, the width of the depletion layer generated around the drain diffusion layer when a high voltage is applied to the drain diffusion layer becomes small, and the depletion layer is generated in this depletion layer. The number of holes that are formed is reduced. The holes generated in the depletion layer are accelerated by the vertical electric field and injected into the oxide film immediately above the depletion layer. The trap is not accelerated and the window narrowing problem is reduced.

FIGS. 3 and 6 are views showing window narrowing, respectively. As shown in FIG. 6, the implantation dose of arsenic ions was set to 1 × 10 ¹⁵ atoms / cm ^2. When the drain diffusion layer is obtained as, that is, the surface concentration of the drain diffusion layer is 1 × 10 ¹⁵ atoms / cm ² In case of
Window narrowing is W / E (write / erase)
The number becomes remarkable from about 500 times. On the other hand, as shown in FIG. 3, the implantation dose of arsenic ions is set to 1 × 10 ¹⁶ atoms / cm ² as in the above embodiment. When the drain diffusion layer is obtained, that is, the surface concentration of the drain diffusion layer is 1 × 10 ¹⁶ atoms / cm ² In the case of the degree, the window narrowing W / E number is 10 ⁴ It is small enough even at times. In FIG. 3, the implantation dose of arsenic ions is 5 × 10 ¹⁵ atoms / cm ^2. When the drain diffusion layer is obtained as, that is, the surface concentration of the drain diffusion layer is 5 × 10 5.
¹⁵ atoms / cm ² The case is also illustrated. Even in this case, the endurance window narrowing is improved as compared with the conventional example shown in FIG. As described above, by increasing the concentration of arsenic atoms in the drain diffusion layer, the endurance resistance of the EEPROM cell can be improved.

FIG. 4 shows the W / E10 ^4. From Vth in the erased state after cycles to Vth in the erased state after 10 cycles
ΔVt indicating the window / narrowing amount minus th
It is a figure which shows the relationship between h and the surface concentration of a drain diffusion layer. The effect of reducing the amount of narrowing is that the implantation dose of arsenic ions in the drain diffusion layer is 5 × 10 ¹⁵ atoms / cm 3.
² That is, the surface concentration of the drain diffusion layer is 5 × 10 ^15.
atoms / cm ² From the above, it can be seen that the state is almost saturated.

As described above, the depletion layer width W, the drain diffusion layer concentration N _D, and the oxide film electric field E _OX have the relationship of the above expression 1. In view of this relation, the window narrowing is also improved by applying a rounded erase pulse to the drain to reduce the oxide film electric field E _OX and reduce the depletion layer width to reduce hole injection. It has been confirmed that the model described above is correct. However, the erase pulse with roundness is effective as a model verification, but is not practical in practice, and hole injection can be reduced even when the roundness is small. The structure to make it practical is practical.

[0029]

As described above, according to the present invention, in the nonvolatile semiconductor memory device including the EEPROM cell for erasing the electrons in the floating gate to the drain diffusion layer by FN tunneling, high endurance resistance is provided. It is possible to provide a nonvolatile semiconductor memory device having

[Brief description of drawings]

FIG. 1 is a SISOS according to an embodiment of the present invention.
FIG. 3 is a sectional view of a type EEPROM cell.

FIG. 2 is a diagram illustrating a method of manufacturing the EEPROM cell shown in FIG. 1, and FIGS. 2A to 2D are cross-sectional views showing respective main steps.

FIG. 3 is a diagram showing a window narrowing of an EEPROM cell according to the present invention.

FIG. 4 is a diagram showing the relationship between the window / narrowing amount and the surface concentration of the drain diffusion layer of the EEPROM cell according to the present invention.

FIG. 5 is a sectional view of a general SISOS type EEPROM cell.

FIG. 6 shows a window of a conventional EEPROM cell.
The figure which shows a narrowing.

FIG. 7 is a cross-sectional view of the vicinity of a drain diffusion layer during an erase operation.

FIG. 8 is a band diagram on the drain diffusion layer during an erase operation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate, 2 ... 1st gate oxide film, 3 ... floating gate (1st polycrystalline silicon film), 4 ... interlayer insulation film,
5 ... Control gate (second polycrystalline silicon film), 6 ... Second interlayer insulating film, 7 ... Second gate insulating film, 8 ... Select gate (third polycrystalline silicon film), 9 ... Drain region, 10 ... source
Region, 11 ... interlayer insulating film, 12 ... contact hole, 13
... Wiring (metal wiring material), 14 ... PSG film, 15 ... Plasma SiN film, 20 ... Drain high concentration diffusion layer, 21 ...
Drain low concentration diffusion layer.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, a first insulating film formed on the surface of the semiconductor substrate, a floating gate provided on the first insulating film, and a floating gate on the floating gate. A second insulating film provided, and a control gate provided on the second insulating film, the source side and drain side gate ends of which are self-aligned with the floating gate, respectively.
The floating gate and the control gate are provided via a third insulating film formed on sidewalls of the source side and a fourth insulating film formed on the surface of the semiconductor substrate, and the gate end is self-aligned with the floating gate. A source region formed in the semiconductor substrate and a source region formed in the semiconductor substrate, the source region being self-aligned with the select gate aligned, and the region edge being formed in the semiconductor substrate. A memory cell comprising a drain region self-aligned with the floating gate end, the source region comprising a diffusion layer region containing arsenic atoms as a main impurity, and the drain region comprising Part is formed under the floating gate, and is formed so as to surround the shallow diffusion layer and a shallow diffusion layer region in which arsenic atoms and phosphorus atoms are the main impurities. Consists of a deep diffusion layer region with the impurity, the surface concentration of arsenic atoms in the shallow diffusion layer constituting the drain region is 5 × 10 ¹⁵ atoms / cm ² A non-volatile semiconductor memory device characterized by the above.