JPH06151758A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enable a semiconductor memory to be improved in yield and elongated in data-hold time by a method wherein a connection hole is lessened in aspect ratio so as to enhance a wiring layer in covering properties, and a charge storage electrode of a capacitor is kept unconnected to a semiconductor substrate. CONSTITUTION:After a capacitor is formed on a semiconductor substrate 11, a semiconductor layer 17 where a channel can be formed and N-type impurity layers 18 which serve as a source and a drain are formed, and a gate oxide film 19, a gate electrode 20, and a second wiring layer 23 are formed on the semiconductor layer 17, whereby a connection hole 22 provided to the second wiring layer 23 can be lessened in aspect ratio. No short circuit occurs between a capacitor electrode 14 and the connection hole 22, a capacitor charge storage electrode 14 is prevented from being connected to a semiconductor substrate 11, and the stored static charge is prevented from being discharged to the semiconductor substrate 11, so that a semiconductor memory of this design can be elongated in data-hold time and improved in yield and reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device, ie, a DRAM, which stores data by a transistor and a capacitor and can be written and read at any time.

[0002]

2. Description of the Related Art Conventionally, a method of increasing the capacitance of a capacitor has been considered as a means for increasing the data storage retention time in a DRAM. Starting from a planar capacitor formed of a conductor with a diffusion layer on the surface of the semiconductor substrate and an insulating film, to cope with subsequent miniaturization and to obtain a larger capacitor capacitance, the semiconductor substrate is dug to reduce the capacitor area. There is a trenched capacitor to be increased, and a stacked capacitor to form a capacitor on a gate electrode, which appears next due to an increase in leak current of the trenched capacitor to a semiconductor substrate. The most common DRAM cell structure at present is shown in FIG. The structure of a conventional DRAM will be described with reference to FIG.
51 is a P-type semiconductor substrate, 52 is a LOCO, for example.
An element isolation oxide film formed by the S method, 53 is a gate oxide film of about 15 nm formed by an oxidation technique, 54 is a gate electrode made of polycrystalline silicon containing impurities such as phosphorus, and 55 is arsenic on a semiconductor substrate, for example. Is an N-type impurity diffusion layer serving as a source / drain formed by implanting silicon, 56 is a first interlayer insulating film made of a silicon oxide film deposited by, for example, a CVD technique, and 57 is, for example, a 300 nm phosphorus film serving as a capacitor portion charge storage electrode. Polycrystal silicon containing impurities such as 58, 58 is a connection hole for electrically connecting the capacitance section charge storage electrode 57 and the N-type impurity diffusion layer 55, and 59 is, for example, C
A silicon nitride film having a thickness of about 10 nm deposited by the VD technique, 60 is a capacitor constant voltage electrode of polycrystalline silicon containing impurities such as phosphorus having a thickness of about 150 nm, and 61 is a silicon oxide film containing impurities such as phosphorus and boron. (BPS
G film), 62 is a metal wiring layer containing a trace amount of silicon or the like, or a silicide wiring layer of a refractory metal and silicon, 63 is a connection hole for electrically connecting the wiring layer 62 and the N-type impurity diffusion layer 55. Is. In the above structure, data reading and writing are performed with the potential of the gate electrode 54 raised, and the electrode 5 of the capacitor portion connected to the semiconductor substrate 51.
It is carried out by accumulating the electric charge in 7, discharging the accumulated electric charge, and discharging the accumulated electric charge amount.

[0003]

In this conventional DRAM structure, since the capacitance portion is on the gate electrode, the ratio of the opening diameter to the depth of the connection hole of the second wiring layer (hereinafter referred to as the aspect ratio) is It becomes large, and the coverage in the connection hole of the second wiring layer deteriorates. In addition, the gap between the electrode of the capacitance section and the connection hole of the second wiring layer is narrowed, so that a short circuit occurs between the second wiring layer and the capacitance section electrode in the connection hole portion, resulting in a decrease in yield and deterioration of reliability. there were. Further, since the space between the connection hole of the second wiring layer and the capacitor electrode is required to some extent, the area of the capacitor cannot be increased and the required capacitance value cannot be obtained. Alternatively, if an attempt is made to secure a required capacitance by utilizing the area of the side wall by increasing the thickness of the electrode of the capacitor portion, there is a problem that the aspect ratio of the connection hole of the second wiring layer is deteriorated. Further, since the electrode of the capacitor portion is connected to the N-type impurity layer of the semiconductor substrate, the charge accumulated in the electrode of the capacitor portion is discharged due to leakage to the semiconductor substrate, the data retention time is deteriorated, and the yield is increased. There was also a problem that it decreased.

An object of the present invention is to provide a semiconductor memory device capable of reducing the aspect ratio of a connection hole, improving the coverage of a wiring layer to improve the yield, and extending the data storage retention time. It is in.

[0005]

According to another aspect of the present invention, there is provided a semiconductor memory device including an impurity diffusion layer formed on a semiconductor substrate and a charge holding layer formed via a first insulating film formed on the impurity diffusion layer. Conductive layer, a first conductive type semiconductor layer serving as a channel portion formed through a second insulating film formed on the charge holding conductive layer, and a part of the first conductive type semiconductor layer A second conductivity type semiconductor serving as a source / drain, and a connection hole for electrically connecting the conductor layer for holding charges and a part of the second conductivity type semiconductor layer,
A first wiring layer formed via a third insulating film formed on the first conductivity type semiconductor layer and a fourth insulating film formed on a fourth insulating film deposited on the first wiring layer 2 wiring layers,
The semiconductor device further includes a connection hole for electrically connecting the second conductive type semiconductor layer and the second wiring layer.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, 11 is, for example, a P-type semiconductor substrate, 12 is, for example, an N-type impurity diffusion layer serving as a capacitor constant voltage electrode into which phosphorus or arsenic is introduced by an ion implantation method,
Numeral 13 is a 9 nm silicon nitride film deposited by, for example, the CVD method as a capacitive insulating film, and 14 is an electrode for accumulating charge in the capacitive part made of a polycrystalline silicon film deposited by, for example, the CVD method. These 12, 13, and 14 form a capacitance section. Reference numeral 15 is an interlayer insulating film made of, for example, a silicon oxide film buried by a CVD method, and 17 is a thickness 200 formed by, for example, heat-treating an amorphous silicon layer at a low temperature.
is a semiconductor layer having a thickness of about nm, and 18 is, for example, the semiconductor layer 17
An N-type impurity layer serving as a source / drain formed by introducing an impurity such as arsenic or the like by an ion implantation method, and an interlayer insulating film 15 for connecting the N-type impurity layer 18 and the capacitance section charge storage electrode 14 are provided, for example. Numeral 19 is a buried contact hole in which polycrystalline silicon is buried by a CVD method in a contact hole formed by using a photolithography technique, 19 is a 15 nm silicon oxide film to be a gate oxide film by, for example, a thermal oxidation method, and 20 is, for example, a CVD method. A gate electrode made of a polycrystalline silicon film having a thickness of 150 nm formed by the method
Second interlayer insulating film made of a silicon oxide film having a thickness of 300 nm by the method, 22 is a connection hole formed by photolithography of the second interlayer insulating film 21, and 23 is a second wiring layer made of refractory metal silicide, for example. ing. The semiconductor memory device having the above-described structure has the semiconductor layer 17 capable of forming a channel on the capacitor portion, the source / drain made of the N-type impurity layer 18, and the transistor formed of the gate, Data can be stored in the same manner as in the conventional semiconductor memory device by accumulating or discharging the charges of the partial charge accumulating electrode 14. As described above, by forming the capacitance section on the lower side of the semiconductor layer 17 and the wiring section on the upper side, it is not necessary to consider the distance between the second wiring layer 23 and the capacitance section electrode, and the area of the capacitance section can be made larger than in the conventional case. It becomes possible to do. In addition, the capacitors 12, 13, 14 are connected to the gate electrode 20.
Since it is not formed on the top surface, the aspect ratio of the connection hole 22 is half that of the conventional one, and the coverage of the second wiring layer is also improved. Further, since the capacitor electrode 14 for accumulating charges is not in contact with the semiconductor substrate, the largest charge leak source is eliminated, and the storage retention time is extended.

FIG. 2 is a sectional view of a semiconductor memory device according to another embodiment of the present invention. 31 is, for example, a P-type semiconductor substrate, 32
Is a capacitor constant voltage electrode made of an N-type impurity diffusion layer into which phosphorus or arsenic or the like is introduced by an ion implantation method by etching a P-type semiconductor substrate using a photolithography technique, and 33 is deposited by, for example, a CVD method. Done 9
A capacitor insulating film made of a silicon nitride film having a thickness of 34 nm is an electrode for accumulating a charge of a capacitor made of a polycrystalline silicon film buried by, for example, a CVD method, and a constant voltage electrode 32 for the capacitor which is dug into the substrate. The capacitor insulating film 33 and the capacitor charge storage electrode 34 form a capacitor. The rest of the structure is similar to that of the first embodiment. Since the capacitor portion charge storage electrode 34 is not in contact with the semiconductor substrate 31, it is not necessary to consider the leakage of charges to the semiconductor substrate 31, and by digging into the semiconductor substrate 31, it is easy to increase the surface area of the capacitor portion. It is possible to increase the value and extend the memory retention time.

[0008]

As described above, according to the present invention, the semiconductor layer capable of forming a channel and the N-type impurity layer serving as the source / drain are formed on the capacitor portion to form the connection hole of the second wiring layer. Since the aspect ratio is reduced and the capacitor portion and the wiring are separated above and below the semiconductor layer, the risk of short circuit between the capacitor portion electrode and the wiring is eliminated, and the yield and reliability are improved. In addition, the capacitor portion charge storage electrode is not in contact with the semiconductor substrate, and the stored charge is not discharged due to leakage to the semiconductor substrate,
In addition, since the semiconductor substrate can be dug down to increase the surface area of the capacitor portion, the data retention time can be significantly extended and the yield can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor memory device according to another embodiment of the present invention.

FIG. 3 is a cross-sectional view of an example of a conventional semiconductor memory device.

[Explanation of symbols]

 11, 31, 51 P-type semiconductor substrate 12, 32, 60 Capacitance part constant voltage electrode 13, 33, 59 Capacitance insulating film 14, 34, 57 Capacitance part charge storage electrode 15, 35, 56 First interlayer insulating film 16, 36, 58 Capacitance part electrode connection hole 17, 37 Semiconductor layer 18, 38 N-type impurity layer 19, 39, 53 Gate insulating film 20, 40, 54 Gate electrode 21, 41, 61 Second interlayer insulating film 22, 42, 63 Second Wiring Layer Connection Hole 23, 43, 62 Second Wiring Layer 51 Element Isolation Oxide Film 55 N-type Impurity Diffusion Layer

Claims (1)

[Claims] 1. An impurity diffusion layer formed on a semiconductor substrate, a charge-holding conductor layer formed via a first insulating film formed on the impurity diffusion layer, and the charge-holding conductor. A first conductive type semiconductor layer which is a channel formed through a second insulating film formed on the layer and a second source / drain which is formed in a part of the first conductive type semiconductor layer
A conductive semiconductor, a connection hole for electrically connecting the charge retaining conductor layer and a part of the second conductive semiconductor layer, and a third hole formed on the first conductive semiconductor layer. Wiring layer formed via the insulating film, the second wiring layer formed via the fourth insulating film deposited on the first wiring layer, the second conductivity type semiconductor layer, and A semiconductor memory device having a connection hole for electrical connection with a second wiring layer.