JPH06151754A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory device which is prevented from deteriorating in soft error resistance, wherein an access transistor is restrained from deteriorating in characteristics, a capacitor dielectric film is prevented from deteriorating in quality, and the lower electrode of a stacked capacitor is lessened in contact resistance. CONSTITUTION:In a semiconductor memory device called a stacked capacitor DRAM, an arsenic-doped polycrystalline Si film 30 in contact with the one diffusion region 15 of an access transistor 23, a phosphorus-doped polycrystalline Si film 32 formed on the film 30, and an SiO2 film 31 formed at least, on a part of the polycrystalline Si film 30 so as to prevent phosphorus from diffusing into the polycrystalline Si film 30 and the diffusion region 15 are provided. Si films 30 and 32 are made to serve a lower electrode of a stacked capacitor 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device called a stacked capacitor DRAM.

[0002]

2. Description of the Related Art FIG. 2 shows a stacked capacitor DRAM.
FIG. 11 is a cross-sectional view showing a conventional example of the memory cell of FIG. As shown in this figure, the polycrystalline Si film 12, W is formed on the P-type Si substrate 11.
The Si _x 13 and the side wall 14 are provided, and the access transistor 15 having the LDD structure is formed. Here, regions 16 and 17 are diffusion regions of access transistor 15 in which N-type impurities are ion-implanted. further,
Interlayer insulating film 1 formed on access transistor 15
A contact hole 19 reaching the diffusion region 16 is formed in the hole 8.

Next, the diffusion region 1 is formed on the P-type Si substrate 11.
6 and a polycrystalline S doped with N-type impurities in order to reduce the contact resistance with the diffusion region 16.
An i film 20 is formed. A capacitor dielectric film 21 such as an ONO film is formed on the polycrystalline Si film 20,
A polycrystalline Si film 22 into which a type impurity is introduced is sequentially laminated on the entire surface to form a stacked capacitor 23.
Here, the polycrystalline Si film 20 is a lower electrode and is made of polycrystalline Si.
The film 22 is the upper electrode. Further, an interlayer insulating layer 24 is formed on the entire surface of the stacked capacitor 23,
A contact hole 25 reaching the diffusion region 17 is opened, and although not shown, the diffusion region 1 is formed through the contact hole 25.
The bit line that contacts 7 is patterned.

[0004]

However, when phosphorus is used as the N-type impurity to be introduced into the polycrystalline Si film 20, phosphorus has a large diffusion coefficient, so that the phosphorus is diffused through the contact hole 19 into the polycrystalline Si film. From 20 to the Si substrate 11, the diffusion region 16 is deeply joined as shown in FIG. When the junction of the diffusion region 16 becomes deep in this way, problems such as soft error resistance and deterioration of the characteristics of the access transistor 23 occur. On the other hand, when arsenic having a small diffusion coefficient is introduced into the polycrystalline Si film 20, the junction of the diffusion region 16 becomes shallow, but the film quality of the capacitor dielectric film 21 formed on the polycrystalline Si film 20 deteriorates. To do.

Therefore, the present invention prevents the deterioration of the soft error resistance and the characteristics of the access transistor, and at the same time, prevents the deterioration of the film quality of the capacitor dielectric film, while reducing the contact resistance of the lower electrode of the stacked capacitor. It is an object to provide a semiconductor memory device.

[0006]

A semiconductor memory device according to the present invention is a semiconductor memory device having a memory cell composed of one MIS transistor and one stacked capacitor, and one diffusion of one of the MIS transistors. A first semiconductor film which is in contact with the region and is formed by introducing a first impurity having a relatively small diffusion coefficient;
Is formed on the semiconductor film to prevent the diffusion of the second impurity having a relatively large diffusion coefficient, and the second impurity having a relatively large diffusion coefficient is introduced onto the diffusion blocking film. A second semiconductor film to be formed, and the first and second semiconductor films form a lower electrode of the stacked capacitor.

[0007]

In the semiconductor memory device according to the present invention, the first semiconductor film of the lower electrode of the stacked capacitor which is in contact with one diffusion region of the MIS transistor has the first impurity having a relatively small diffusion coefficient. Has been introduced. In addition, the second semiconductor film formed on the first semiconductor film of the lower electrode has a second diffusion coefficient that is relatively large.
Impurities have been introduced. A diffusion blocking film that blocks the diffusion of the second impurities is formed between the first and second semiconductor films.

Therefore, even after the heat treatment process which is the subsequent manufacturing process, both of the first and second impurities are MIS.
It is difficult to diffuse into one diffusion region of the transistor, and the junction of this diffusion region is prevented from becoming deep. Therefore, the contact resistance of the lower electrode is reduced while preventing deterioration of soft error resistance and deterioration of transistor characteristics.

On the other hand, in the lower electrode of the stacked capacitor, the second impurity introduced into the second semiconductor film formed on the first semiconductor film has a relatively large diffusion coefficient as described above. Therefore, the contact resistance of the lower electrode is reduced while preventing the deterioration of the film quality of the capacitor dielectric film formed on the second semiconductor film.

[0010]

EXAMPLE An example of the present invention will be described below. FIG. 1 is a sectional view showing an embodiment of a memory cell of a stacked capacitor DRAM of the present invention. It should be noted that the same reference numerals are given to the portions corresponding to the constituent portions shown in FIG. 2 which is one conventional example described above.

In this embodiment, as shown in FIG. 1, a P-type Si substrate 11 is provided with a polycrystalline Si film 12, WSi _x 13 and side walls 14, and an access transistor 15 having an LDD structure is formed. There is. Where regions 16 and 17
Is a diffusion region of the access transistor 15 in which N type impurities are ion-implanted. Further, the contact hole 1 reaching the diffusion region 16 is formed in the interlayer insulating film 18 formed on the access transistor 15 to have a film thickness of 500 to 100 nm.
9 is perforated.

Next, on the P-type Si substrate 11, a polycrystalline Si film 30 having a film thickness of 100 to 200 nm which contacts the diffusion region 16 is formed. In order to reduce the contact resistance with the diffusion region 16, the polycrystalline Si film 30 contains arsenic at an acceleration energy of 50 to 100 keV at 1 ×.
Ion implantation is performed at a dose amount of 10 ¹⁴ to 1 × 10 ¹⁶ cm ^-2 .

Here, the SiO ₂ film 31 is formed only on the portion of the polycrystalline Si film 30 on the contact hole 19. In order to form the SiO ₂ film 31 having such a pattern, for example, polycrystalline Si is formed by a thermal oxidation method or a CVD method.
A SiO ₂ film 31 is formed on the entire surface of the film 30.
_{2 The} film 31 is processed into the above pattern by the lithography method and the etching method.

After that, a polycrystalline Si film 32 is formed on the polycrystalline Si film 30 to have a film thickness of 100 to 200 nm.
The polycrystalline Si film 32 has 1 × 10 ¹⁹ to 1 × 10 ²¹ c.
Phosphorus is diffused so that the concentration becomes m ^-2 . And
The polycrystalline Si films 30 and 32 form the lower electrode of the stacked capacitor 23.

Stacked capacitor 23 other than lower electrode
The configuration is similar to that of the conventional example. That is, on the lower electrode,
A capacitor dielectric film 21 such as an ONO film having a film thickness of 20 to 30 nm is then a polycrystalline Si film 2 into which N-type impurities are introduced.
2 are sequentially laminated on the entire surface to form a stacked capacitor 23. Further, an interlayer insulating layer 24 is formed on the entire surface of the stacked capacitor 23, and a contact hole 25 reaching the diffusion region 17 is opened. Although not shown, the contact hole 25 reaches the diffusion region 17 through the contact hole 25. The contacting bit line is patterned.

In the embodiment described above, the polycrystalline Si film 30 is used.
Since the diffusion coefficient of the arsenic ion-implanted in the silicon is small, this arsenic will not be removed even after the heat treatment process.
It is difficult to diffuse to the diffusion region 16 via the. Therefore, the junction of the diffusion region 16 is prevented from becoming deep. In addition, polycrystalline S
Although the diffusion coefficient of phosphorus diffused in the i film 32 is large,
The O ₂ film 31 is a diffusion blocking film for phosphorus. Therefore, even after the subsequent heat treatment step, this phosphorus is difficult to diffuse into the polycrystalline Si film 30 and further into the diffusion region 16 via the contact hole 19.

That is, in order to reduce the contact resistance between the lower electrode of the stacked capacitor 32 and the diffusion region 16, arsenic and phosphorus are introduced into the polycrystalline Si films 30 and 32, but these arsenic and phosphorus are introduced. This can prevent the junction of the diffusion region 16 from becoming deep. Therefore, it is possible to reduce the contact resistance of the lower electrode while preventing deterioration of the soft error resistance and deterioration of the characteristics of the access transistor 23.

On the other hand, since the diffusion coefficient of phosphorus diffused in the polycrystalline Si film 32 is large, the contact resistance of the lower electrode can be reduced while preventing the deterioration of the film quality of the capacitor dielectric film 21. Therefore, the stacked capacitor DRAM of this embodiment is excellent in both performance and reliability.

In the present embodiment, the insulating film S is used as a diffusion blocking film for phosphorus diffused in the polycrystalline Si film 32.
Although the iO ₂ film 31 is used, this SiO ₂ film 31 is formed only on a part of the polycrystalline Si film 30. However, if a conductive film is used as the diffusion blocking film, this diffusion blocking film can be formed on the entire surface of the polycrystalline Si film 30.

[0020]

According to the semiconductor memory device of the present invention, in the lower electrode of the stacked capacitor, the first semiconductor film contacting one diffusion region of the access transistor has the first diffusion film having a relatively small diffusion coefficient. 1 impurity has been introduced. A second impurity having a relatively large diffusion coefficient is introduced into the second semiconductor film formed on the first semiconductor film in the lower electrode. A diffusion blocking film that blocks the diffusion of the second impurities is formed between the first and second semiconductor films.

Therefore, even after a heat treatment step which is a manufacturing process thereafter, it is difficult for both the first and second impurities to diffuse into one diffusion region of the access transistor, and it is possible to prevent the junction of this diffusion region from becoming deep. Therefore, it is possible to reduce the contact resistance of the lower electrode while preventing deterioration of soft error resistance and deterioration of transistor characteristics.

In the lower electrode of the stacked capacitor, the second impurity introduced into the second semiconductor film formed on the first semiconductor film has a relatively large diffusion coefficient as described above. Therefore, the contact resistance of the lower electrode can be reduced while preventing the deterioration of the film quality of the capacitor dielectric film formed on the second semiconductor film.

[Brief description of drawings]

FIG. 1 is a side sectional view showing an embodiment of a memory cell of a stacked capacitor DRAM of the present invention.

FIG. 2 is a side sectional view showing a conventional example of a memory cell of a stacked capacitor DRAM.

[Explanation of symbols]

14 Access Transistor 15 Diffusion Region 23 Stacked Capacitor 30 Polycrystalline Si Film 31 SiO ₂ Film 32 Polycrystalline Si Film

Claims (3)

[Claims] 1. A semiconductor memory device having a memory cell composed of one MIS transistor and one stacked capacitor, wherein one diffusion region of the MIS transistor is in contact and the diffusion coefficient is relative. A first semiconductor film formed by introducing a small first impurity into the second semiconductor film, and a second semiconductor film having a relatively large diffusion coefficient on the first semiconductor film.
And a second semiconductor film formed by introducing a second impurity having a relatively large diffusion coefficient onto the diffusion blocking film, the diffusion blocking film being formed to prevent the diffusion of the impurities. A semiconductor memory device, wherein the first and second semiconductor films form a lower electrode of the stacked capacitor. 2. The semiconductor memory device according to claim 1, wherein the diffusion blocking film is an insulating film and is formed on at least a part of the first semiconductor film. 3. The semiconductor memory device according to claim 1, wherein the first impurity is arsenic, and the second impurity is phosphorus.