JPH06150680A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten inspection time by making the maximum repeating number of times of an automatic write-in operation/automatic erasure operation smaller than that of a normal operation at the time of an inspection in a nonvolatile semiconductor memory device capable of performing a write-in and a batch erasure electrically. CONSTITUTION:In a control circuit 7A, a counter 7a capable of counting the repeating number of times of the automatic write-in operation/automatic erasure operation of information to a prescribed maximum repeating number of times and a counter 7b capable of counting the number to less maximum number than the maximum number countable by the counter 7a are provided. Then, the automatic write-in operation /automatic erasure operation are performed by using the counter 7a at the time of the normal mode, and using the counter 7b at the time of the inspection mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device which can be electrically written and collectively erased.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a flash memory as a nonvolatile semiconductor memory device capable of being electrically written and collectively erased. In the figure, the memory cells in the memory cell array 3 are selected in byte units by the X decoder 1 and the Y decoder 2 according to an address signal input from the outside through the address input terminals A _{0 to} A ₁₆ .

Data input from the outside via the data input / output terminals D _{0 to} D ₇ , the sense amplifier / output buffer 4 and the Y gate circuit 5 is written in the selected memory cell in byte unit.

The writing and erasing of data in the memory cell array 3 are executed by the control circuit 7 according to the contents of the command input from the outside to the data input / output terminals D _{0 to} D ₇ and latched in the command latch circuit 6. It

A chip enable signal and an output enable signal externally input to a chip enable circuit and an output enable circuit 8 via a chip enable terminal CE bar and an output enable terminal OE bar, and a write enable terminal WE from the outside. In response to the write enable signal input to the bar, the control circuit 7 can write and erase data.

Then, the control circuit 7 causes the program voltage generator 9 or the erase voltage generator 10 to generate a program voltage or an erase voltage, respectively, and executes writing or erasing within a predetermined time by the timer 10 and ends. Each time, a verify voltage is generated from the verify voltage generating circuit 11 to check the writing or erasing state.

The control circuit 7 executes a write operation or an erase operation according to an external command or automatically according to an external command. Further, the control circuit 7 generates a pulse for each write operation or erase operation, and counts this by the counter circuit 7a inside the control circuit 7 as the number of write operation or erase operation. The maximum number of repetitions of the write operation / erase operation for one byte is fixed at 25/1000 in advance, and is set as the maximum countable value in the counter circuit 7a.

Further, V _PPH (12 V) is applied to the V _PP terminal when writing, erasing and erasing operations are executed.

Next, the operation of the control circuit having the above configuration will be described. First, a case where the write operation / erase operation is executed according to an external operation will be described. A program pulse / erase pulse is input after a write program command / write erase command is input from the outside via the data input / output terminals D _{0 to} D ₇ . The command latch circuit 6 latches those commands and outputs a command to the control circuit 7. The control circuit 7 executes a write operation / erase operation in response to a command from the command latch circuit 6.

Each time the write operation / erase operation by the control circuit 7 is completed, a write program verify command / write erase verify command is input from the outside, and the control circuit 7 checks the write / erase state. If the write / erase state is not sufficient, the command input operation from the outside is repeated until the write / erase state is good, and the control circuit 7 repeatedly executes the write operation / erase operation.

The number of times the write operation / erase operation is repeated by the control circuit 7 is a predetermined maximum value set in the counter circuit 7a, for example, 25/1.
If the write / erase state is not sufficient even in the verification after the 25th / 1000th write / erase operation, the write / erase of the device becomes a failure (failure).

The control circuit 7 has a function of repeatedly executing the write operation / erase operation in response to an external operation until the write / erase state becomes good as described above, and the write operation is automatically performed without the external operation. / Has functions of automatic write operation / auto erase operation that repeatedly executes erase operation.

The automatic write operation by the control circuit 7 is shown in FIG.
This will be described with reference to the flowchart of. First, step s
After 5 V is applied to the V _CC terminal and V _PPH (12 V) is applied to the V _PP terminal in 1, an auto program command is input to the command latch circuit 6 from the outside in step s2, and the command latch circuit 6 controls the control circuit 7. An automatic write command is output.

By this automatic writing command, step s
In 3, the control circuit 7 sets the initial value of the counter circuit 7a to 0, and in step s4, the write data is externally input to the data input / output terminals D _{0 to} D ₇ .

Subsequently, in step s5, the first automatic write operation is started, and in step s6, the write operation is completed, for example, at 10 μs, and then the counter circuit 7a is incremented in step s6.

Subsequently, since the count value of the counter circuit 7a has not reached the maximum value 25 yet, the process proceeds to step s8 through step s7, and the verify is executed to check the write state. If the write condition is good, the device passes the write.

As a result of executing the verify in step s8, if the write state is not sufficient, the write is unsuccessful and the steps s4 to s8 are repeated, and the counter circuit 7a is incremented each time.

When the count value of the counter circuit 7a reaches the maximum value 25 in step s7, the process proceeds to step s10 to execute the verification. As a result, if the write status is good, the device passes the write, and if the write status is not good, the device fails the write.

Next, the automatic erase operation by the control circuit 7 will be described with reference to the flowchart of FIG. First, at step t1, 5 V is applied to the V _CC terminal and V _PPH (12 V) is applied to the V _PP terminal, and at step t2, an command command is input from the outside to the command latch circuit 6 and controlled by the command latch circuit 6. An automatic write command is output to the circuit 7.

Then, at step t3, it is judged whether or not all bytes are written to 00H. If not, then at step t4 all bytes are set to 00H, and at step t5, the start address of the address is set. specify. If all the bytes are 00H in step t3, the process proceeds to step t5.

Subsequently, at step t6, the control circuit 7 sets the initial value of the counter circuit 7a to 0, and at step t7, the first erase operation is started. After the erase operation is completed, for example, at 9.5 ms at step t7, the counter circuit 7a is incremented at step t8.

Then, since the count value of the counter circuit 7a has not reached the maximum value 1000 yet, the process proceeds to step t10 through step t9, and the verify is executed to check the erased state. If the erase condition is good, the device passes the erase.

If the erase state is not sufficient as a result of executing the verify in step t10, the erase fails, and steps t7 to t10 are repeated, and the counter circuit 7a is incremented each time.

When the count value of the counter circuit 7a reaches the maximum value 1000 in step t9, the process proceeds to step t11 to execute the verify. As a result, the device passes the erase if the erase state is good, and the device fails the erase if the erase state is not sufficient.

As described above, in the automatic write operation / automatic erase operation, first, an external autogram command / automatic program /
Control circuit 7 only by inputting auto-laize command
The external operation is very simple because it automatically executes all steps of the write / erase operation.

When performing a test of the automatic write operation / automatic erase operation, the same operation as the above-mentioned normal time is carried out.

[0027]

In the conventional nonvolatile semiconductor memory device, as described above, the number of pulses generated in each automatic write operation / automatic erase operation, that is, automatic write operation /
Counter circuit 7 for counting the number of repetitions of the automatic erase operation
Since the maximum countable value of a is set to a predetermined value and cannot be changed, the maximum value set in the counter circuit 7a must be set if the write / erase does not reach a good state during the test as in the normal state. The write / erase operation is repeated up to the value. Therefore, there is a problem that the test time becomes long.

The present invention has been made in order to solve such a problem, and shortens the test time by making the maximum number of repetitions of the automatic write operation / automatic erase operation smaller than the normal time during the test. An object is to obtain a non-volatile semiconductor memory device that can be used.

[0029]

A non-volatile semiconductor memory device according to a first aspect of the present invention is a non-volatile semiconductor memory device in which information can be electrically written and erased. It has a first counter that counts the number of repetitions during operation up to the maximum number of repetitions, and a second counter that counts up to the maximum number of repetitions that is smaller than the maximum number of repetitions of the first counter. A control means for executing automatic writing or automatic erasing by using the second counter and executing automatic writing or automatic erasing by using the second counter in the test mode is provided.

A non-volatile semiconductor memory device according to a second aspect of the present invention is a non-volatile semiconductor memory device capable of electrically writing and erasing information, and has a maximum number of repetitions during an automatic information writing operation or an automatic erasing operation. Can be set, has a counter for counting the number of repetitions up to the set maximum number of repetitions, and is provided with a control means for executing automatic writing or automatic erasing using this counter.

[0031]

In the non-volatile semiconductor device according to claim 1 of the present invention, the control circuit includes a first counter for counting the number of repetitions during the automatic writing operation or the automatic erasing operation of information up to the maximum number of repetitions in the normal mode. In the test mode, the second counter, which counts up to the maximum number of repetitions smaller than the maximum number of repetitions of the first counter, is used to execute the automatic writing or the automatic erasing.

In the non-volatile semiconductor memory device according to claim 2 of the present invention, the control circuit sets the maximum number of repetitions of the automatic writing operation or the automatic erasing operation of the information to the counter from the outside and sets the maximum repetition number. Up to the number of times, the automatic write operation or the automatic erase operation is counted by the counter.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. Example 1. 1 is a block diagram showing a first embodiment of the present invention. In the figure, for example, the address input terminal A ₁
Is input to the address detection circuit 13 in the X decoder and the high voltage detection circuit 14, and when the input is an address input, 5V is applied from the high voltage detection circuit 14 to the control circuit 7A. Then, the control circuit 7A enters the normal mode in which the normal operation is executed, and its input is the high voltage
_When it is _HH , 0V is applied to the control circuit 7A, and the control circuit 7A enters the test mode in which the test is executed.

In the control circuit 7A, the maximum countable value for one byte is set to, for example, 25 in the automatic write operation and to 1000 in the automatic erase operation in response to the command from the command latch circuit 6 as in the conventional example. In the normal mode, the counter circuit 7a for controlling the number of pulses generated for each write operation / erase operation is used.
The number of repetitions of the erase operation is counted by the counter circuit 7a.

In addition, the control circuit 7A sets the maximum countable value for one byte, which is smaller than 25 in the automatic write operation, to 12, for example, 12 in response to a command from the command latch circuit 6, and sets it to more than 1000 in the automatic erase operation. It has a counter circuit 7a set to a small number, and in the test mode, the counter circuit 7b counts the number of pulses generated for each write operation / erase operation as the number of times of the write operation / erase operation. The other parts than the above-mentioned configuration are the same as those in FIG.

Next, the operation of the control circuit 7A having the above configuration will be described with reference to FIG. First, the time of automatic writing will be described. After 5 V is applied to the V _CC terminal and V _PPH (12 V) is applied to the V _PP terminal in step u1,
In step u2, the high voltage V _HH is input to the address input terminal A ₁ and detected by the high voltage detection circuit 14. The high voltage detection circuit 14 supplies 0V to the control circuit 7A to switch the control circuit 7A to the test mode. As a result, the counter circuit 7b in the control circuit 7A becomes operable.

Then, in step u3, an auto program command is input to the command latch circuit 6 from the outside, and an automatic write command is output from the command latch circuit 6 to the control circuit 7A.

In the control circuit 7A, since the counter circuit 7b is enabled, in step u4, the counter circuit 7b receives the automatic write command from the command latch circuit 6 and executes the automatic write operation similar to that shown in FIG. To do.
However, since the maximum value that can be counted by the counter circuit 7b is set to 12, the automatic write operation for 1 byte is repeated up to 12 times, and if the write state is not sufficient even in the 12th automatic write operation, the device Is a write failure (fail).

As described above, in the test mode, the maximum countable value is set to 12, which is smaller than that in the normal mode. By using the counter circuit 7b, the number of repetitions of the automatic write operation for one byte is counted, thereby performing the test. It takes about half the time required for normal mode.

Also during automatic erasing, as shown in FIG. 2B, after 5 V is applied to the V _CC terminal and V _PPH (12 V) is applied to the V _PP terminal in step v1, in step v2 High voltage V _HH 2 input to address input terminal A ₁
Is detected by the high voltage detection circuit 14 and the high voltage detection circuit 1
0V is supplied from 4 to the control circuit 7A,
Switches to test mode.

After that, in step v3, an auto erase command is input from the outside to the command latch circuit 6 and an automatic erase command is output from the command latch circuit 6 to the control circuit 7A. In step v4, the control circuit 7A performs an automatic erase operation. And the pulse generated for each automatic erasing operation is counted by the counter circuit 7b as the number of repetitions of the automatic erasing operation.

As described above, in the test mode, the maximum countable value is set to be smaller than that in the normal mode. By using the counter circuit 7b, the number of repetitions of the automatic erase operation for one byte is counted, and the test is required. Time is reduced. In the normal mode, the counter circuit 7a is used to count the number of pulses in both the automatic write operation and the automatic erase operation as in the conventional example.

Example 2. In the first embodiment described above, the control circuit 7A is configured to switch to the test mode by applying a high voltage to a specific terminal. However, the test command is input from the outside and the command latch circuit 6 latches the command for test mode. You may switch to.

Example 3. In the first embodiment, the control circuit 7
After A switches to the test mode and the counter circuit 7b becomes operable, the auto program command /
When the auto-laise command is input from the outside, the maximum countable value of the counter circuit 7b is set to a predetermined value smaller than that in the normal mode. On the other hand, in the third embodiment, as shown in FIG. 3A / FIG. 3B, after switching to the test mode at step w2 / step x3 and the counter circuit 7b becomes operable, , arbitrarily set the countable maximum value of the counter circuit 7b from the outside to the counter circuit 7b via the data input-output terminal D ₀ to D ₇ and the command latch circuit 6.

Therefore, in the third embodiment, the number of repetitions of the automatic write operation / auto erase operation for one byte can be made variable according to the maximum countable value of the counter circuit 7b inputted from the outside. You can set the time freely.

Example 4. In the first to third embodiments, the initial value of the counter circuit 7b is fixed to 0 and the upper limit value is changed to change the maximum countable value of the counter circuit 7b. However, the upper limit value of the counter circuit 7b is fixed. The same effect can be obtained even if the maximum countable value of the counter circuit 7b is changed by changing the initial value.

[0047]

As described above, according to the first aspect of the present invention.
The non-volatile semiconductor memory device according to the present invention uses a first counter that counts the number of repetitions during the automatic writing operation or the automatic erasing operation of information up to the maximum number of repetitions in the normal mode. Second, which counts up to the maximum number of repetitions
Since the maximum number of repetitions of the automatic write operation / auto erase operation during the test is smaller than that in the normal mode by configuring the counter to perform the automatic write operation or the automatic erase operation, the test time can be shortened. There is an effect that can be.

Further, in the non-volatile semiconductor memory device according to claim 2 of the present invention, the maximum number of repetitions at the time of the automatic writing operation or the automatic erasing operation of information can be set, and the number of repetitions is counted up to the set maximum number of repetitions. By configuring to execute the automatic write operation or automatic erase operation using the counter, the maximum number of repetitions of the automatic write operation or automatic erase operation can be set to be smaller than that in the normal mode during the test, thus reducing the test time. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a flow chart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a flow chart for explaining the operation of the second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional nonvolatile semiconductor memory device.

FIG. 5 is a flowchart for explaining the operation of the conventional nonvolatile semiconductor memory device.

FIG. 6 is a flowchart for explaining the operation of the conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

 7A control circuit 7a counter 7b counter

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[Procedure amendment]

[Submission date] May 19, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 2

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

A non-volatile semiconductor memory device according to a second aspect of the present invention is a non-volatile semiconductor memory device capable of electrically writing and erasing information, and has a maximum number of repetitions during an automatic information writing operation or an automatic erasing operation. From the outside
It has a counter that can be set to any value and counts the number of repetitions up to the set maximum number of repetitions, and is provided with control means for executing automatic writing or automatic erasing using this counter.

Claims (2)

[Claims] 1. A non-volatile semiconductor memory device capable of electrically writing and erasing information, comprising: a first counter for counting the number of repetitions during an automatic information writing operation or an automatic erasing operation up to a maximum number of repetitions; A second counter that counts up to the maximum number of repetitions that is smaller than the maximum number of repetitions of one counter. In the normal mode, the first counter is used to perform automatic writing or automatic erasing, and in the test mode, the second counter is used. A non-volatile semiconductor memory device comprising control means for executing automatic writing or automatic erasing by using. 2. In a non-volatile semiconductor memory device capable of electrically writing and erasing information, a maximum number of repetitions during an automatic information writing operation or an automatic erasing operation can be set, and the maximum number of repetitions can be repeated. A non-volatile semiconductor memory device comprising a counter for counting the number of times, and a control means for executing automatic writing or automatic erasing using the counter.