JPH07182899A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To enlarge an operation margin by corresponding to a test result and setting the maximum number of times of repetition of automatic write/ erasure. CONSTITUTION:An automatic sequence counter circuit 13A consists of binary counters 31, 32, 33 in cascade connection, and counts the number of times of repetition of the automatic write/erasure, and outputs the repetition stop signal STOP of the automatic write/erasure through a selector circuit 39 if the counted number reaches to the prescribed maximum number of times of repetition, e.g. eight times. At the time of operation test, a voltage higher than a source voltage Vcc by a prescribed value or above is applied as an input signal TT. A high voltage detection circuit 51 detects that, and sends a detection signal TS to a selector control circuit 6. The selector control circuit 6 is provided with a maximum repetition number of times setting means consisting of e.g. fuses, and conducts any one of gates G31, 32, 33 of the selector circuit 39 in response to the setting at the time of receiving the detection signal TS. In an acceleration test for enlarging the operation margin, the maximum number of times of repetition is reduced to e. g. 2, 4 times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, a batch erasing type electrically rewritable and erasable nonvolatile semiconductor memory device (EEPRO) such as a flash memory
M).

[0002]

2. Description of the Related Art As is well known, a flash memory is a batch erasing type EEPROM and is expected as a storage medium replacing a conventional magnetic storage medium as a semiconductor EEPROM having a high degree of integration and a large capacity. There is.

From the viewpoint of ensuring reliability and user friendliness, the flash memory is set with a maximum number of times of writing / erasing, and particularly in a large capacity memory, a program including this maximum number of times of repeating is set. Rewriting operation is generally performed by automatic writing and erasing operations. Further, a verification circuit for automatically verifying whether or not the threshold value of the memory cell after the write / erase operation in the rewrite operation has reached a preset value (hereinafter, verify operation) is provided, When the threshold value reaches the above set value, the write / erase operation is terminated, and when the threshold value is not reached, the write / erase operation is performed again.
The erase operation is performed, and the write / erase operation is repeated until the set value or the maximum number of repetitions is reached.

Referring to FIG. 4 which is a block diagram showing a conventional semiconductor memory device of this type, the conventional semiconductor memory device is supplied with external input signals DATA and CMD and receives a signal S.
Input / output buffer circuit 8 for outputting 0, S1, S3, data latch circuit 9 for receiving signal S0 and outputting signal S7, command controller circuit 10 for inputting signal S1 and outputting signal S2, and signal S2 Supply of signals PST, RETRY, SP0, SP1, and S5, S
6, an auto sequence controller circuit 11 for outputting S8, S9, S21 and a signal P for receiving the signal PST.
Timer circuit 12 for outputting ED and signals ST, RETR
An auto sequence counter circuit 13 which receives the supply of Y and outputs a signal STOP, a writing circuit 14 which receives the signals S6, S7 and SP0 and outputs a signal S12, and a signal S
8, an erase circuit 15 which receives the supply of SP1 and outputs the signal S13, a sense amplifier circuit 16 which receives the supply of the signal S13 and outputs the signals S4 and S19, and a verification which receives the supply of the signal S9 and outputs the signals S10 and S20. The circuit 17, the address buffer circuit 18 which receives the supply of the external input signal AD and outputs the signal S18, and the signal S1 which receives the supply of the signal S18
5, an address latch circuit 19 for supplying S17, and a Y decoder 2 for receiving a signal S15 and supplying a signal S14.
0, which is supplied with signal S17 and outputs signal S16 X
Decoder 21 and signals S11, S12, S14, S16
Is supplied to the Y selector group 22 for outputting the signal S13.
And a memory cell array 23.

Referring to FIG. 5A showing the structure of the auto sequence counter circuit 13, the auto sequence circuit 13 includes an inverter I31 and signals TTi and B, respectively.
A binary counter 31-33 of three stages having a structure shown in FIG. 5B for receiving signals TQi and BQi (i = 1 to 3) supplied with Ti is provided. 31-33 are activated and signal RET
When the set number of RY is counted eight times here, the signal STOP is output.

Referring to FIG. 5B, each of the binary counters 31 to 33 includes an inverter I41 and an inverter I42,
It includes NAND circuits D41 and D42, and transfer gates G41 to G44 each including an N-channel transistor and a P-channel transistor.

Next, the operation of the conventional semiconductor memory device will be described with reference to FIGS. 4 and 5. First, the automatic write operation will be described. The input / output buffer 8 supplies the signal S1 to the command controller circuit 10 in response to the supply of the command signal CMD from the outside. The command controller circuit 10 responds to the supply of the signal S1 with the signal S.
2 is supplied to the auto sequence controller circuit 11. The auto sequence controller circuit 11 uses the signal S
In response to the supply of 2, the signal S5 is sent to the data latch circuit 9,
The signal S21 is supplied to the address latch circuit 19, the signal PST is supplied to the timer circuit 12, and the signals ST and RETRY are supplied to the auto sequence counter circuit 13, respectively. The address latch circuit 19 latches the signal S18 corresponding to the address signal AD from the address buffer circuit 18 in response to the supply of the signal S21, and supplies the signals S15 and S16 to the Y decoder circuit 20 and the X decoder circuit 21, respectively. To do. The Y decoder circuit 20 decodes the signal S15 to generate a Y (digit line) selection signal S14 and supplies it to the Y selector group 22. The X decoder circuit 21 decodes the signal S17, generates an X (word line) selection signal S16, and supplies it to the memory cell array 23.

On the other hand, in response to the supply of the signal S5, the data latch circuit 9 latches the signal S0 corresponding to the external input data DATA supplied from the input / output buffer circuit 8, and the signal S5.
7 is supplied to the writing circuit 14. The auto sequence controller circuit 11 supplies the signal S6 to the writing circuit 14 and simultaneously supplies the signal PST to the timer circuit 12 and the signal S
The T and RETRY are supplied to the auto sequence counter circuit 13, respectively. The write circuit 14 starts the write operation in response to the supply of the signal S6 and outputs the signal S11 corresponding to the signal S7 to Y.
It is supplied to the selector group 22. The timer circuit 12 is for setting the write time per write, counts the time in response to the supply of the signal PST, and supplies the signal PED to the auto sequence controller circuit 11 when the write set time has elapsed. . In response to the supply of the signal PED, the auto sequence controller circuit 11 supplies the write end signal SP0 to the write circuit 14. Write circuit 14 terminates the write operation in response to the supply of signal SP0.

Next, the automatic verification operation will be described with reference to FIGS. 4 and 5 and FIG. 6 showing the operation time chart of the auto sequence counter circuit 13. The auto sequence counter circuit 13 responds to the supply of the signals ST and RETRY. Then, the counting of the number of times of writing is started as follows. First, at the same time when the signal S6 is supplied to the writing circuit 14, the signal ST
Is from "L" to "H", and the signal RETRY is from "H" to "
L ″, respectively, so that the output TQ1 of the binary counter 31 and the output ST of the binary counter 33 are inverted.
OP is inverted from "L" to "H". After the elapse of the write setting time, the auto sequence controller circuit 11 responds to the supply of the signal PED from the timer 12 with the signal R.
Invert ETRY from "H" to "L". At this time, the signals TQ1 and STOP continue to hold "H". at the same time,
The auto sequence controller circuit 11 supplies a signal S9 instructing the start of the verification operation to the verification circuit 17, and the verification circuit 17 responds to the supply of the signal S9 in response to the sense amplifier circuit 1
6, the signal S19 corresponding to the read signal S13 corresponding to the memory cell read operation of 6 is started, the verification operation is started, and the signal S10 reflecting the verification result is sent to the auto sequence controller circuit 11
Supply to. As a result of the above verification, when the threshold value of the memory cell has reached the preset expected value, the auto sequence controller circuit 11 supplies the write end signal SP0 to end the write operation.

When the expected value is not reached, the auto sequence controller circuit 11 again supplies the signal S6 to the write circuit 14, the signal PST to the timer circuit 12, and the signal RETRY to the auto sequence counter circuit 13, respectively. Supply and restart the write operation. At this time, the signal RETR
When Y is again inverted from "H" to "L", the output signal T
Q1 is inverted from "H" to "L", and the signal RETRY is inverted from "L" to "H" again after the write setting time has elapsed. The above-described write / verify operation is repeated, and when the verification result does not reach the expected value again, the third write / verify operation is performed. The signal RETRY is again inverted from "H" to "L", and the output signal TQ1 is inverted from "L" to "H". That is, the binary counter 31 is inverted from "H" to "L" when the write / verify operation is completed twice.
Therefore, the outputs TQ2 and TQ3 of the binary counters 32 and 33 respectively correspond to those of the write / verify operation described above.
The signal STOP corresponding to the output TQ5 which is inverted from "H" to "L" by the completion of the 8th and 8th times and which responds to the completion of the 8th time.
Is inverted from "H" to "L". This signal STOP "
In response to the inversion from H "to" L ", the auto sequence controller circuit 11 finally outputs the signal S indicating the end of the write operation.
Supply P0 to complete the write operation.

As described above, the auto sequence counter circuit 13 fixedly sets the maximum number of repetitions of the write / verify operation according to the number of stages of the binary counter. If the number of stages of the binary counter is N, then the maximum number of iterations is 2
^N times. Similarly, the maximum number of repetitions of the automatic erase / verify operation is fixedly set by the number of stages of the binary counter.

[0012]

In the conventional semiconductor memory device described above, the maximum number of repetitions of the automatic write / erase operation is fixed, so that the automatic write operation against changes in operating environment conditions such as power supply voltage and temperature. The operation margin of the write / erase operation becomes smaller, and if the product shipped as a non-defective product is under the usage conditions of the user near the limit of the above environmental conditions, the automatic write or automatic erase operation is often not completed within the maximum number of repetitions. There is a drawback that it causes a malfunction.

[0013]

A semiconductor memory device of the present invention includes a batch erase type electrical circuit which is internally provided with automatic write / erase operation control means for controlling a sequence of automatic write and automatic erase including a verify operation. In a non-volatile semiconductor memory device capable of rewriting and erasing, the automatic write / erase operation control means is provided with a test mode setting means for a performance confirmation test, and a write and / or erase operation is performed in response to the test result. And a maximum number of repetitions setting means for changing the maximum number of repetitions of the sequence.

[0014]

Embodiments of the present invention will now be described with reference to the drawings. The semiconductor memory device of this embodiment is provided with an auto sequence counter circuit 13A instead of the auto sequence counter circuit 13 in addition to the components 7 to 12 and 14 to 23 similar to those of the conventional example.

Referring to FIG. 1, which is a block diagram showing a part of the configuration of an automatic sequence counter circuit 13A which is a feature of the present invention, the automatic sequence counter circuit 13A is shown.
Includes an inverter I31 similar to the conventional auto sequence counter circuit 13, binary counters 31 to 33, a selector circuit 34 for changing the setting of the count value, a test mode determination circuit 5, and a selector control circuit 6. Is further provided.

The selector circuit 34 includes transfer gates G31 to G33 each composed of an N channel transistor and a P channel transistor.

The test mode determination circuit 5 comprises a high voltage detection circuit 51 and an inverter I51, and outputs a signal TS in response to the supply of the test mode control signal TT. The high voltage detection circuit 51 includes N-channel transistors N51, N
52, a P-channel transistor P51, and inverters I511 and I512, which are supplied with the external signal TT and the power supply voltage VCC and generate an output signal SS2.

Referring to FIG. 2, the selector control circuit 6
Are the same selection signal generation circuits 61 and 62 which generate selection signals F1 and F2 for the selector selection circuit 34 in response to the supply of the signal TS, and inverters I61 to I65 and the NAND gate D61 which are supplied with the selection signals F1 and F2.
To D62, and transfer gates G31 to G3
Transfer gate control signals X1 to X3, Y for selecting 3
1 to Y3 are generated.

The selection signal generation circuit 61 includes an N-channel transistor N61, a P-channel transistor P61, and
It has a fuse E61 and an inverter I66, and has a signal T
In response to the supply of S, the signal F1 corresponding to the interrupted state of the fuse E61 is generated.

Next, the operation of this embodiment will be described with reference to FIGS. 1 and 2. The set value of the maximum number of repetitions of the automatic write / verify operation or the automatic erase / verify operation of this embodiment is changed. The test mode operates when the high voltage detection circuit 51 is supplied with the external input signal TT of the voltage Vin represented by the following equation.

Vin> VCC + VTN + VTP Here, VCC is the power supply voltage, and VTN and VTP are the threshold voltages of the transistors N51 and P51, respectively.

Referring also to FIG. 3 showing the time chart of this test mode, when the voltage Vin of the signal TT is higher than the voltage (VCC + VTN + VTP), the signal S
When S0 is inverted from "L" to "H" and exceeds the inversion level Vj1 of the inverter I511, the signal SS1 changes to the inverter I.
The output signal SS2 drops below the inversion level Vj2 of 512, and the output signal SS2 is also inverted from "L" to "H".

The reason for controlling the test mode by applying the high voltage signal different from the normal logic level is based on the following two reasons. First, since the test mode is a mode used only by the manufacturer, it is desirable to control in a signal mode not used by general users.
The second is that it is less susceptible to input noise and the like as compared with the control method using a normal logic level command or the like.

Next, the mode selection operation will be described. First, in the normal operation mode, the signal TT (VC
A voltage Vin lower than (C + VTN + VTP) is applied.
As a result, the signal SS2 is set to "L", so that the signal T
S becomes "H". Here, for convenience of explanation, the selection signal generation circuit 61 will be described. In response to the supply of the signal TS of "H", the transistor N51 is turned on and the transistor P51 is turned off, so that the output F1 is always "H". . Similarly, the output F2 of the selection signal generation circuit 62 is always "H". As a result, only the transfer gate control signal X3 becomes "H" and the other signals X1 and X2 are "L".
(The signals Y1 to Y3 are complementary signals of the signals X1 to X3). Therefore, only the transfer gate G33 becomes conductive, and the transfer gates G31 and G32 become non-conductive. That is, the binary counter 33 of the third stage is connected to the output signal STOP as in the conventional case. When the automatic write operation instruction command CMD is supplied to the input / output buffer circuit 8, the automatic write operation is started as in the conventional case. The auto sequence counter circuit 13A repeats the above-mentioned automatic write operation eight times, as in the conventional case.
Output TOP.

Next, in the test mode, a voltage Vin higher than (VCC + VTN + VTP) is applied as the signal TT. As a result, the signal SS2 is set to "H" so that the signal TS becomes "L". In response to the supply of the "L" signal TS, the transistor N51 is turned off and the transistor P5 is turned on.
Since 1 is turned on, the output level of the signal F1 changes depending on the disconnection or connection of the fuse E51. When the fuse E51 is cut, the signal F1 becomes "H", and when the fuse E51 is connected, the signal F1 becomes "L". Similarly, in the selection signal generation circuit 62, the signal F2 depends on the interrupted state of the fuse E52. If the fuse E51 is in the disconnected state and the fuse E52 is in the connected state, the signals F1 and F2 are "H" and "L", respectively. As a result, only the transfer gate control signal X2 ″
H "and the other signals X1 and X3 become" L ". Therefore, only the transfer gate G32 becomes conductive and the transfer gates G31 and G33 become non-conductive. That is, the second stage binary counter 32 outputs. When the automatic write operation instruction command CMD is supplied to the input / output buffer circuit 8, the automatic write operation is started in the same manner as described above. When the operation is repeated four times, the end signal STOP is output.

Similarly, when the fuse E52 is in the cut state and the fuse E51 is in the connected state, only the transfer gate control signal X1 becomes "H" and the transfer gate G
Since only 31 is in the conductive state, the binary counter 31 is connected to the signal STOP, so that the auto sequence counter circuit 13A outputs the end signal STOP after repeating the automatic write operation twice.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments and various modifications can be made. For example, the test mode determination circuit and the selector control circuit include a data latch circuit that latches a high voltage signal similar to the test mode signal of the first embodiment, instead of the fuse, and responds to the supply of the test mode signal by the data latch circuit. It goes without saying that supplying a control signal for controlling a predetermined transfer gate to be conductive depending on the voltage level of the data latch circuit can also be applied without departing from the spirit of the present invention.

[0028]

As described above, in the semiconductor memory device of the present invention, the test mode setting means and the maximum number of repetitions for changing the maximum number of repetitions of the automatic write / erase sequence according to the test result are changed. Since the setting means is provided, the operation margin of the product can be made sufficiently large by performing the accelerated test with the maximum number of repetitions of the automatic writing and erasing reduced during the operation test. This is effective in preventing the occurrence of defects.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an auto sequence counter circuit of an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a selector control circuit of FIG.

FIG. 3 is a time chart showing an example of the operation of a test mode determination circuit.

FIG. 4 is a block diagram showing an example of a conventional semiconductor memory device.

5 is a circuit diagram of the auto-sequence counter circuit of FIG.

FIG. 6 is an operation time chart of the auto-sequence counter circuit of FIG.

[Explanation of symbols]

5 Test Mode Judgment Circuit 6 Selector Control Circuit 8 Input / Output Buffer Circuit 9 Data Latch Circuit 10 Command Controller Circuit 11 Auto Sequence Controller Circuit 12 Timer Circuit 13, 13A Auto Sequence Counter Circuit 14 Write Circuit 15 Erase Circuit 16 Sense Amplifier Circuit 17 Verification Circuit 18 Address buffer circuit 19 Address latch circuit 20 Y decoder 21 X decoder 22 Y selector group 23 Memory cell array 31 to 33 Binary counter 34 Selector circuit 51 High voltage detection circuit 61,62 Selection signal generation circuit D41, D42, D61 to D63 NAND gate Q61 Fuse G31 to G33, G41 to G43 Transfer gate I31, I41, I42, I51, I61 to I66, I
511, I512 inverter

Claims (5)

[Claims] 1. A batch erasing type electrically rewritable and erasable non-volatile semiconductor memory device internally provided with automatic write / erase operation control means for controlling a sequence of automatic write and automatic erase including a verify operation. In the above, the automatic write / erase operation control means changes the set number of the maximum number of repetitions of the sequence during the write and / or erase in the test mode with the test mode setting means for the performance confirmation test. A semiconductor memory device comprising: a repetition number setting means. 2. The automatic write / erase operation control means controls the sequence in response to a command supplied from the outside, and a start signal for instructing the start of the sequence and a repeat signal for instructing the repetition of the sequence. And an auto sequence counter circuit that outputs a stop signal when the number of repetitions is counted up to the set number in response to the supply of the start signal and the repetition signal. A circuit having binary counters of first and second stages; and a switch circuit which selectively outputs the output of one of the binary counters of the first and second stages as the stop signal in response to a control signal, A selector control circuit for generating the control signal in response to the supply of the test mode signal; The semiconductor memory device according to claim 1, characterized in that it comprises a test mode decision circuit for setting a test mode in response to preparative signal to generate the test mode signal. 3. The test signal is a first high voltage signal obtained by adding a predetermined voltage to a power supply voltage, and the test mode determination circuit sets a test mode using the first high voltage signal as a threshold value. 3. The semiconductor memory device according to claim 2, further comprising a high-voltage detection circuit that determines whether or not the test mode signal is generated. 4. The first and second fuse means in which the selector control circuit is selectively blown, and the intermittent state of the first and second fuse means in response to the supply of the test mode signal. 4. The semiconductor memory device according to claim 2, further comprising: a logic circuit that generates the control signal. 5. A data latch circuit in which the selector control circuit latches a second high voltage signal obtained by adding a predetermined voltage to a power supply voltage, and a voltage level of the data latch circuit in response to the supply of the test mode signal. 4. The semiconductor memory device according to claim 2, further comprising: a logic circuit that generates the control signal corresponding to.