JPH06149664A - Data transfer control device for information processor - Google Patents

Abstract

PURPOSE:To shorten the processing time of transfer processing whose distance is '0'. CONSTITUTION:An information processor having an instruction execution control part 3 connected to a transferring source storing area 1 and a transferred destination storing area 2 and specifying a transferring source address, a transferred destination address and a distance between data element at the time of transferring data consisting of plural data elements and a transfer control part 4 is provided with a distance '0' detecting means 5, a final address generating means 6 for generating the transferring source address of data to be finally written at the time of detecting distance '0' and a data storing means 7. When '0' is specified as a distance, the control part 3 repeatedly writes only the data to be finally written in the area 2 or data stored in the means 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device for an information processing device, and more particularly, to a transfer source storage area and a transfer destination storage area, and to transfer from the transfer source storage area to the transfer destination storage area at high speed. The present invention relates to a data transfer control device of an information processing device capable of transferring data.

[0002]

2. Description of the Related Art Many information processing apparatuses are provided with a data movement instruction between storage areas, for example, between a memory of a main body apparatus and an extended storage apparatus. In this kind of instruction, the movement of data arranged at a certain interval (distance),
That is, there is one in which a distance access instruction suitable for the interleave method is prepared.

The transfer processing by this kind of instruction is performed in the following procedure. First, in the first transfer processing, as shown in FIG. 5, the data 32 arranged in a continuous area from the specified transfer source address of the transfer area storage area 30 to the specified length is transferred to the transfer destination. In the case where the data element length is moved from the specified transfer destination address of a certain storage area 31 while maintaining the specified distance, in this case, one data element is read from the transfer source address.

Move the data element to the destination address. Add the source address for the length of the data element. Add the transfer destination address by the distance value. If the steps from to are repeated and the designated transfer length is transferred, the instruction is completed. Further, in the second transfer processing, as shown in FIG. 6, when the positions of the transfer source and the transfer destination of the storage area are exchanged and the data transferred to the storage area 31 is transferred to the original storage area 30 according to the above-mentioned procedure. In this case, one data element is read from the transfer source address.

Move the data element to the destination address. Add the destination address for the length of the data element. Add the source address by the distance value. If the steps from to are repeated and the designated transfer length is transferred, the instruction is completed. Data is transferred between the storage areas by such a procedure.

[0006]

By the way, in such an information processing apparatus, there is a specification of the apparatus in which the distance value can be used as 0. At this time, if 0 is specified as the distance value, the above-described processing operates as follows.

In the case of the first processing (FIG. 7) One data element is read from the transfer source address. Move the data element to the destination address. Add the source address for the length of the data element. Add 0 to the transfer destination address. That is, the first transfer destination address remains unchanged. .

If the designated transfer length is repeated by repeating the steps from to, the instruction is completed. In this transfer process, the transfer destination address is always the same,
The result of instruction completion no matter what length (except 0) is specified is that only the last moved data appears to have been moved. That is, the logical significance of the data movement operation other than the last data movement operation is lost, and most of the time required for the data movement operation becomes logically meaningless.

In the case of the second process (FIG. 8) One data element is read from the transfer source address. Move the data element to the destination address. Add the destination address for the length of the data element. Add 0 to the transfer source address. That is, the original address remains unchanged.

When the designated transfer length is repeated by repeating the steps from to, the instruction is completed. Since the transfer source address is constant in this transfer process, the data read from the transfer source is the same no matter what length is given. At this time, it is meaningless to read the data from the transfer source every time, and there is a problem that most of the time required for the data moving operation becomes logically meaningless.

Further, such a transfer process, a so-called cache memory that is conventionally provided in a CPU, has a large amount of data movement, so that replacement of cache entries frequently occurs. For example, when transferring data from main memory to expanded memory, CP
The ratio of data used by U for processing is generally low, and as a result, it is possible to significantly reduce the hit rate of the cache memory in the processing after data movement. The read access by the instruction is performed on the storage area where all the read operations are performed. Therefore, in the case of the example shown as the above-mentioned second processing, useless processing is performed over a very long time.

Therefore, an object of the present invention is to provide a data transfer control device of an information processing device capable of shortening the processing time of a transfer process with a distance of zero.

[0013]

In the present invention, the first means for solving the above problems has a transfer source storage area 1 and a transfer destination storage area 2 as shown in FIG. ,
When transferring data consisting of one or a plurality of data elements from the transfer source storage area 1 to the transfer destination storage area 2, a transfer source address that specifies the first address of the data to be transferred in the transfer source storage area 1, and a transfer destination A transfer destination address that specifies the first address of the storage area 2, a distance (interval) that specifies the distance between data elements at the transfer destination, and a length (transfer length) that specifies the total transfer amount of data are specified. The instruction execution control unit 3 and the data arranged in a continuous area from the specified transfer source address of the transfer source storage area 1 to the specified length are transferred from the specified transfer destination address of the transfer destination storage area 2 to the data. In an information processing device having a data transfer control unit 4 that moves a designated distance by element length, it is detected that the designated distance is 0. The distance 0 detection unit 5 and the final address generation unit 6 that generates the transfer source address of the data to be written last when the distance 0 detection unit detects the distance 0 have the data transfer control unit 3 as a distance. When it is detected that 0 is specified, only the last data to be written is moved,
It is to end the process.

In the present invention, the second means has a transfer source storage area and a transfer destination storage area, as shown in FIG. 1, and one or a plurality of transfer source storage areas are provided in the transfer destination storage area. When transferring the data consisting of the data elements, the transfer source address that specifies the first address of the data to be transferred in the transfer source storage area 1, the first transfer destination address in the transfer destination storage area 2, and the transfer source data An instruction execution control unit that specifies a distance that specifies the distance between elements (an interval and a length (transfer length) that specifies the total amount of data transferred,
Data elements stored at a specified distance from the specified transfer source address in the transfer source storage area 1 are sequentially read out, and as continuous data over the specified length from the transfer destination address in the transfer destination storage area 2. In the information processing apparatus having the data transfer control unit 3 to be moved, the distance 0 detection unit 5 for detecting that the designated distance is 0, and the distance 0 detection unit first from the transfer source area when the distance 0 is detected. The data transfer control unit 3 has a data holding unit 7 that holds the content of the read data element, and the data transfer control unit 3 ends the processing by repeatedly writing the held data element from the designated transfer destination address over the designated length. It is to let.

[0015]

According to the first means of the present invention, the instruction execution control unit 4 controls the execution of the data movement process. The transfer source address, the transfer destination address, the length, and the distance are sent to the data transfer control unit 3, and the data transfer control unit 3 executes the process of moving the data from the designated transfer source storage area to the transfer destination storage area. .

When the instructed data movement processing is completed, the data transfer control section 3 reports a processing end signal to the instruction execution section 4. The instruction execution unit 4 determines that the series of processing has been completed due to the arrival of the instruction, and moves to the next instruction processing. The distance output from the instruction execution unit to the data transfer control unit is input to the distance 0 detection means 5. When the distance 0 detection means 5 detects the distance value = 0, a control signal indicating that is generated, and the final address generation means 6 is transmitted.

The transfer source address, the transfer destination address, and the length are also input to the final address generating means, and the final address generating means 6 outputs the final transfer source address obtained to the data transfer control unit 3. At this time, the length is 1 unit and the distance is 0. By this instruction, as shown in FIG. 2, only the data element at the final address of the transfer source is transferred.

When the transfer is completed, the data transfer control unit 3 sends a processing completion signal to the instruction execution unit 4, and the instruction execution control unit moves to the next instruction processing. Next, the operation of the second means of the present invention will be described. If the distance sent from the instruction execution unit 1 is 0, the data transfer control unit 3 sets the data element of the address specified by the data transfer source address from the transfer source storage area 1 to 1 as shown in FIG. The data is read only once, the data is held in the data holding means 7, and transferred to the address designated by the data transfer destination address in the data transfer destination storage area 2. For the next data, the data held in the data holding means 7 without being read from the transfer source storage area 1 is supplied,
Data is transferred to the transfer destination storage area by the specified transfer length.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data transfer control device of an information processing apparatus according to the present invention will be described below with reference to the drawings. FIG. 4 shows an embodiment of the data transfer control device of the information processing apparatus according to the present invention. This embodiment has a configuration that realizes both the first and second means. Further, in the present embodiment, both have a storage area X24 and a storage area Y which are a transfer source and a transfer destination of data.

In the figure, a command code, a transfer destination address, a transfer source address, a length, and a distance are sent from an instruction execution control unit (not shown). In the figure, 11 and 12 are decoders for decoding command codes,
13 indicates that the decoder 12 decodes the command code,
When it is an instruction corresponding to the means of, the transfer source address, the length, the distance and the data element length,
The final transfer address is obtained based on [source address + (length / data element length) × distance] and is output together with the length = 1 signal. The final address generation mechanism is a final address generation mechanism, and 14 is a NOR of all bits of the distance. If the logic is taken and all bits are 0
a NOR gate, which is a distance 0 detecting means for generating the nce = 0 signal, 15 is an AND gate for outputting a logical product of the Distance = 0 signal and the length = 1 signal, 1
6 is an AND gate that outputs the logical product of the inversion signal of the Distance = 0 signal and the length, 17 is an OR gate that outputs the logical sum of the outputs of both AND gates 15 and 16, and 18 is the Distance = 0 signal and the final transfer source address An AND gate that outputs a logical product, 19 is Distance
An AND gate that outputs a logical product of the inverted signal of the = 0 signal and the transfer source address, and 20 represents an OR gate that outputs a logical sum of the outputs of both AND gates 18 and 19. Further, reference numeral 21 forms a part of the data transfer control unit, and the decoder 1
1. Store control for inputting the outputs and distances of the OR gates 20 and 21 and controlling storage of data in both storage areas 23 and 24. Reference numeral 22 forms a part of the data transfer control unit, and the decoder 11 and the OR gates 20 and 21. Output and distance are input, and both storage areas 23 and 2
4 shows the fetch control for performing the fetch control of the data of No. 4. Further, in the present embodiment, the fetch control 22 is provided with a data element holding mechanism 25 which is a data holding means and which stores a data element when the second means is executed.

According to the present embodiment, the command code from the instruction execution control section is decoded by the decoder 12, and if this is an instruction corresponding to the first means, the final address generation mechanism 13 is activated to set the final transfer source address. Ask for. For the distance, NOR logic of all bits is taken from the NOR gate 14, and if all bits are 0, a Distance = 0 signal is generated.

The transfer source address and length are Di
AND gate 16,1 if stanc = 0 signal is 1
9, the final transfer address sent from the final address generation mechanism 14 is output as the transfer source address, and the length = 1 is output as the length through the AND gates 15 and 18 to the store control 21 and the fetch control 22. To be done.

Here, the decoder 12 is a part of the data transfer control mechanism, and operates the store control 21 and the fetch control 22 according to each command code.
If the instruction specification does not guarantee the read order and the write order of the move data but only the transfer result at the time when the data transfer is completed, the final transfer address generation mechanism 14 uses a particularly strict address. It is not necessary to generate, and it is sufficient to generate an appropriate address within a range that does not violate the instruction specifications, such as simply generating length = 1.

Next, the operation of this embodiment will be described. When the instruction to activate the first means is executed, the decoder 11 causes the store control 21 as well as the fetch control 22.
In addition, the decoder 12 outputs the analysis result to the final address generation mechanism 13. Then, the final address generation mechanism 13 outputs the final transfer address. Further, the Distance = 0 signal is output from the NOR gate 14 and is input to the AND gates 15, 16, 18, and 19, and the final transfer source address, the transfer destination address, and the length = 1 are stored in the store control 21 and the fetch control 22. As shown in FIG. 2, only the data having the data element length of one unit from the final transfer address of the transfer source storage area (for example, the storage area Y21) is transferred to the transfer destination storage area (for example, the storage area X24) and processed. To finish.

Further, when the instruction for executing the second means is instructed by the instruction code and the distance = 0, as shown in FIG. 3, the fetch control 22 has the transfer source storage area (for example, the storage area X24). ), The data of the data element length of one unit stored is read out and sent to the store control 21. The data is also stored in the data element holding mechanism 25. Then, the store control 21 stores the transfer destination storage area (for example, the storage area Y21).
Store the data in. Furthermore, fetch control 2
2 does not read the next data from the transfer source storage area, reads the data from the data element holding mechanism 25 and supplies it to the store control 21, and the store control 21 uses the data specified by the length specified in the transfer destination storage area. Store the element and end the process.

[0026]

As described above, according to the present invention,
In the data transfer control device of the information processing device, in the distance access process, the instruction can be completed at high speed without performing the wasteful data movement operation when the length is designated as 0, so that the speed of the information processing device is greatly increased. The effect that it can contribute is produced. .

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing the operation of the first means according to the present invention.

FIG. 3 is a diagram showing the operation of the first means according to the present invention.

FIG. 4 is a diagram showing an embodiment of a data transfer control device of an information processing device according to the present invention.

FIG. 5 is a diagram showing an example of the operation of a data transfer control device of a conventional information processing device.

FIG. 6 is a diagram showing an example of the operation of a data transfer control device of a conventional information processing device.

FIG. 7 is a diagram showing an example of an operation in the case of a distance 0 of a data transfer control device of a conventional information processing device.

FIG. 8 is a diagram showing an example of an operation in the case of a distance 0 of the data transfer control device of the conventional information processing device.

[Explanation of symbols]

 1 Transfer-source storage area 2 Transfer-destination storage area 3 Data transfer control section 4 Instruction execution control section 5 Distance 0 detection means 6 Final address generation means 7 Data holding means

Claims (2)

[Claims] 1. A transfer source storage area (1) and a transfer destination storage area (2) having one or a plurality of data elements from the transfer source storage area (1) to the transfer destination storage area (2). When transferring data, a transfer source address that specifies the first address of the data to be transferred in the transfer source storage area (1), and a transfer destination address that specifies the first address of the transfer destination storage area (2),
An instruction execution control unit (3) that specifies a distance (interval) that specifies a distance between data elements at a transfer destination and a length (transfer length) that specifies a total transfer amount of data, and a transfer source storage area (1 ), The data arranged in the continuous area from the specified transfer source address to the specified length is transferred from the specified transfer destination address of the transfer destination storage area (2) to the specified distance for each data element length. In an information processing device having a data transfer control unit (4) for keeping and moving, a distance 0 detection unit (5) for detecting that a designated distance is 0 and a distance 0 detection unit (5) detect a distance 0. And a final address generating means (6) for generating a transfer source address of the data to be written last when the data transfer control unit (3) A data transfer control device of an information processing device, which moves only the last data to be written when it is detected that 0 is designated as a drawer and ends the processing. 2. A transfer source storage area (1) having a transfer source storage area and a transfer destination storage area, and when transferring data consisting of one or a plurality of data elements from the transfer source storage area to the transfer destination storage area. ), The transfer source address that specifies the first address of the data to be transferred, the first transfer destination address of the transfer destination storage area (2), and the distance that specifies the distance between the transfer source data elements. An instruction execution control unit that specifies the length (transfer length) that specifies the total transfer amount of data, and a data element that is stored with the specified distance from the specified transfer source address in the transfer source storage area (1). To a data transfer control unit (3) for sequentially reading out and moving as continuous data over a specified length from the transfer destination address of the transfer destination storage area (2). The distance 0 detecting means (5) for detecting that the designated distance is 0, and the data holding for holding the contents of the data element first read from the transfer source area when the distance 0 detecting means detects the distance 0. Information including a means (7), wherein the data transfer control unit (3) ends the processing by repeatedly writing the held data element from the specified transfer destination address over the specified length. A data transfer control device of a processing device.