JPH06149430A - Interface circuit - Google Patents

Abstract

PURPOSE:To provide the interface circuit for small amplitude which is miniaturized and reduces energy consumption. CONSTITUTION:A pulse generation circuit 6 generates a one-shot pulse signal P in response to logic data D1 outputted from a logic circuit 11 for data transmission/reception. A pulse width TP of the pulse signal is set at a certain value sufficiently shorter than the minimum cycle of transmitting/receiving data. A storage circuit 17 temporarily stores an output signal D2 of a differential comparator 8 in response to a received clock W outputted from the logic circuit 11 for data transmission/reception.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit, and more particularly to an interface circuit suitable for an input / output interface for a small amplitude whose signal amplitude is 1V or less.

[0002]

2. Description of the Related Art In recent years, as the speed of MPUs, memories, etc. has increased, the need for input / output interfaces capable of high-speed transmission has increased. However, in conventional TTL level transmission, there is a limit to speeding up due to noise such as reflection. Therefore, a low amplitude level such as the ECL level is adopted, and a small amplitude input that enables speeding up and low power consumption is achieved. Output interfaces are beginning to be proposed.

This means that noise such as reflection is suppressed by matching-terminating the transmission line, and the transmission line is charged and discharged at a high speed by making the amplitude small, thereby further increasing the speed of each dramba. The circuit configuration is intended to achieve low voltage and low power consumption.

Regarding such a small-amplitude input / output interface, for example, US Pat. No. 5,023,488 is used.
Issue, Nikkei Electronics June 8, 1992 issue, 1st
33 to 136 pages and the like.

FIG. 10 shows a transmission line 3 whose both ends are connected to a fixed potential via resistors for matching termination, and a conventional logic circuit network 100 which mutually transmits and receives binary data via the transmission line 3. FIG. 2 is a diagram showing a configuration, and the logic circuit network includes an input / output interface for transmitting / receiving data to / from the transmission line 3.

In the figure, one end of a terminating resistor 2 for matching termination is connected to both ends of the transmission line 3, and the other end of the terminating resistor 2 is connected to a terminating voltage 1 (1.2 V). The transmission line 3 includes a plurality of logic circuits 100 (100-1 to 100-1).
00-n) are connected. Each logic network 100 is
An open drain N-channel MOS transistor 4 (hereinafter simply referred to as NMOS) connected between the transmission line 3 and the ground potential, a differential comparator 8, a drive circuit 51,
And a data transmission / reception logic circuit 11 and is usually integrated as a VLSI.

The inverting input terminal of the differential comparator 8 is the transmission line 3
Connected to the reference voltage Vref (0.8
V) is input. A transmission permission signal TEN is input to the data transmission / reception logic circuit 11, and only the specified logic circuit network 100 is permitted to transmit data to the transmission line 3.

In such a configuration, the logic circuit network 10
When 0 functions as a driver (data transmission end), N
When the "H" level signal is applied to the gate of the MOS4 to turn it on, the transmission line 3 becomes "L" level and the potential of the transmission line 3 becomes the ON output voltage V of the NMOS4.
It becomes OL (0.4V).

On the other hand, when an "L" level signal is applied to the gate of the NMOS 4 to turn it off, the transmission line 3 has the same potential as the termination voltage 1 (1.2 V). That is, the signal amplitude on the transmission line 3 is the termination voltage 1 (1.
2V) -VOL (0.4V) = 0.8V, which is a small amplitude.

[0010]

In the above-mentioned prior art, in the logic circuit network 100 which is outputting the "L" level to the transmission line 3, {[terminal voltage 1 (1.2V) -VOL (0.4
V)] / termination parallel resistance 2} x VOL (0.4V) is consumed, and in addition, in the termination resistance 2 of the transmission line 3, {[termination voltage 1 (1.2V) -VOL (0.4V) ] / Terminal parallel resistance 2} × Amplitude (0.8 V) is consumed, which causes a problem of relatively large power consumption.

Moreover, the resistance value of the terminating resistor 2 is around 50Ω, and the ON resistance of the NMOS 4 is a fraction of the terminating resistor 2.
Therefore, the size of the NMOS 4 must be increased. As a result, not only the chip area becomes large, but also a large direct current continues to flow during the period when the transmission data is at the "L" level, resulting in a waste of power.

An object of the present invention is to solve the above-mentioned problems of the prior art and provide a small-sized and low power consumption small-amplitude interface circuit.

[0013]

In order to achieve the above object, according to the present invention, binary data is transmitted and received to and from a transmission line whose both ends are connected to a fixed potential through resistors for matching termination. In an interface circuit that sends and receives data to and from a logic circuit network, a switching element connected between a transmission line and a ground potential and "L" level data is sent from the logic circuit network side to the transmission line side. At this time, means for applying a signal having a pulse width sufficiently shorter than the minimum cycle of transmission / reception data to the switching element to make it conductive, and when transmitting data from the transmission line side to the logic circuit side, the switching element is Means for storing the logic level on the transmission line during the period of continuity.

[0014]

According to the above construction, when transmitting the "L" level data from the logic network side to the transmission line side, the switching element conducts only for a period sufficiently shorter than the minimum cycle of transmission / reception data, and transmits only during this period. The line becomes "L" level.

On the other hand, when receiving data from the transmission line side, the logic level on the transmission line during the period when the switching element is conducting is stored and held.

Therefore, if the stored logical level is treated as received data, the period in which current flows from the fixed potential of the transmission line to the ground side and power is consumed is more than the minimum cycle of transmitted / received data. Since it is only for a short period, the power consumption is greatly reduced.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram for explaining the operation principle of the present invention, and FIG. 2 is a timing chart showing the operation timing of the main part thereof, and the same symbols as those used above represent the same or equivalent parts. ing.

The pulse generation circuit 6 generates a one-shot pulse signal P in response to the logic data D1 output from the data transmission / reception logic circuit 11. The pulse width TP of the pulse signal P is set to a value sufficiently shorter than the minimum cycle of transmission / reception data. The memory circuit 17 temporarily stores the output signal D2 of the differential comparator 8 in response to the reception clock W output from the data transmission / reception logic circuit 11.

In such a configuration, the logic circuit network 10
In the case where 0-1 functions as a driver and the logic circuit network 100-n functions as a receiver, when the output data D1 of the data transmission / reception logic circuit 11 becomes "H" level, the pulse generation circuit 6
Detects the rise of D1 and outputs a one-shot pulse signal P. As a result, the NMOS 4 becomes conductive only during the period TP corresponding to the pulse width of the pulse signal P, so that the transmission line 3 becomes the ON voltage VOL of the NMOS 4 during the period TP.

At this time, in the logic circuit network 100-n functioning as a receiver, the inverting input of the differential comparator 8n becomes "L" level and falls below the reference voltage Vref, so that the output data D2 thereof is "T" only during the period TP. It becomes H "level.

The storage circuit 17n stores and holds the output data D2 of the differential comparator 8n in response to the reception clock W,
This value is used as data D3 for data transmission / reception logic circuit 11
Continue to output to n. Reception clock W of the memory circuit 17n
Is the transmission data from the logic network 100-1 on the driver side.
In order that the data can be reliably received by the logic network 100-n on the receiver side, it is desirable to delay the transmission permission signal TEN by a predetermined time Δt and output it.

The pulse width TP of the transmission pulse signal P, which directly affects the power consumption, allows the transmission data D1 sent to the transmission line 3 to be reliably received as reception data D3 on the receiver side. Set to minimum time.

According to the above configuration, when the "L" level data is transmitted via the transmission line 3, the period during which power is consumed by the logic circuit network 100 functioning as a driver and the terminating resistor 2 is Since it is only the period TP corresponding to the pulse width of the one-shot pulse signal P output from the pulse generation circuit 6, the power consumption can be remarkably reduced as compared with the prior art.

FIG. 3 is a block diagram of the first embodiment of the present invention, in which the same symbols as those used in the previous description represent the same or equivalent portions.

In this embodiment, the pulse generator circuit 6 is
It is characterized in that it is composed of the input NAND circuit 61 and the memory circuit 17 is composed of the inverter 9 and the flip-flop 10.

In the figure, the one-shot pulse signal P1 output in synchronization with the transmission enable signal TEN is input to one input terminal of the 2-input NAND circuit 61, and the other input terminal is used for data transmission / reception. The output data D1 of the logic circuit 11 is input.

The output signal of the differential comparator 8 is input to the data terminal D of the flip-flop 10 via the inverter 9 for level conversion. A pulse signal output in synchronization with the transmission permission signal TEN is input to the clock terminal T of the flip-flop 10 via the inverter 7 having a two-stage configuration. The data output terminal Q of the flip-flop 10 is connected to the data transmitting / receiving logic circuit 11.

In such a configuration, when the logic circuit network 100 functions as a driver, a 2-input NAND is used.
The circuit 61 outputs a pulse signal P corresponding to the logic data D1 output from the data transmission / reception logic circuit 11 in synchronization with the transmission permission signal TEN. As a result, NMOS
4 is turned on for the period TP corresponding to the pulse width of the pulse signal P, the transmission line 3 is N for the period TP as described above.
It becomes the ON voltage VOL of the MOS4.

On the other hand, when the logic circuit network 100 functions as a receiver, a signal corresponding to the level of the transmission line 3 is input to the data terminal D of the flip-flop 10.
Further, since the pulse signal synchronized with the transmission permission signal TEN on the driver side is delayed by the inverter 7 having a two-stage configuration and input as the reception clock W to the clock terminal T, the flip-flop 10 is connected to the data terminal D. The input data can be surely latched, and the stored data can be continuously output even after the data terminal D transits to the “L” level. Here, the input signal to the delay circuit 7 for generating the receive clock W on the receive side is the transmission pulse signal P.
May be

FIG. 4 is a block diagram of the second embodiment of the present invention, in which the same symbols as those used above represent the same or equivalent portions.

In this embodiment, NP is used instead of NMOS4.
The feature is that the N bipolar transistor 41 is used. This is because the NMOS 4 serving as a driver requires a very large drive on-current, and therefore aims to achieve superiority by using a bipolar transistor having a larger driving force.

In this embodiment, since the current continues to be supplied to the base of the NPN bipolar transistor 41 from the PMOS in the CMOS inverter forming the drive circuit 5, the NPN bipolar transistor 41 is connected to the base of the NPN bipolar transistor 41.
The PN41 is saturated and the ON voltage VOL becomes 0V. As a result, in the NPN 41, the power consumption becomes almost zero not only in the non-operating state but also in the operating state.

Further, in the differential comparator 8, its input is N
Since there is a difference between the collector voltage of PN41 and the reference voltage Vref, the noise margin becomes large.

FIG. 5 is a block diagram of the third embodiment of the present invention, in which the same symbols as those used above represent the same or equivalent portions.

In this embodiment, N in the second embodiment is used.
The feature is that a PNP bipolar transistor 42 is provided instead of the PN bipolar transistor 41.

According to this embodiment, as shown in FIG.
Since the bipolar transistor can be similarly formed on the P substrate 80 on which the CMOS is formed, the manufacturing process can be simplified and the device can be downsized.

FIG. 7 is a block diagram of a fourth embodiment of the present invention, in which the same symbols as those used above represent the same or equivalent portions.

The present embodiment is characterized in that the NPN 41 is used instead of the NMOS 4 and that the feedback inverter circuit 53 cuts off the saturated state of the NPN 41 during the ON operation, as described above.

That is, when "L" level data is transmitted to the transmission line 3, the input to the drive circuit 52 is "L", the two-stage PMOS transistor in the drive circuit 52 is turned on, and the input to the NPN 41 is "L". H ”, NPN41
Is on-saturated, and the transmission line 3 has an on-voltage VOL = 0V.

At this time, the feedback inverter circuit 53 turns off the lower PMOS of the drive circuit 52 and sets NP.
Shut off the base current to N41. As a result, NPN4
1 is turned off, and the voltage level of the transmission line 3 becomes the termination voltage 1. At this time, on the receiver side, a means for taking the transmitted data into the data transmission / reception logic circuit 11 so as to be able to receive it or storing it in memory is provided.

8 and 9 are block diagrams of the fifth and sixth embodiments of the present invention, in which the same symbols as those used in the previous description represent the same or corresponding portions.

In each of the embodiments, the NMOS of the prior art described with reference to FIG.
It is characterized in that it is replaced with P42.

In the sixth embodiment of FIG. 8, since the current is continuously supplied from the PMOS in the CMOS inverter forming the buffer 51, the NPN 41 is saturated and the ON voltage VOL is 0.
It becomes V. As a result, in the NPN 41, the power consumption becomes almost zero not only in the non-operating state but also in the operating state.

The input of the differential comparator 8 is NP.
Since there is a difference between the collector voltage of N41 and the reference voltage Vref, the noise margin becomes large.

On the other hand, in the seventh embodiment of FIG. 9, PNP and C
Since the MOS and the P substrate can be formed on the same P substrate,
Miniaturization and simplification of the manufacturing process are achieved.

[0047]

As described above, according to the present invention, it is possible to shorten the period in which power is consumed by the logic circuit network and the terminating resistor when transmitting "L" level data through the transmission line. Therefore, it is possible to significantly reduce the power consumption as compared with the related art.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining the operation principle of the present invention.

FIG. 2 is a timing chart of the main part of FIG.

FIG. 3 is a block diagram of a first embodiment of the present invention.

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is a block diagram of a third embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing method of the third embodiment.

FIG. 7 is a block diagram of a fourth embodiment of the present invention.

FIG. 8 is a block diagram of a fifth embodiment of the present invention.

FIG. 9 is a block diagram of a sixth embodiment of the present invention.

FIG. 10 is a block diagram of a conventional technique.

[Explanation of symbols]

1 ... Termination voltage, 2 ... Termination resistance, 3 ... Transmission line, 4 ... N
Channel MOS transistor, 6 ... Transmission pulse drive circuit, 11 ... Transmission / reception control arithmetic logic circuit, 17 ... Storage circuit

Claims (6)

[Claims] 1. A transmission line, both ends of which are connected to a fixed potential via resistors for matching termination, and a plurality of logic circuits which mutually transmit and receive binary data via the transmission line, In an interface circuit for transmitting and receiving binary data, a semiconductor switching element connected between a transmission line and a ground potential, a pulse signal is input to a specific terminal, and is conductive for a period corresponding to a pulse width, and a logic circuit network. Means for supplying a pulse signal to the semiconductor switching element when transmitting "L" level data from the transmission line side to the transmission line side, and the transmission at the time of supplying the pulse signal when transmitting data from the transmission line side to the logic circuit side Means for storing a logic level on the line, wherein the pulse width of the pulse signal is sufficiently shorter than the minimum cycle of transmission / reception data. Interface circuit of symptoms. 2. The means for supplying a pulse signal to the switching element is a two-input NAND circuit that receives transmission data and a pulse signal as inputs.
The described interface circuit. 3. A means for storing a logic level on the transmission line, wherein a differential comparator for comparing the logic level on the transmission line with a reference signal and an output of the differential comparator are inputted as data, and the pulse is output. 3. The interface circuit according to claim 1, wherein the interface circuit comprises a flip-flop that receives a delayed signal of the signal as a clock. 4. The semiconductor switching element is one of an N channel MOS transistor and a bipolar transistor.
The interface circuit according to any one of 1. 5. A transmission line, both ends of which are connected to a fixed potential via resistors for matching termination, and a plurality of logic circuit networks for mutually transmitting and receiving binary data via the transmission line, In an interface circuit for exchanging binary data, a bipolar transistor connected between a transmission line and a ground potential, and a bipolar transistor which conducts at the time of sending "L" level data from the logic network side to the transmission line side. An interface circuit comprising means and means for detecting a logic level on the transmission line when transmitting data from the transmission line side to the logic circuit network side. 6. The interface circuit according to claim 5, further comprising a feedback inverter circuit for cutting off the saturation operation of the bipolar transistor.