JPH06149195A - Crt display device - Google Patents

Abstract

PURPOSE:To accelerate scrolling in an interlace display screen. CONSTITUTION:A *CBLNK is inputted to a TER/TSR forming part 6 and AND gates 7, 8. The *HSYNC, *VSYNC are inputted to an ODD/EVEN discrimination part 5 and the TER/TSR forming part 6. By the ODD/EVEN discrimination part 5, an *ODD and an EVEN are formed, and are sent to the AND gates 7, 8 respectively. By the TER/TSR forming part 6, a TSR, a TER are formed, and are sent to the AND gates 7, 8 respectively. By the AND gate 7, the inverted *CBLNK and the EVEN and the TSR is ANDed, and is sent to an OR gate 9. By the AND gate 8, the AND of respectively inverted the *CBLNK and the *ODD and the TER is obtained, and is sent to the OR gate 9. By the OR gate 9, the AND of the inputted signals from the AND gates 7, 8 is obtained, and is sent to a D/A converter 3 as a blank signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRT display device capable of screen display by an interlace system.

[0002]

2. Description of the Related Art A conventional CRT display device uses image data stored in a video memory 1 as GS as shown in FIG.
An analog RG is generated by the D / A converter 3 using the control signal of the P (graphic system processor) 2.
It is converted into B signal and displayed on the screen. When the screen display is performed by interlacing with this device, the first half of the first line and the second half of the last line may be displayed as shown in FIG. 9 depending on the type of GSP2.

Therefore, the first line and the last line have been erased from the screen by writing black pixel data in the corresponding positions of the video memory 1. These data writing processes have been conventionally performed by software. As this type of GSP, Ti company's TMS3
4020 (registered trademark) is known.

[0004]

However, when the screen in which the display of the first and last lines is erased is scrolled in this way, the process of erasing the first line and the last line from the screen is a heavy load on the CPU, Therefore, there is a problem that the screen cannot be scrolled at high speed. The present invention has been made to solve the above problems, and an object of the present invention is to provide a CRT display device capable of scrolling at high speed.

[0005]

In order to achieve the above object, the present invention provides an interlaced CRT display device in which the display of the first half of the first line of an even field and the second half of the last line of an odd field is lacking. The circuit that generates the leading line erase signal that is active from the trailing edge of the leading inactive portion of the blanking signal to the trailing edge of the vertical synchronizing signal of the same field, and the horizontal synchronizing signal is counted for each field. A circuit that generates the final line erase signal that is active from immediately before the last line to the field edge, and an even field signal and an odd field display period that activate the even field display section from the vertical sync signal and horizontal sync signal. A circuit that generates an active odd field signal Circuit for converting the leading inactive part in the even field part of the blanking signal from the signal and the even field signal to active, and the final inactive in the odd field part of the blanking signal from the last line erasing signal and the odd field signal And a circuit for actively converting the unit.

[0006]

In the present invention, the leading line erasing signal that is active is generated for each field from the trailing edge of the leading inactive portion of the blanking erasing signal to the trailing edge of the vertical synchronizing signal of the same field. Further, the horizontal sync signal is counted for each field, and a final line erase signal that is active from immediately before the final line to the field end is generated. Further, an even field signal that activates the even field display section and an odd field signal that activates the odd field display section are generated from the vertical synchronization signal and the horizontal synchronization signal.

From the leading line erasing signal and the even field signal thus generated, the leading inactive portion in the even field portion of the blanking signal is converted to active. Similarly, the final inactive portion in the odd field portion of the blanking signal is converted to active from the final line erase signal and the odd field signal. As a result, the first line and the last line of the CRT screen are erased.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. In the figure, the blanking signal * CBLNK output from the GSP 2 is sent to the TER / TSR creating unit 6 and also via the inverter 11 the AND gate 7,
Sent to 8. Similarly, the horizontal sync signal * HSYNC and the vertical sync signal * VSYNC output from the GSP2.
Is sent to the ODD / EVEN discrimination unit 5 and the TER / TSR creation unit 6.

The ODD / EVEN discrimination unit 5 generates an even field signal EVEN and sends it to the AND gate 7, and also generates an odd field signal * ODD and sends it to the AND gate 8 via the inverter 12. TER / TSR
The generation unit 6 generates the head line erase signal TSR to generate AN
The final line erase signal TER is sent while being sent to the D gate 7.
Is generated and sent to the AND gate 8 via the inverter 13.

AND gate 7 is inverted * CBLNK
AND of EVEN and TSR are generated and sent to the OR gate 9. Similarly, the AND gates 8 are each inverted *
The logical product of CBLNK, * ODD and TER is obtained and sent to the OR gate 9.

The OR gate 9 obtains the logical sum of the input signals from the AND gates 7 and 8 and sends it as a blank signal to the D / A converter 3 via the inverter 14. The D / A converter 3 converts the image data sent from the video memory 1 into an analog RGB signal, erases the blanking line, the display of the first and last lines, and then sends the blanked signal to the CRT for display.

FIG. 2 shows the ODD / EVEN discrimination unit 5 of FIG.
3 is a block diagram showing the configuration of FIG. The discriminator 5 includes a delay line 21 and flip-flops (FF) 22 and 23. The video clock signal VCLK is input to the clock input terminal of the FF 22 via the delay line 21, and * VSYNC is input to the input terminal of the FF 22. The inverted output of the FF22 is input to the clock input terminal of the FF23.

The input terminal of the FF23 has * HSY
NC is input. As a result, EVEN is output from the output terminal of the FF 23 and * ODD is output from the inverting output terminal. The EVEN and * ODD have opposite phases, and are inverted at the falling timing of * VSYNC. In addition, delay line 2 is added to VCLK.
The reason for connecting 1 is to delay VCLK because the falling edges of * VSYNC and VCLK are synchronized.

FIG. 3 is a block diagram showing the configuration of the TSR creating section in the TER / TSR creating section 6 of FIG. TS
The R creation unit is composed of the FF 24, and the voltage Vcc is supplied to the input terminal to constantly input the H level. * CBLNK is input to the clock input terminal. * VSYNC is input to the reset input terminal. As a result, TSR is output from the output terminal.

This TSR becomes H level at the fall of the leading pulse for each field of * CBLNK, that is, the timing at which it changes from inactive to active, and is inverted to L level at the fall of * VSYNC.

FIG. 4 is a block diagram showing the configuration of the TER creating unit in the TER / TSR creating unit 6 of FIG. TE
The R creation unit includes a register 25, a counter 26, and an FF 27. A register 25 is connected to the counter 26, and the value set in the register 25 is loaded into the counter 26 while * VSYNC input to the load terminal is at the L level.

The counter 26 counts the * HSYNC pulse, and outputs the ripple carry-out signal RCO after counting up until the next pulse is input and inputs it to the clock input terminal of the FF 27. This FF
The voltage Vcc is supplied to the input terminal of 27 to constantly input the H level, and * VS is input to the reset input terminal.
YNC is input. As a result, TER is output from the output terminal.
Is output.

This TER becomes H level at the timing of the falling edge of the * HSYNC pulse corresponding to one line before the final line of each field, and is inverted to the L level at the timing of the falling edge of * VSYNC. In the embodiment, as shown in FIG. 5, the screen of the CRT 4 is composed of eight lines, so the number of lines in the odd display field is half that of four. The number of lines 4 is set in the register 25 and loaded in the counter 26.

FIG. 6 is a timing chart showing a comparison between * HSYNC, * VSYNC and * CBLNK and the waveforms of the signals generated by the above-mentioned sections. The counter value in the figure indicates the count value of the counter 26 in FIG. Further, the blank signal corresponds to the D / A converter 3 in FIG.
This is a blank signal input to.

FIG. 7 is an enlarged timing chart showing the main part of FIG. 6, and the delay output in the figure shows the output of the delay line 21 of FIG.

In this embodiment, the * CBLNK No. output from the GSP2. 0 line and No. The H-level inactive portions corresponding to the 7th line, that is, the leading line of the even field lacking the first half and the final line of the odd field lacking the latter half are each converted to the L-level active. As a result, the display of the leading line of the even field and the final line of the odd field, which were conventionally displayed with half missing, can be completely erased. When the upper and lower lines of the screen are erased by the hardware as described above, the load on the CPU is reduced accordingly, and the screen scrolling can be speeded up.

[0022]

As described above, according to the present invention, the vertical and horizontal synchronizing signals and the blanking signal are combined to form the first inactive portion in the even field portion and the final inactive portion in the odd field portion of the blanking signal. By converting the active part to active, the first line and the last line of the CRT screen are erased. As a result, without relying on software processing as before,
Moreover, since the first line and the last line of the CRT screen are erased at high speed, the load on the CPU is reduced accordingly, and the screen can be scrolled at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an ODD / EVEN discrimination unit of FIG.

FIG. 3 is a block diagram showing a partial configuration of a TER / TSR creation unit in FIG.

4 is a block diagram showing a partial configuration of a TER / TSR creation unit in FIG.

FIG. 5 is an explanatory diagram showing a line configuration of a CRT.

FIG. 6 is a timing diagram showing waveforms of respective signals in comparison.

FIG. 7 is a timing diagram showing an enlarged main part of FIG.

FIG. 8 is a block diagram showing a configuration of a conventional CRT display device.

FIG. 9 is an explanatory diagram showing a configuration of a conventional CRT display screen.

[Explanation of symbols]

 1 Video Memory 2 GSP 3 D / A Converter 4 CRT 5 ODD / EVEN Discrimination Section 6 TER / TSR Creation Section 7, 8 AND Gate 9 OR Gate 11-14 Inverter 21 Delay Line 22-24 Flip-Flop (FF) 25 Register 26 Counter 27 flip-flop (FF)

Claims (1)

[Claims] 1. In an interlace type CRT display device in which the first half of the first line of the even field and the second half of the last line of the odd field are lacking in display, the field from the trailing edge of the first inactive part of the blanking signal is changed from field to field. The circuit that generates the first line erase signal that is active up to the trailing edge of the vertical sync signal and the last line that counts the horizontal sync signal for each field and that is active from immediately before the last line to the field end A circuit that generates an erase signal, a circuit that generates an even field signal that activates the even field display section and an odd field signal that activates the odd field display section from the vertical synchronization signal and the horizontal synchronization signal, and the first line erase signal And the even field signal A circuit for converting the head inactive part in the field part to active, and a circuit for converting the final inactive part in the odd line field of the blanking signal from the final line erase signal and the odd field signal to active. CRT display device characterized by: