JPH06149153A - General purpose high-speed encoding device - Google Patents

Abstract

PURPOSE:To provide the general purpose high-speed encoding device which can selects an optional number of internal rotation stages for FEAL encoding and performs encoding and decoding at a high speed with small hardware. CONSTITUTION:This device includes a key processing part 1 which generates an extended key as a coding key of 64-bit length by inputting an fk function, etc., an extended key register 2 which holds the extended key 5 outputted by the key processing part 1, and a data randomizing part 3 which performs encoding or decoding processing with the input data 7 of a plain sentence or encoded sentence of 64-bit length by exclusive OR, an (f) function 6, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a general-purpose high-speed encryption device, and more particularly to a FEAL (Fa (Fa)
st Data Enclipherment Algorithm: A high-speed general-purpose cryptographic device that performs encryption and decryption at high speed using a high-speed data encryption algorithm.

[0002]

2. Description of the Related Art FEAL-8 cryptographic algorithm (for details, refer to, for example, literature, Miyaguchi, Shiraishi, Shimizu: "FEAL-8 cryptographic algorithm", Research Practical Report, Volume 37, 4/5).
No., pp. 321-327, 1988), the number of internal rotation stages is 8
FEAL-N that can increase the number of selected plaintext attacks
Ciphers have been proposed (for details, refer to, for example, literature: Miyaguchi, Kurihara, Ota, Morita: “Extending FEAL Ciphers”, NTT R).
& D Vol.39, No 10, pp.1439-1450, 1990).

[0003]

[Problems to be Solved by the Invention] However, FEA
Cryptographic devices that perform L-N in hardware at high speed have also not been implemented.

As a method of realizing this FEAL-N (N: internal rotation speed) at high speed, it is necessary to realize it by hardware rather than software. However, it is necessary to implement FEAL-N of all assumed internal rotation speeds by hardware. It is impossible to realize with ware in terms of scale.

The present invention has been made in view of the above points, and in FEAL encryption, an arbitrary number of internal rotation stages can be selected, and general-purpose high-speed encryption capable of executing high-speed encryption and decryption with a small amount of hardware. The purpose is to provide a device.

[0006]

FIG. 1 is a block diagram showing the principle of the present invention.

The general-purpose high-speed encryption device of the present invention uses an encryption key having a 64-bit length in an encryption device using a high-speed data encryption algorithm which is an encryption algorithm used to enhance the security of communication data and computer data. A key processing unit 1 that generates an extended key by inputting an fk function, an extended key register 2 that holds an extended key 5 that is an output from the key processing unit 1, and an input that is a plaintext or a ciphertext having a 64-bit length. The key processing unit 1 includes a data 7 and a data randomizing unit 3 that performs encryption or decryption processing from the output of the extended key register 2 by exclusive OR and f-function 6 or the like.
The output of the k-th (k is a positive integer) fk function, the output of the 2k + 1-th fk function, the buffer that temporarily holds the output of the 2k + 2-th fk function, the output of the 2k + 1-th fk function, the 2k + 2-th output The address of the extended key register 2 that holds the output of the fk function is generated, and the data randomization unit 3 inputs either one of the input data 7 and the output of the 64-bit buffer that temporarily holds the intermediate result of the encryption process. An input selector for selecting, an exclusive OR unit configured by exclusive OR, an encryption processing unit configured by an f-function circuit and exclusive OR, an output of the exclusive OR unit, or An output selector that selects one of the outputs,
It has a 64-bit buffer for temporarily holding the intermediate result of the cryptographic processing which is the output of the output selector, the first and last processing is performed by the exclusive OR section, the intermediate processing is repeated by the cryptographic processing section, The output of the exclusive OR unit or the output of the encryption processing unit is temporarily held, the address of the corresponding extended key register is generated by the encryption or decryption instruction, and the extended key is added to the exclusive OR unit and the encryption processing unit.

[0008]

According to the present invention, when the encryption key is input to the key processing unit,
Generate an extended key and output the extended key to the extended key register.
The extended key register writes the extended key to the address specified in the extended key register and holds the contents, and the data randomization unit extends the input plaintext or ciphertext according to the set number of internal rotation stages. The extended key held in the key register is used for encryption or decryption by exclusive OR and f-function to form data, encryption or decryption, and output of encrypted or decrypted text. By performing a series of these processes, an arbitrary number of internal rotation stages can be selected, and encryption and decryption can be realized with small-scale hardware.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. Hereinafter, "converting plaintext into ciphertext" will be referred to as "encryption", "converting ciphertext into plaintext" will be referred to as "decryption", and the general term for encryption and decryption will be referred to as "encryption".

FIG. 1 is a block diagram showing the configuration of a general-purpose high-speed encryption apparatus using a high-speed data encryption algorithm (FEAL) according to an embodiment of the present invention. This general-purpose high-speed encryption device uses an fk function (f
For the k function, refer to "FEAL-8 encryption algorithm") or the like to generate an extended key, and a 2-port RAM (Random A) that holds the extended key from the key processing unit 1.
ckey (random memory) etc. extended key register 2, input data (plaintext or ciphertext) by exclusive OR and f function (f function will be described later), etc. Encryption unit 3, data line 4 for inputting an encryption key, data line 7 for inputting a plaintext or ciphertext, control line 9 for specifying the number of internal rotation stages, control line 10 for specifying encryption or decryption, ciphertext or plaintext Of the data line 8 for outputting

Generation of an extended key and data randomization will be described below.

(1) Extended Key Generation FIG. 2 is a diagram showing a detailed configuration of the key processing unit and the extended key register according to the embodiment of the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals.

The key processing control unit 10 of the key processing unit 1 controls the entire key processing unit 1 and the writing of the extended key to the extended key register 2 by inputting the number of internal rotation stages from the control line 9. The buffers 11, 12, and 13 are 32-bit buffers that temporarily hold the results during the processing, and hold the contents of input data (plaintext or ciphertext) at the rising edge of the control line 29. In the selectors 14 and 16, the value of the control line 30 is "0".
, The output of the S0 side is output and the value of the control line 30 is "1".
Is a 32-bit wide selector that outputs the input on the S1 side. The AND gate 15 outputs "0" to all the bits when the value of the control line 30 is "0", and outputs the input as it is when the value of the control line 30 is "1". ) It is a gate. Exclusive OR (hereinafter, EOR) gates 17 and 19 are gates that output an exclusive OR (EOR) of two sets of input data (32 bits per set). The fk function circuits 18 and 20 are circuits that realize the logical configuration shown in FIG. 3 by using the function defined by FEAL.

The extended key register 2 is a register for writing the extended key generated by the key processing unit 1 to the address indicated by the address line 31 from the key processing control unit 10, and the input 5 (64 bits) at the rising time of the control line 32. Hold the contents of.

Next, the number of internal rotation stages is set to 32 (N
= 32), the operation sequence of the key processing unit 1 and the extended key register 2 will be described with reference to FIGS. 2, 3, 4, 5, and 6. FIG. 3 is a diagram showing the logical configuration of the fk function.
FIG. 4 is a logical configuration diagram of the key processing unit. FIG. 5 is a timing chart of the operation of the key processing unit according to the embodiment of the present invention.
FIG. 6 is a diagram showing the relationship between the value of the extended key and its address according to the embodiment of the present invention.

Step 1 (see o in FIG. 5) When the 64-bit encryption key is set on the data line 4, the key processing controller 10 sets the control line 30 to "0". As a result, 32 bits on the LSB (least significant bit) side of the input encryption key appear at the output 22 of the selector 14, and 32 bits on the MSB (most significant bit) side of the input encryption key appear at the output 25 of the selector 16. appear. If the control line 30 is "0", the outputs 23 of the AND gate 15 are all "0", and the output 22 of the selector 14 appears at the output 24 of the EOR gate 17.

Hereinafter, the input of the buffer 13 is the output 26 of the fk function circuit 18 (values (K0, K
1)) appears. The selector 1 is connected to the input of the buffer 12.
4 output 22 (value at the location indicated by b in FIG. 4) appears. At the input of the buffer 11, the output 28 of the fk function circuit 20 (values (K2, K3) at the place indicated by c in FIG. 4 appears. Therefore, at the end of this step (o in FIG. 5), the key processing control unit 1
"0" changes the control line 29 from "0" to "1" in order to temporarily hold the input values of the buffers 11, 12, and 13 (see p in FIG. 5).

By this step 1, the processing is performed up to the location of d in FIG.

Step 2 (see q in FIG. 5) The key processing controller 10 sets the control line 30 to "1" and outputs the buffer 13 (K0, K1) and the buffer 1
In order to hold the output (K2, K3) of 1 in the extended key register 2, the key processing control unit 10 outputs the address “0” of the extended key register 2 to the address line 31 (see r in FIG. 5),
The control line 32 is changed from "0" to "1" to write the extended key.
(See s in FIG. 5). Further, the value of the place (K4, K5) shown in f of FIG. 4 appears in the input of the buffer 13, the value of the place shown in e of FIG. The value of the place indicated by d of 4 (K6
K7) appears, and at the end of this step, the key processing control unit 10 controls the control line 29 to temporarily hold the value of the buffer input.
Is changed from "0" to "1" (see t in FIG. 5).

By this step, the processing is performed up to the position of g in FIG.

Step 3 to Step 10 In this step, the same operation as in step 2 is performed. In addition,
Buffer 13, output of buffer 11 and key processing control unit 1
The address value of the extended key register 2 by the address line from 0 is as follows.

[Table 1]

Step 11 (see u in FIG. 5) In this step, the outputs of the buffer 13 and the buffer 11 (K
36, K37, K38, K39) only in the extended key register 2, the key processing control unit 10 outputs the address "9" of the extended key register 2 to the address line 31 (see w in FIG. 5). ), Signal line 3 for writing the extended key
2 is changed from "0" to "1" (see x in FIG. 5).

By performing the above operation, the address of the extended key register 2 and the written extended key become as shown in FIG. FIG. 6 is a diagram showing the relationship between the value of the extended key and its address according to the embodiment of the present invention.

(2) Data Randomization FIG. 7 shows the details of the data randomizing section 3 in FIG.

The data randomization unit 3 is constituted by a data randomization control unit 61 for controlling the entire data randomization unit 3, an input selector 62 for selecting either input data or the output of the buffer 66, and an exclusive OR. An EOR unit 63, an encryption processing unit 64 configured by an f-function circuit and an exclusive OR, an output selector 65 for selecting one of the output of the EOR unit 63 and the output of the encryption processing unit 64, and an intermediate result of the encryption process. It is composed of a 64-bit buffer 66 for temporary holding.

Further, the EOR unit 63 outputs the exclusive OR (EOR) of two sets of input data (16 bits per set), and the value of the control line 69 is "0". It is composed of a selector 87 and a selector 88 each having a 16-bit width, which outputs the input on the S0 side when the value is 1, and outputs the input on the S1 side when the value of the control line 69 is "1".

The encryption processing unit 64 outputs the input on the S0 side when the value of the control line 71 is "0", and outputs the input on the S1 side when the value of the control line 71 is "1". 8 to realize the logical configuration shown in FIG. 8 by using the selectors 91 to 94 and the f function defined by FEAL (for details, refer to “FEAL-8 encryption algorithm”).
The function circuit 95 to f function circuit 98 and EOR gates 99 to EOR gates 102 for outputting the exclusive OR (EOR) of two sets of input data (32 bits per set).

Next, the number of internal rotation stages is set to 32 by the control line 9.
An operation example when the extended key register 2 and the data randomization unit 3 perform encryption and decryption when (N = 32) is designated will be described with reference to FIGS. 8, 9, and 10.

In case of encryption: Step 101 (see γ in FIG. 10) When 64-bit plaintext is set in the data line 7 (see FIG. 1)
Value of 0), the data randomization control unit 61 controls the control line 6
7, 70 are set to "0", and the control line 69 is set to "1". Also, "8" is output to the address line 68 (see λ in FIG. 10). As a result, the output 6 of the extended key register 2 has K
32-K35 appears, and this value and the input plaintext are EO
An exclusive OR is taken by the R gates 81 to 86, and the selector 65
Appears at the output 74 (values at locations indicated by h and i in FIG. 9).
At the end of this step, the data randomization control unit 61 changes the control line 72 from "0" to "1" in order to temporarily hold the intermediate result of the processing (see μ in FIG. 10).

By this step, the processing is performed up to the location of j in FIG.

Step 102 (see δ in FIG. 10) The data randomization control unit 61 sets the control lines 70 and 71 to "1" and outputs "0" to the address line 68. As a result, K0 to the output 6 of the extended key register 2
K3 appears, and this value is processed by the cryptographic processing unit 64 and appears in the output 74 of the selector 65 (values at locations indicated by k and z in FIG. 9). At the end of this step, the data randomization control unit 61
Changes the control line 72 from "0" to "1" in order to temporarily hold the intermediate result of the processing (see τ in FIG. 10).

By this step, processing has been performed up to the location m in FIG.

Step 103 to Step 109 The same operation as Step 102 is performed. The data randomization control unit 61 has the following address values to the extended key register 2 via the address line 68.

[Table 2]

Step 110 (see FIG. 10φ) In this step, the extended key, the buffer 66, and the output are EO.
The data randomization control unit 61 sets the control line 67 to “1” and the control lines 69 and 70 to “0” because the R gates 81 to 86 take the exclusive OR. Also, "9" is output to the address line 68. At the end of this step, the data random “control unit 61 changes the control line 72 from“ 0 ”to“ 1 ”in order to hold the processing result (ciphertext) (FIG. 10).
Η)). As a result, the 64-bit encryption unit appears at the output of the buffer 66 (see ω in FIG. 10).

In the case of decryption: Step 201 When the 64-bit ciphertext is set in the data line 7, the subsequent operation is the same as that of Step 101 in the case of encryption, but the data randomization control unit 61 uses the address line. The difference is that "9" is output to 68.

Step 202 The same operation as Step 101 in the case of encryption,
The data randomization control unit 6 is different in that the control line 71 is set to "0" and that "7" is output to the address line 68.

Step 203 to Step 209 The same operation as Step 202 is performed. In the data randomization control unit 61, the address value of the extended key register 2 by the address line 68 is as follows.

[Table 3]

Step 210: The same operation as Step 110 in the case of encryption,
The difference is that the data randomization control 61 outputs "8" to the address line 68.

This causes the 64-bit plaintext to appear at output 8 of buffer 66.

From the above, the number of internal rotation stages N is P (P is 4
In the above case, the operations of the extended key and the generation and the data randomization in the case of a multiple of 4) can be summarized as follows.

(1) Extended Key Generation The number of steps (SE) required to generate the extended key and store all the extended keys in the extended key register 2 is

[Equation 1] Becomes

The operation of each step will be described below.

Step 301 The same operation as the operation of Step 1 of the extended key generation when the number of internal rotation stages is set to 32 (N = 32) is performed.

Step 302 The same operation as the operation of Step 2 of the extended key generation when the number of internal rotation stages is set to 32 (N = 32) described above is performed.

Step 303 to Step (SE-1) The same operation as Step 302 is performed. The key control unit 1
The address value of the extended key register 2 from 0 to the address line 31 is as follows.

[Table 4]

Final step (step SE) The key processing controller 10 sets the extended key register 2 to the address line 31.
Except for outputting the address "SE-1" of
It is the same as the operation in step 11 of -32.

(2) Data Randomization The number of steps (SD) until the plaintext is input and the ciphertext is output, or the ciphertext is input and the plaintext is output is

[Equation 2] Becomes

The operation of each step will be described below.

In the case of encryption: Step 401 The data randomization control unit 61 sends "P /
4 ”is output, the number of internal rotation stages is 32 (N
= 32), the operation is the same as the operation of step 101 at the time of encryption.

Step 402 The operation is the same as that of Step 102 at the time of encryption when the number of internal rotation stages is set to 32 (N = 32).

Step 403 to step (SD-1)
Up to step 402, the same operation is performed. In the data randomization control unit 61, the address value of the extended key register 2 by the address line 68 is as follows.

[Table 5]

Final step (step SD) The data randomization control section 61 outputs the address value "SD-1" of the extended key register 2 through the address line 68, except for the operation of step 10 of N = 32 described above. It is the same.

Decoding Step 501 The data randomization control unit 61 outputs N (3) described above except that "(P / 4) +1" is output to the address line 68.
When it is set to 2, the same operation as step 101 at the time of encryption is performed.

Step 502 The data randomization control unit 61 sends "(P
/ 4) -1 "is output, and the same operation as step 102 at the time of encryption when N = 32 is performed.

Steps 503 to (SD-
Up to 1), the same operation as step 502 is performed. In the data randomization control unit 61, the address value of the extended key register by the address line 68 is as follows.

[Table 6] Final step (step SD) The data randomization control unit 61 outputs the address value "P / 4" of the extended key register 2 through the address line 68, except that the operation of Step 110 at the time of N = 32 encryption described above. Is the same as.

As described above, according to the present invention, if the number of internal rotation stages is 4 or more and is a multiple of 4, encryption and decryption can be performed easily and at high speed.

[0057]

As described above, according to the present invention, the following effects can be obtained.

If N (the number of internal rotation stages) is 4 or more and is a multiple of 4, the present invention can be applied to any value and is versatile. Therefore, it is also applicable to FEAL-8 with N = 8.

Even if the number of internal rotation stages increases, the hardware amounts of the key processing unit and the data randomizing unit do not change.

The present invention can provide an encryption device which can be easily realized by a small-scale LSI or the like, is inexpensive, has general versatility, and can perform high-speed encryption or decryption.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a diagram showing a detailed configuration of a key processing unit and an extended key register according to an embodiment of the present invention.

FIG. 3 is a diagram showing a logical configuration of an fk function circuit.

FIG. 4 is a logical configuration diagram of a key processing unit.

FIG. 5 is a timing chart of the operation of the key processing unit according to the embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between an extended value value and its address according to an embodiment of the present invention.

FIG. 7 is a detailed diagram of a data randomizing unit according to an embodiment of the present invention.

FIG. 8 is a diagram showing a logical configuration of an f-function circuit.

FIG. 9 is a diagram showing a logical configuration of a data randomizing unit.

FIG. 10 is a timing chart of the operation of the data randomization unit according to the exemplary embodiment of the present invention.

[Explanation of symbols]

 1 key processing unit 2 extended key register 3 data randomizing unit 4 encryption key input 5 extended key 6 output of extended key register 7 data line 8 ciphertext or plaintext 9 control line 10 key processing control unit 11, 12, 13 buffer 14 selector 15 AND gate 16 Selector 17, 19 EOR gate 18, 20 fk function circuit 22 Output of selector 14 23 EOR gate output 24 EOR gate 17 output 25 Selector 16 output 26 fk function circuit 18 output 28 fk function circuit 20 Output 29, 30 Control line 31 Address line 32 Control line 61 Data randomization control unit 62 Input selector 63 EOR unit 64 Cryptographic processing unit 65 Selector 66 Buffer 67 Control line 68 Address line 69, 70, 71, 72 Control line 74 Selector 65 Output 81, 82, 83, 84 , 85, 86 EOR gate 87, 88, 91, 92, 93, 94 selector 95, 96, 97.98 f-function circuit 99, 100, 101, 102 EOR gate

Claims (1)

[Claims] 1. A cryptographic device using a high-speed data encryption algorithm (FEAL), which is an encryption algorithm used to enhance the security of communication data and computer data, is provided with an encryption key having a 64-bit length. A key processing unit that generates an extended key by inputting an fk function set by the encryption algorithm, an extended key register that holds the extended key that is an output from the key processing unit, and a plaintext or a cipher having a 64-bit length. From the input data which is a sentence and the output of the extended key register, the exclusive OR and the function f defined by the high speed data encryption algorithm
And a data randomizing unit that performs encryption or decryption processing by a function or the like, and the key processing unit outputs the 2k-th (k is a positive integer) output of the fk function, the 2k + 1-th output of the fk function, and the 2k + 2-th output. Has a buffer that temporarily holds the output of the fk function of
The address of the extended key register that holds the output of the k + 1-th fk function and the output of the 2k + 2-th fk function is generated, and the data randomization unit temporarily stores the input data or the intermediate result of the cryptographic process in 64 bits. An input selector that selects one of the outputs of the buffers, an exclusive OR unit configured by exclusive OR, a cryptographic processing unit configured by an f-function circuit and an exclusive OR circuit, An output selector for selecting either the output of the logical sum unit or the output of the cryptographic processing unit and a 64-bit buffer for temporarily holding the intermediate result of the cryptographic processing which is the output of the output selector are provided. The final processing is performed by the exclusive OR unit, and the processing in the middle is repeated by the encryption processing unit, and the output of the exclusive OR unit or the output of the encryption processing unit is temporarily held and encrypted. Alternatively, a general-purpose high-speed encryption device characterized by generating an address of a corresponding extended key register according to a decryption instruction and adding the extended key to the exclusive OR unit and the encryption processing unit.